JP4385893B2 - Coefficient interpolation circuit in data processing circuit - Google Patents

Description

  The present invention relates to a coefficient interpolation circuit in a data processing circuit suitable for use in generating a digital musical tone signal.

  When a musical sound signal is generated by digital technology, a digital musical sound signal (PCM (Pulse Code Moduration) data) generated by a tone generator circuit or PCM data received from the outside is input to an effect applying circuit, and an effect ( Effect) and a stereophonic effect. This effect applying circuit is configured to include a plurality of digital filters such as an FIR filter and an IIR filter, and each filter is generally configured by a DSP (digital signal processor).

  As is well known, the DSP has a program RAM (random access memory), a coefficient RAM, a data RAM in which musical tone data is temporarily stored, an arithmetic circuit, and the like, and from the data RAM based on a program in the program RAM. Data is read out, and a filter operation is performed on the musical tone data based on the program read from the program RAM and the coefficient read from the coefficient RAM in the arithmetic circuit. Then, the calculation result is converted into an analog signal by a next-stage DAC (digital / analog converter) and output to a speaker.

Patent documents 1 to 3 are known as conventional technical documents related to the present application.
Japanese Patent No. 2768241 Japanese Patent No. 2727802 JP-A-8-32385

By the way, in the processing of PCM data in the DSP, in order to generate a variety of musical sounds, the coefficient of the arithmetic circuit described above is often changed. This process is performed by rewriting the coefficient RAM with coefficients output from an external CPU (central processing unit). However, if the coefficient RAM is rewritten suddenly, noise may be added to the PCM data. Therefore, two coefficient RAMs are provided, the coefficient to be rewritten is written in the second coefficient RAM, and coefficient interpolation is performed to gradually change the coefficient from the coefficient of the first coefficient RAM currently used to the coefficient of the second coefficient RAM. A circuit is provided. However, in the coefficient change, it is not preferable to gradually change the coefficient by the coefficient interpolation circuit, and there are cases where it is desired to immediately reflect the coefficient change in the calculation.
In addition, the coefficient interpolation circuit using a multiplier conventionally used has a problem that the circuit scale becomes large.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a coefficient interpolation circuit in a data processing circuit that has a simple configuration and can select whether or not to perform coefficient interpolation. .

The present invention has been made to solve the above problems, and the present invention stores a program memory storing a program output from an external control device and a coefficient output from the external control device. In a data processing circuit comprising a coefficient memory and an arithmetic circuit that sequentially reads out a program in the program memory and a coefficient in the coefficient memory in accordance with address data output from a program counter, and operates according to the program and the coefficient. When an external control device is instructed to change the coefficient, a new coefficient memory in which the new coefficient after the change is stored, and when an external control device is instructed to change the coefficient, the old coefficient before the change is The stored intermediate coefficient memory, and sequentially from the old coefficient in the intermediate coefficient memory to the new coefficient in the new coefficient memory Coefficient generating means for generating a coefficient to be converted and interpolation control information indicating whether or not to instruct coefficient interpolation is included in the program, and the interpolation control information included in the program read from the program memory is When coefficient interpolation is instructed, the output of the coefficient generation means is output to the arithmetic circuit, and when the interpolation control information does not instruct coefficient interpolation, the coefficient read from the new coefficient memory is output to the arithmetic circuit. Selecting means for outputting, the coefficient generating means from the data obtained by shifting the new coefficient read from the new coefficient memory in a predetermined bit lower direction before the change read from the intermediate coefficient memory A subtracting means for subtracting data obtained by shifting the old coefficient in the lower direction of the predetermined bit; an adding means for adding the output of the subtracting means and the output of the intermediate coefficient memory; Writing means for writing the output of the adding means into the intermediate coefficient memory; and determining means for determining the number of bits N (N is a positive integer) corresponding to the magnitude of the output of the subtracting means, And an end determination means for determining that the interpolation is completed when the upper N bits of the output of the new coefficient memory coincide with the upper N bits of the output of the addition means, and the selection means includes the end determination The coefficient interpolation circuit in the data processing circuit outputs the coefficient read from the new coefficient memory to the arithmetic circuit when it is determined by the means that the interpolation is completed .

According to a second aspect of the present invention, in the coefficient interpolation circuit, the subtracting means reads the new coefficient read from the new coefficient memory and the intermediate coefficient memory when the result of the subtraction indicates zero. As a result of comparison, +1 is output when the new coefficient is larger than the coefficient, and -1 is output when the new coefficient is smaller than the coefficient .

According to the first aspect of the present invention, when the program read from the program memory instructs the coefficient interpolation, the output of the coefficient generating means is output to the calculating means, and the program does not instruct the coefficient interpolation. In some cases, since the selection means for outputting the coefficient read from the new coefficient memory to the calculation means is provided, it is possible to freely select whether or not to perform the coefficient interpolation.
Further, according to the second aspect of the present invention, the interpolation process can be performed without using the multiplication means, which has the effect of simplifying the configuration.
Further, according to the third aspect of the present invention, there is an effect that it is possible to easily determine whether or not the interpolation is completed.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a musical tone signal generation circuit G using a coefficient interpolation circuit according to an embodiment of the present invention, and FIG. 2 shows a configuration of a mobile phone using the musical tone signal generation circuit G shown in FIG. It is a block diagram. In FIG. 2, reference numeral 1 denotes a CPU (central processing unit) that controls each part of the circuit, and performs normal communication and call processing, as well as game program processing. Reference numeral 2 denotes a ROM (read only memory) in which a program executed by the CPU 1, that is, a communication / call processing program, a game program, a music reproduction processing program, and the like are stored. Reference numeral 3 denotes a non-volatile RAM (random access memory) for data storage, and the CPU 1 temporarily stores data during each process.

4 is an input unit provided with a numeric keypad for inputting a telephone number and various function keys , and 5 is a display unit using a liquid crystal display. A communication unit 6 having an antenna 7 modulates a carrier wave with transmission data and transmits it from the antenna 7, and demodulates an incoming signal received via the antenna 7 and outputs it to the CPU 1 or the audio processing unit 8. The audio processing unit 8 converts the audio signal output from the microphone 9 into digital data, further compresses it and outputs it as transmission data to the communication unit 6, and decompresses the compressed audio data output from the communication unit 6, The sound signal is converted and output to the speaker 10. The musical tone signal generation circuit G generates various musical tone signals such as incoming melody, game effect music, and viewing music, and outputs them to the speaker 16.

Next, the tone signal generation circuit G will be described in detail with reference to FIG.
In FIG. 1, reference numeral 12 denotes a buffer register in which various data and control commands supplied from the CPU 1 via the bus line B are temporarily stored. A tone generator circuit 13 receives an incoming melody generation instruction from the CPU 1 via the buffer register 12, and generates and outputs a digital musical tone signal (PCM data) of the incoming melody. When receiving a game sound effect generation command from the CPU 1, PCM data of the game sound effect is generated and output. The DSP (data processing circuit) 14 gives an effect, a stereophonic effect (3D), and a wide stereo effect to the digital musical sound signal output from the sound source circuit 13 and outputs the signal to the DAC (digital / analog processor) 15. The DAC 15 converts the digital tone signal output from the DSP 14 into an analog tone signal and outputs the analog tone signal to the speaker 16.

  Next, in the DSP 14, 21 is a data RAM, which temporarily stores PCM data output from the tone generator circuit 13, and outputs the stored data to the arithmetic circuit 23 in accordance with a program output from the program RAM 22. The arithmetic circuit 23 performs an operation designated by the program output from the program RAM 22 on the PCM data output from the data RAM 21 and outputs the result. In this case, the coefficient K output from the selector 43 is used as the calculation coefficient. A buffer memory 24 temporarily stores the PCM data output from the arithmetic circuit 23 and outputs it to the DAC 15 at the timing of the clock pulse CLK1. Here, the clock pulse CLK1 is a clock pulse having the same frequency (48 KHz) as the sampling frequency of the PCM data.

The program RAM 22 is a RAM in which an effect program, a stereophonic sound effect program, a wide stereo effect program, and the like are stored in advance, and each program can be rewritten by a program output from the CPU 1.
Each step of each program includes an address of the data RAM 21, an arithmetic instruction to the arithmetic circuit 23, and a 1-bit correction control signal HC.

The program RAM 22 can store a program having a maximum of 768 steps, and each step is sequentially read and output in accordance with address data output from the program counter 27. For example, one or more of an effect program, a stereophonic effect program, a wide stereo effect program, and the like are stored in 768 steps. In accordance with the count output of the program counter 27 supplied to the address terminal, the effect program is read out, whereby an effect is added to the PCM data output from the data RAM 21, or the stereophonic sound effect program is read out next. Or a wide stereo effect program is read out, and thereby the wide stereo effect is added to the PCM data. The program counter 27 is a 768-ary counter, and repeatedly outputs a count output of 0 to 767 in accordance with a clock pulse CLK2 having the following frequency.
Frequency = 48KHz × 768 = 36.864MHz

  31 to 34 are coefficient RAMs for storing calculation coefficients used in the calculation circuit 23. The coefficient RAM (previous stage) 31, the coefficient RAM (new) 32, and the coefficient RAM (middle) 34 are each 768 words (1 Word = 16 bits) and the coefficient RAM (old) 33 has a storage capacity of 768 bytes. Here, the number of bits of the coefficient is 16, so that the coefficient RAM (previous stage) 31, the coefficient RAM (new) 32, and the coefficient RAM (intermediate) 34 can each store 768 coefficients, and the coefficient RAM (Old) 33 can store the upper 8 bits of 768 coefficients. Further, the count output of the program counter 27 is applied to the address terminals of the coefficient RAMs 31 to 34, and data writing / reading is performed with respect to the address specified by the count output of the program counter 27. That is, each coefficient in the coefficient RAMs 31 to 34 corresponds to each program step of the program RAM 22.

Further, the coefficient RAM (previous stage) 31 is rewritten by the coefficient output from the CPU 1, and the coefficient RAM (new) 32 is rewritten by the coefficient output from the coefficient RAM (previous stage) 31. The coefficient RAM (old) 33 is rewritten by the coefficient output from the coefficient RAM (previous stage) 31 or the selector 43. In this case, the input data is switched by the selector 36. The coefficient RAM (intermediate) 3 4 is rewritten by the coefficient output from the coefficient RAM (front) 31 or selector 43. In this case, input data is switched by the selector 37.

  Reference numeral 41 denotes a subtraction circuit, which subtracts the output of the coefficient RAM (old) 33 from the upper 8 bits of the output of the coefficient RAM (new) 32. An adder circuit 42 adds the output of the subtractor circuit 41 and the output of the coefficient RAM (intermediate) 34. The selector 43 selects one of the output of the coefficient RAM (new) 32 or the output of the adder circuit 42 and outputs it to the arithmetic circuit 23 as the coefficient K. The end determination circuit 44 is a circuit that determines the end of coefficient interpolation. Reference numeral 45 denotes an OR gate which outputs the output of the end determination circuit 44 or the interpolation control signal HC output from the AND gate 55 to the selector selection terminal.

The coefficient RAMs 32 to 34, the selectors 36 and 37, the subtraction circuit 41, the addition circuit 42, the selector 43, the end determination circuit 44, and the OR gate 45 constitute the coefficient interpolation circuit 50. When the coefficient is changed, if the coefficient is changed suddenly, noise may be included in the output PCM data. Therefore, the maximum 255 of the clock pulse CLK1 from the coefficient before the change to the coefficient after the change. This is a circuit for gradually changing the coefficient over a clock time.

  Reference numerals 51 and 52 denote a start register and an end register, respectively. When the program is changed, the start address and end address of the program to be changed output from the CPU 1 are written. For example, when the effect program stored in the addresses 0 to 150 of the program RAM 22 is rewritten, “0” is written in the start register 51 and “150” is written in the end register 52. A comparison circuit 54 compares the output of the program counter 27 with the data of the start register 51 and the end register 52. The output of the program counter 27 is between the data of the start register 51 and the data of the end register 52. “1” is output in some cases, and “0” is output in other cases.

  55 is an AND gate (for the number of bits of the output of the program RAM 22). When the output of the comparison circuit 54 is "1", it is closed and data "0 (all bits" 0 ")" (NOP instruction) When the output of the comparison circuit 54 is “0”, the circuit is opened, the program step output from the program RAM 22 is output to the data RAM 21 and the arithmetic circuit 23, and the interpolation control signal included in the program step is output. HC is output to the OR gate 45. Since data “0” is a NOP (No Operation) instruction, malfunction during rewriting can be prevented. (If the NOP instruction is not “0”, the AND gate 55 changes it according to the bit arrangement.)

Next, the operation of the above-described tone signal generation circuit G will be described.
First, it is assumed that an effect program is stored in addresses 0 to 150 of the program RAM 22 and a stereophonic sound effect program is stored in addresses 151 to 767. In this case, the coefficients of the same effect program are stored in the addresses 0 to 150 of the coefficient RAMs 31, 32, and 34, respectively, and the coefficients of the same stereophonic effect program are stored in the addresses 151 to 767, respectively. . The coefficient RAM (old) 33 stores the upper 8 bits of each coefficient in the coefficient RAM (previous stage) 31.

  In this state, for example, when an incoming melody generation command is output from the CPU 1 to the tone generator circuit 13, the tone generator circuit 13 generates a digital musical tone signal (PCM data) of the incoming melody and outputs it to the DSP 14. The outputted PCM data is temporarily stored in the data RAM 21, and at the same time, the program counter 27 starts to count up the clock pulse CLK2. When the program counter 27 counts up with the clock pulse CLK 2, program steps are sequentially output from the program RAM 22 and output to the data RAM 21, the arithmetic circuit 23, and the OR gate 45 through the AND gate 55.

  On the other hand, when the program counter 27 counts up the clock pulse CLK2, the coefficients are sequentially read out from the coefficient RAM (new) 32, the coefficient RAM (old) 33, and the coefficient RAM (intermediate) 34, and the subtraction circuit 41 and the addition circuit. 42 is output. However, as described above, in the state where the coefficient is not changed, the upper 8 bits of the data of the coefficient RAM (new) 32 and the data of the coefficient RAM (old) 33 are the same. Therefore, the output of the subtraction circuit 41 is “0”. " As a result, the output data of the coefficient RAM (intermediate) 34 is output from the adder circuit 42, supplied to the arithmetic circuit 23 via the selector 43, and written to the coefficient RAM (intermediate) 34 via the selector 37.

As described above, when the program counter 27 counts up by the clock pulse CLK2, the program steps read from the program RAM 22 are sequentially added to the data RAM 21 and the arithmetic circuit 23, and read from the coefficient RAM (intermediate) 34. coefficients are applied to the arithmetic circuit 23 through the coefficient interpolation circuit 5 0. Thereby, the effect program and the stereophonic sound effect program are repeatedly executed in sequence. The coefficient read from the coefficient RAM (intermediate) 34 is returned to the coefficient RAM 34 again and written to the same address. Therefore, there is no change in the data of the coefficient RAM (intermediate) 34.

Next, the operation for changing the coefficient will be described.
When the coefficient is changed, first, the changed coefficient (referred to as a new coefficient) output from the CPU 1 is written in the coefficient RAM (previous stage) 31. For example, when the coefficient of the effect program is changed, the new coefficient output by the CPU 1 is written to addresses 0 to 150 of the coefficient RAM (previous stage) 31.

Each time the coefficient in the coefficient RAM (new) 32 is read by the count output of the program counter 27, it is compared with the new coefficient read from the coefficient RAM (previous stage) 31 by the comparator and does not match. The coefficient in the coefficient RAM (new) 32 is rewritten with a new coefficient. The rewritten new coefficient is output to the subtraction circuit 41. The subtracting circuit 41 subtracts 8 bits of the coefficient before change (referred to as old coefficient) output from the coefficient RAM (old) 33 from the higher 8 bits of the new coefficient. The adder 42 adds the subtraction result to the lower 8 bits of the output (16 bits) of the coefficient RAM (intermediate) 34. The sign is extended to the upper bits. FIG. 6 shows a specific configuration example. The subtraction circuit 41 subtracts the input B (8 bits) from the input A (8 bits). The output A-B is 9 bits by adding a sign (SIGN 1 bit) (because it becomes a negative value when B> A). The adder 42 adds the input A (16 bits) and the input B (16 bits). In the input A, the output of the subtracter 41 is input as difference data. The sign (SIGN) is input to 8 bits from the MSB of input A, and the lower order is input to 8 bits below it. That is, the difference data obtained by shifting the output of the subtracter 41 by 8 bits in the lower direction is input to the input A of the adder 42. Here, as is well known, when a binary number is shifted by 8 bits in the lower direction, the binary number is divided by “256”. Therefore, the upper 8 bits of the old coefficient are changed from the upper 8 bits of the new coefficient. subtraction, the adder 42 lower 8 bits input to means that provide the following difference data to input a of the adder 42.
Difference data = (new coefficient−old coefficient) / 256 (1)

The adder circuit 42 adds the above difference data to the coefficient output from the coefficient RAM (intermediate) 34 and outputs the addition result of the following equation (referred to as an intermediate coefficient) to one input terminal of the selector 43.
Intermediate coefficient = old coefficient + difference data (2)
If the interpolation control signal HC included in the program step output from the program RAM 22 is “1” instructing execution of interpolation, the intermediate coefficient is output from the selector 43 and added to the arithmetic circuit 23. It is done. At this time, the selector 37 is switched, and the intermediate coefficient output from the selector 43 is written into the coefficient RAM (intermediate) 34.

Then, (after 768 clock of the clock pulse CLK2) 1 clock after the clock pulse CLK1, the same new coefficients are read from the coefficient RAM (New) 32 Again, the in the subtraction circuit 4 1 (1) subtraction rows The difference data is further added to the intermediate coefficient (old coefficient + difference data) read from the coefficient RAM (intermediate) 34 to the subtraction result, and the next intermediate coefficient is obtained.
Intermediate coefficient = old coefficient + 2 x difference data (3)
The intermediate coefficient is output to the arithmetic circuit 23 via the selector 43 and written to the coefficient RAM (intermediate) 34.

  Thereafter, the same operation is repeated every time one cycle of the clock pulse CLK1 elapses, whereby the intermediate coefficient output from the selector 43 is changed from the old coefficient to the new coefficient as shown in FIG. It increases monotonously (when the difference data is positive) or decreases (when the difference data is negative) at the timing of the clock pulse CLK1 and at the pitch of the difference data.

  When the difference between the intermediate coefficient and the new coefficient becomes smaller than the difference data of the above equation (1), the end determination circuit 44 detects this and outputs an end signal. When this end signal is output, the selectors 36, 37 and 43 are switched, and the new coefficient in the coefficient RAM (new) 32 is written into the coefficient RAM (old) 33 (upper 8 bits) and the coefficient RAM (intermediate) 34. It is. On the other hand, when the coefficient RAM (previous stage) 31 is rewritten by the CPU 1 before the end signal is output, the upper 8 bits of the intermediate coefficient at that time are written in the coefficient RAM (old). As a result, thereafter, as shown in FIG. 3B, the intermediate coefficient sequentially changes from the intermediate coefficient toward a new new coefficient (new coefficient).

  Although the above description is for one address of the coefficient RAMs 31-34, the same operation is performed for the coefficients of other addresses. That is, when a new coefficient is written by the CPU 1 at, for example, addresses 0 to 150 of the coefficient RAM (previous stage) 31, the above-described interpolation processing by monotonically increasing or decreasing is performed for each of the new coefficients at addresses 0 to 150. Is called.

If the upper 8 bits of the old coefficient and the new coefficient match, the subtraction result (difference data) of the subtraction circuit 41 is “0”. In this case, the interpolation does not proceed and the interpolation process does not end. Therefore, when the difference data is “0”, the intermediate coefficient of the coefficient RAM (intermediate) 34 and the new coefficient of the coefficient RAM (new) 32 are compared, and the output of the subtracting circuit 41 is changed according to the result. Thus, it is replaced with +1 or -1.
New coefficient > Intermediate coefficient +1
New coefficient <intermediate coefficient ...- 1
At this time, the time until the end of interpolation varies within the range of 1 clock to 255 clocks with the clock pulse CLK1.

  The above is the details of the interpolation processing in the coefficient interpolation circuit 50. The above-described interpolation processing can be invalidated by setting the program interpolation control signal in the program RAM 22 to "0". That is, when the interpolation control signal is “0”, the “0” signal is output from the OR gate 45 to the selector 43, whereby the selector 43 selects the coefficient output from the coefficient RAM (new) 32, and the arithmetic circuit To 23. As described above, the coefficient RAM (new) 32 is a RAM in which the latest coefficient is always written. Therefore, when the interpolation control signal is “0”, coefficient interpolation is not performed, and the latest coefficient is calculated by the arithmetic circuit 23. Supplied to.

Next, the case of program change will be described with reference to the flowchart of FIG. When changing the program, the coefficients are usually changed.
When the program and coefficient are changed, the CPU 1 first outputs data specifying the rewrite range. The output data is written into the start register 51 and the end register 52 (step S1). For example, when the effect program is rewritten, the CPU 1 outputs the address 0 and the address 150, and these addresses are written in the start register 51 and the end register 52. When the start register 51 and the end register 52 are written, “1” is output from the comparison circuit 54 when the output of the program counter 27 is between the start address and the end address. All bits "0" (NOP instruction) are output from (step S2).

  When the program and the coefficient are changed, the selectors 36 and 37 are switched, and the output of the coefficient RAM (previous stage) 31 is written in each of the coefficient RAMs 32 to 34. That is, the coefficient interpolation process in the coefficient interpolation circuit 50 is not substantially performed (step S3).

  Next, the CPU 1 outputs a new program and a new coefficient. The output new program is written into the program RAM 22, and a NOP instruction is output from the AND gate 55 during this writing. Therefore, the arithmetic circuit 23 does not output an abnormal output during writing. Further, the new coefficient output from the CPU 1 is written in the coefficient RAM (previous stage) 31 and then written in the coefficient RAMs 32 to 34 (step S4). When the writing of the coefficient RAMs 32 to 34 is completed, the start register 51 and the end register 52 are cleared (step S5), and thereafter, a new program is output from the AND gate 55. In addition, new coefficients are output from the coefficient RAMs 32 to 34 in synchronization with the new program, but these are the same coefficients. Therefore, the output of the subtraction circuit 41 becomes “0”, and the old coefficients in the coefficient interpolation circuit 40 are changed. Interpolation to the new coefficient is not performed. As a result, when the program is changed, it is possible to prevent the inconvenience that the interpolation process is performed between the coefficient before the change and the coefficient after the change.

Next, the operation of the end determination circuit 44 will be described in detail with reference to FIG.
As described above, when the difference between the intermediate coefficient output from the adder circuit 42 and the new coefficient output from the coefficient RAM (new) 32 becomes equal to or less than a predetermined value, the end determination circuit 44 outputs an end signal to the OR gate 45. To the selector 43. The reason why such an end determination circuit 44 is provided is that the difference data output from the subtraction circuit 41 is the difference between the upper 8 bits of the new coefficient and the upper 8 bits of the old coefficient, so that the difference data is sequentially added to the old coefficient. This is because the addition result does not always coincide with the new coefficient. Here, as is naturally predicted, the constant value is larger as the difference data that is the difference between the new coefficient and the old coefficient is larger, and is smaller when the difference data is small. Therefore, when the difference data is large, it can be determined that the difference between the new coefficient and the intermediate coefficient is less than a certain value if the higher bits of the new coefficient and the intermediate coefficient match. If the number of bits counted from the higher order does not match, it cannot be determined that the difference between the new coefficient and the intermediate coefficient has become a certain value or less.

  The end determination circuit 44 is formed according to this idea. That is, if the difference data is +128 to +255, if the upper 8 bits of the new coefficient and the intermediate coefficient match, the difference data will be +128 to +255 or less regardless of what the lower 8 bits are. A signal is output. If the difference data is +64 to +127, if the upper 9 bits of the new coefficient and the intermediate coefficient match, the difference data will be +64 to +127 or lower regardless of what the lower 7 bits are, and an end signal is output. The FIG. 5 shows the relationship between such difference data and comparison bits.

The above is the details of one embodiment of the present invention.
According to the above embodiment, whether or not to perform coefficient interpolation can be specified by the coefficient control signal HC in the program, so it is possible to set whether or not to interpolate individually for each coefficient. Thus, it is possible to freely select the coefficient interpolation for the process for suppressing the noise due to the coefficient change and not to perform the coefficient interpolation for the process for improving the followability at the time of the coefficient change.

  Further, after the coefficient interpolation is completed or when the coefficient interpolation is not performed, the coefficient transfer from the coefficient RAM (previous stage) 31 to the coefficient RAM (old) 33 and the coefficient RAM (middle) 34 is stopped, or the coefficient RAM (old) 33, by stopping the coefficient reading of the coefficient RAM (intermediate) 34, the power can be saved.

  Further, according to the above-described embodiment, coefficient interpolation is performed by difference calculation after data shift without using a multiplier. When the data shift is performed after the difference calculation, the coefficient length is 16 bits, and when the interpolation is completed in 256 steps, it is necessary to store all 16 bits in the coefficient RAM. However, if the difference calculation is performed after the data shift, the lower 8 bits that are known to be discarded after the shift are unnecessary from the beginning, and it is only necessary to have the coefficients for the upper 8 bits. There is.

  The present invention is used for generating ringtones and game sound effects in a portable terminal.

It is a block diagram which shows the structure of the musical tone signal generation circuit G to which the coefficient interpolation circuit by one Embodiment of this invention is applied. 3 is a block diagram showing a configuration of a mobile phone using the musical tone signal generation circuit G. FIG. FIG. 6 is a diagram for explaining the operation of the music signal generation circuit G. 4 is a flowchart for explaining the operation of the musical tone signal generation circuit G. It is a figure for demonstrating operation | movement of the completion | finish determination circuit 44 in the same tone signal generation circuit G. 4 is a circuit diagram showing in more detail the configuration of coefficient RAMs 32 to 34, a subtracting circuit 41, and an adding circuit 42 in the musical tone signal generating circuit G. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... CPU, 12 ... Buffer register, 13 ... Sound source circuit, 14 ... Data processing circuit (DSP), 21 ... Data RAM, 22 ... Program RAM, 23 ... Arithmetic circuit, 24 ... Buffer memory, 27 ... Program counter, 31 ... Coefficient RAM (previous stage), 32 ... Coefficient RAM (new), 33 ... Coefficient RAM (old), 34 ... Coefficient RAM (middle), 36, 37, 43 ... Selector, 41 ... Subtractor circuit, 42 ... Adder circuit, 44 ... End determination circuit, 50... Coefficient interpolation circuit.

Claims (2)

A program memory in which a program output from an external control device is stored;
A coefficient memory in which coefficients output from an external control device are stored;
In accordance with address data output from a program counter, a data processing circuit comprising: an operation circuit that sequentially reads out a program in the program memory and a coefficient in the coefficient memory and operates according to the program and the coefficient;
A new coefficient memory for storing a new coefficient after the change when the change of the coefficient is instructed from an external control device;
When instructed to change the coefficient from an external control device, an intermediate coefficient memory in which the old coefficient before the change is stored;
Coefficient generating means for generating a coefficient that sequentially changes from an old coefficient in the intermediate coefficient memory toward a new coefficient in the new coefficient memory;
The program includes interpolation control information indicating whether or not coefficient interpolation is instructed. When the interpolation control information included in the program read from the program memory indicates coefficient interpolation, the coefficient Selecting means for outputting the output of the generating means to the arithmetic circuit, and outputting the coefficient read from the new coefficient memory to the arithmetic circuit when the interpolation control information does not instruct coefficient interpolation;
Equipped with,
The coefficient generation means shifts the old coefficient before change read from the intermediate coefficient memory from the data obtained by shifting the new coefficient read from the new coefficient memory to the predetermined bit lower direction. Subtracting means for subtracting the obtained data;
Adding means for adding the output of the subtracting means and the output of the intermediate coefficient memory;
Writing means for writing the output of the adding means to the intermediate coefficient memory;
Determining means for determining the number of bits N (N is a positive integer) corresponding to the magnitude of the output of the subtracting means; the upper N bits of data of the new coefficient memory; An end determination means for determining the end of interpolation when the upper N bits of output data match,
Comprising
The coefficient interpolating circuit in the data processing circuit , wherein the selecting means outputs the coefficient read from the new coefficient memory to the arithmetic circuit when the end judging means judges that the interpolation is finished . When the subtraction means indicates that the result of the subtraction is zero, the subtraction unit compares the new coefficient read from the new coefficient memory with the coefficient read from the intermediate coefficient memory. 2. The coefficient interpolation circuit in the data processing circuit according to claim 1, wherein +1 is output when the coefficient is larger than a coefficient, and -1 is output when the new coefficient is smaller than the coefficient.

Images