JP2871509B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for performing operations on digital signals to realize various processes.

[0002]

2. Description of the Related Art DSPs (Divisions) are used in electronic musical instruments and
gital Signal Processor) is used to perform a calculation in accordance with the effect to be provided, thereby obtaining a musical tone with a desired effect. The operation unit of the DSP includes a multiplication unit and an addition unit, and in many cases, the multiplication operation and the addition operation can be performed simultaneously in one step of the microprogram.

A multiplier and a multiplicand are supplied to a multiplier.
In a computer, a multiplier and a multiplicand are often represented by two's complement. In the two's complement representation, the absolute value of the maximum value is different from the absolute value of the minimum value. In the case of a fixed-point multiplier, the multiplier and the multiplicand are usually handled as numbers in the range of 1 to 0 to -1. For the above reason, the positive maximum value is 1
Does not correspond to For example, considering an 8-bit coefficient, the maximum positive value is represented by 01111111 (binary notation).
If the position of the decimal point is between the 7th bit and the 8th bit from the left, it is expressed as 0.1111111 (binary notation).
If this is expressed in decimal notation, 0.9921875 (10
Notation) and does not become 1. However, since the negative minimum value is 10000000 (binary notation), it is 1.000000.
00 is exactly -1 (decimal-absolute value display).

[0004]

In an effect imparting device or the like, it is common to adjust the balance between an input signal and a signal obtained by applying an effect to an input musical tone signal. FIG. 2 is a diagram showing this state. A tone generator or a digital signal obtained by converting an analog voice or tone signal into a digital signal is input and divided into two parts. One is input to the multiplier 31 and the other is input to the effect applying unit 30. The effect adding section 30 adds various effects to the input digital signal and outputs the digital signal to the multiplier 32.

In the multipliers 31 and 32, in order to adjust the balance between the input digital signal and the signal to which the effect is given, the coefficients a and b are set as numerical values corresponding to desired balances, respectively. , Multiplier 32. As a result, in the multipliers 31 and 32, the coefficients a,
A signal of a level corresponding to the value of the coefficient b is output,
3 is added. The result of the addition is output by a sound system or input to a mixer for purposes such as recording.

Coefficients a and b supplied to multipliers 31 and 32
Is adjusted according to a value preset according to the effect type, the preference of the player, and the like. Further, an effect bypass switch is provided on the panel of the effect applying device, and when the switch is operated, the input signal is output as it is, so that the coefficient a is set to “1” and the coefficient b is set to “0”, and the output value is set to the input value. Equality is also done.

However, when the input signal is to be output as it is or the signal to which the effect is applied is to be output as it is for the above-mentioned reason, the coefficient corresponding to 1 does not exist. Has to be supplied to the multiplier. Then, there is an inconvenience that the level is slightly attenuated. In this case, the dynamic range cannot be effectively used. Further, there is a case where it is desired to use only the adder for the convenience of signal processing. In that case, it is desired to supply the data supplied with the coefficient of the multiplier set to 1 to the adder. However, for the same reason, the level of the signal supplied to the adder is still low. This does not allow accurate signal processing.

The present invention has been made to solve the above-mentioned disadvantages, and an object of the present invention is to obtain a multiplication result equivalent to multiplication of "1".

[0009]

In order to solve these problems, a signal processing apparatus according to the present invention converts a sign bit into
Process numerical information expressed as multi-bit data including
Signal processing device that supplies the multiplicand
Supply means, multiplier supply means for supplying a multiplier, and the multiplicand
A multiplier for multiplying by the multiplier, said multiplier plurality bi
If it is not the negative minimum value expressed in
And the multiplier is represented by the plurality of bits.
Selection for negative minimum value revealed that outputs the multiplicand
Output means.

[0010]

According to the present invention, the multiplier is represented by a plurality of bits.
If the negative minimum value is not
If the multiplier is a negative minimum represented by multiple bits
Is the least significant positive value of the multiplicand expressed in multiple bits
Multiplied by a number obtained by adding 1 to a bit as a multiplicand
Output, so the multiplier is expressed in multiple bits
Operations when the value "1" same as ing to what was multiplied by.

[0011]

FIG. 1 is a block diagram showing the configuration of an electronic musical instrument to which a signal processing apparatus according to the present invention is applied. In this figure,
Reference numeral 1 denotes a microprocessor (CPU) that detects an event of the performance operation element 5 and supplies sound data and the like to the musical tone generating section 6 to perform processing such as generating a musical tone. ROM (Read Only Memory) in which data and a control program of the CPU 1 are stored,
Reference numeral 3 denotes a RAM (Rand) used as an area for storing tone data and the like set by the user, a work area of the CPU 1, and the like.
om Access Memory), 4 are operators for imparting effects such as pedals and wheels, 5 is a keyboard (KB), which is a performance operator, and 6 is a sound source unit for generating a musical tone based on the control of the CPU 1. TG) 6-1 and a DSP (Digital Sign) for giving an effect or the like to the musical sound synthesized by the sound source section 6-1.
al Processor), a tone generator comprising a signal processor 6-2, a speaker 7 for generating the generated tone,
8 is an address / data bus.

In the electronic musical instrument configured as described above,
When the K.B. 5 is operated, the event is detected by the CPU 1 and transferred to the key data of the K.B. Tone generator 6 of musical tone generator 6
In step 1, a tone signal corresponding to the transferred key data and tone color information transferred from the ROM 2 or the RAM 3 is synthesized, and then the tone synthesized by the signal processing unit 6-2 is synthesized according to the operation amount of the operation element 4. With an effect or the like, a musical tone corresponding to the operation of the KB 5 is generated from the speaker 7.

By the way, D including the signal processing device of the present invention
FIG. 2 is a block diagram of the signal processing unit 6-2 including the SP. In this figure, reference numeral 10 denotes a coefficient register in which coefficients transferred via a CPU bus corresponding to the address / data bus 8 shown in FIG.
The selectors A and 12 for selecting one of the data corresponding to 0 or the negative minimum value multiply the data from the selector A11 by the data read from the temporary RAM (T-RAM) 18 and output the result to the selector B14. Multiplier,
14 is the multiplied data output from the multiplier 12 or T
-The selectors B and 16 which select one of the data read from the RAM 18 and output the selected data to the adder 16 add the data output from the selector B14 and the data output from the selector C15 to the internal bus 22. It is an adder to output.

Reference numeral 13 compares the data from the selector A11 with the data corresponding to the negative minimum value, and selects the data from the temporary RAM 18 to the selector B14 when the output of the selector A11 matches the negative minimum value. This is a comparator that supplies a select signal.

A delay means 24 delays the data from the internal bus 22 by one step, that is, 1/256 sampling period, and delay means D and 15 select either the output from the delay means D24 or "0". Selectors C and 17 which output to the adder 16 select one of the input signal and the data from the internal bus 22 and select a temporary register (T
-RAM) 18 stores the temporarily stored data in the multiplier 12 and the selector B1.
4 is a temporary RAM to be supplied to the RAM 4.

Reference numeral 19 denotes a microprogram register for storing, for example, a 256-step or 128-step microprogram for executing signal processing.
0 is an address register that stores address data read in response to the execution of the microprogram, 2
Reference numeral 1 denotes an address controller for adjusting an address read from the address register 20 to an accessible address of the delay memory. Reference numeral 23 denotes an internal bus 22 at a predetermined timing of the microprogram according to the address output from the address controller 21. This is a delay memory in which write control of the above data or read control of the stored data to the internal bus 22 is executed. The delay memory 23 is usually provided outside the DSP 6-2 because of its large capacity. However, the description will be made here assuming that the delay memory 23 is included in the DSP 6-2.

The operation will be described with reference to FIG. The microprogram register 19 outputs a microprogram of one step every 1/256 sampling period in order to execute a program of a predetermined step, for example, 256 steps, in one sampling period. The output microprogram is divided and sent to each unit for controlling each unit of the DSP 6-2.

The input signal is selected by the selector D17 in a predetermined program step in accordance with the microprogram and stored at a predetermined address of the temporary RAM.
The stored input signal is subjected to various operations using the multiplier 12, the adder 16, and the delay memory 23 according to the contents of the microprogram to give a desired effect, and is output from the internal bus 22.

Next, referring to FIG. 2, a description will be given of a case where the multiplication coefficients a and b of the multipliers 31 and 32 are set to a = 1 and b = 0 to set the effect to a "through" state, with reference to FIG. The part surrounded by the broken line in FIG.
1 is a part realized by a microprogram, the input signal is divided into two, and an operation for applying various effects is performed by the effect applying unit 30, but the detailed description is omitted, and the operation result is the temporary one shown in FIG. It shall be stored at the address specified by the microprogram in the RAM 18.

Here, the input signal and the effect imparting unit 30
Is stored at addresses 1 and 2 of the temporary RAM 18. For example, in the 255th program step, the input signal is read from address 1 of the temporary RAM 18 and the selector A11 is supplied with the negative minimum value from the coefficient register 10, so that the multiplier 12
In the example, the input signal is multiplied by a negative minimum value. However, since the comparator 13 generates a coincidence signal, the selector B1
In step 4, the input signal from the temporary RAM 18 is selected, and the multiplication result of the multiplier 12 is discarded.

In the 255th program step, "0" is selected by the selector C15 and the adder 16 is passed through. The output of the adder is delayed by one step by delay means D24 and supplied to selector C15. Therefore, in the next step, when the output of the delay means D24 is selected by the selector C15, the operation result of one step before can be supplied to the adder 16.

In the 256th program step, the output of the effect applying section 30, that is, the signal to which the effect is applied is read from the address 2 of the temporary RAM 18 and supplied to the multiplier 12. On the other hand, the coefficient register 10
Is supplied to the multiplier 12 when the selector A11 selects the output of the coefficient register 10.
Therefore, the multiplier 12 multiplies the output of the effect imparting unit 30 by “0”, and the multiplication result “
0 "is output. At this time, since the output of the delay means D24 is selected in the selector C15, the operation result of the 255th program step, that is, the input signal is the adder 1
6. The adder 16 adds the input signal to “0”. The addition result becomes the input signal itself,
It is output via the internal bus 22 as the output of the adder 33 in FIG.

An address corresponding to 255 of the microprogram of the coefficient register 10 and an address corresponding to 256 are sent from the CPU 1 via the CPU bus 8 to the "negative minimum value".
And "1" are written. The coefficient register 10 is synchronized with the operation of the microprogram register 19. For example, when the microprogram register outputs the 255th program, the coefficient register 10 also outputs the contents of the address of 255.

Although the minimum negative value is supplied from the coefficient register 10 in the 255th program step, the negative minimum value may be selected by the selector A11.

As can be understood from the above description, in the present invention, the negative minimum value is interpreted as "1", so that some care must be taken when using this arithmetic unit. That is, the negative minimum value used so far cannot be used because it cannot be used. For example, in the case of 8 bits, 1.000000 was the negative minimum value.
It is interpreted as 1. Since the negative minimum value is considerably less than the frequency of using "1", the advantage that "1" can be used can be enjoyed.

[0026]

According to the present invention, the output of the multiplier can be made completely equal to the input.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic musical instrument to which a signal processing device of the present invention is applied.

FIG. 2 is a block diagram of a signal processing unit including the signal processing device of the present invention.

FIG. 3 is a conceptual block diagram for explaining a signal processing operation.

[Explanation of symbols]

1: CPU, 2: ROM, 3: RAM generator, 4: operator, 5: keyboard, 6: tone generator, 6-1: tone generator, 6-2: signal processor, 7: speaker, 10: Coefficient register, 11: selector A, 12: multiplier, 13: comparator, 14: selector B, 15: selector C, 16: adder, 17: selector D, 18 temporary RAM, 19:
Microprogram register, 20: address register, 21: address controller, 22: internal bus, 2
3: delay memory, 24: delay means D, 30: effect imparting unit, 31, 32: multiplier, 33: adder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 7/38-7/52 G10H 1/02

Claims (1)

(57) [Claims] 1. A multi-bit data including a sign bit.
Signal processing device that processes numerical information represented by
Te, a multiplicand supplying means for supplying a multiplicand, and the multiplier supplying means for supplying a multiplier, a multiplier for multiplying the multiplicand by the multiplier, it is a negative minimum value which the multiplier is represented in multiple bits
Output the result of the multiplication by the multiplier,
There the signal processing device for negative minimum value represented by the plurality of bits, characterized in that it and a selection output means for outputting the <br/> multiplicand.