JP3050779B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing, and more particularly to signal generation and tone processing, and more particularly to efficient memory use, dynamic program selection and memory allocation. .

[0002]

2. Description of the Related Art Conventionally, a signal processing device (Digital Signal Processor, hereinafter abbreviated as DSP) has been used for the purpose of giving various effects to voices and musical sounds or for generating voices and musical sounds. Recently, it has become common to perform a plurality of processes within one sampling period.

[0003]

With the advancement of LSI technology, larger signal processing can be performed, and the amount of programs that can be processed within one sampling cycle has been increased. In addition, there is a demand for a DSP that can flexibly use a plurality of different programs according to performance information.

SUMMARY OF THE INVENTION The present invention meets the above-mentioned demands, and an object of the present invention is to provide a DSP capable of selecting a plurality of different processes based on performance information or the like.

[0005] Further, there is the following problem with a memory used for the purpose of delaying data used by a program. When multiple processes are processed in one sampling cycle,
A plurality of areas required for each processing secured in the delay memory must be prepared. Usually, the reserved area is fixed, so that a fixed area is reserved. However, since the fixed area is the largest area that can occur, there are many areas that are not normally used, and it cannot be said that the memory is effectively used. For example,
As one of the processes, there is an effector called a delay for giving a delay to an input signal. When a delay amount is given as a parameter, the input signal changes according to the delay amount. The delay amount can be varied, for example, in the range of 0.1 to 5000 msec. In this case, the memory reserved for the delay secures an area corresponding to the maximum delay amount of 5000 ms. However, in practice, it is rare to set the maximum delay amount, and it is often used with a considerably smaller delay amount. In that case, most of the reserved memory will not be used.

When a plurality of processes are performed, there may be a case where there is a memory that is not used, and on the other hand, there is a process that requires a lot of memory. Also, the delay time and the like may differ depending on the frequency to be sounded. Even in such a case, a fixed amount of memory is ensured regardless of the frequency, and there is an unused memory. The present invention also solves such a problem, and dynamically moves a memory area used by a program so that the memory can be used efficiently.

In addition, the delay memory used by the program must be cleared when it is used for a new process, but the present invention also provides a method of clearing quickly without being affected by the execution of the program. I do.

[0008]

According to a first aspect of the present invention, there is provided a signal processing apparatus for executing a program having a plurality of steps at each sampling period.
Depending on the total number of executable program steps,
Operates in a step cycle with a time length obtained by dividing the ring cycle ,
A calculating means for performing tone generation or effect processing at each sampling cycle; and operating at a predetermined cycle which is slower than the step cycle .
Storage means for storing a plurality of programs for performing tone generation or effect processing, and selecting a part of the plurality of programs from a plurality of programs stored in the first storage means. First selecting means, a storing means operating in the step cycle, a second storing means for storing the plurality of programs, a performance information receiving means for receiving performance information, And a second selection unit for selecting at least one program from the plurality of programs, wherein the calculation unit executes the at least one program selected in real time in the step cycle. By doing
It is characterized in that musical tone generation or effect processing is performed.

According to the signal processing device of the second aspect, in the signal processing device of the first aspect, the performance information
When the information receiving means receives the performance information, a plurality of the performance information
Allocating means for allocating to any of the channels,
The calculating means is for generating or effecting the musical sound for the plurality of channels.
Performing a process, wherein the calculating means is a real-time
Dividing the at least one program selected in
At the step cycle in the assigned channel
By executing, the sound generation of multiple channels or
An effect process is performed.

According to a third aspect of the present invention, a program comprising a plurality of steps is sampled by a sampling circuit.
Indicates the delay time in the signal processing device executed every period
Performance information receiver that receives performance information including delay time information
And a plurality of steps for storing a plurality of programs for effect processing.
1 storage means and a program to be executed in accordance with the performance information.
Program in real time from among the multiple programs
Selecting means for selecting, a second storage means, and the selected
The storage area of the second storage means with respect to the program
Assign in real time within the range according to delay time information
Allocating means, using the allocated storage area,
Effect including delay processing according to the selected program
Computing means for performing processing in real time .

According to a fourth aspect of the present invention, there is provided a signal processing apparatus, comprising: a program memory for storing a program for signal processing; a memory means including a plurality of memory areas used by the stored program; Arithmetic means for executing a program stored in a memory; clear instruction means for issuing an instruction for clearing at least one memory area of the plurality of memory areas; and It is characterized by comprising detecting means for detecting a timing when the memory means is not used, and clearing means for clearing the memory area designated by the clear instructing means at the timing detected by the detecting means. The signal processing device according to claim 5 is a signal processing device capable of executing tone generation or effect processing for a predetermined number of steps for each sampling period,
First storage means for storing a plurality of programs each having a different number of steps, second storage means for storing information relating to a storage position of a leading step of each of the plurality of programs, and individual programs of the plurality of programs A third storage unit for storing information on a storage position of another step, a designating unit for sequentially designating a program to be executed among the plurality of programs for each sampling period, and an executable unit within the sampling period.
The sampling period depends on the total number of steps in the program
A read address of the program specified by the specifying means is generated based on the information stored in the second storage means for each step cycle of a time length obtained by dividing the first storage means, and the first storage is performed in accordance with the read address. Reading means for reading a program from the means one step at a time, calculating means for executing a tone generation or effect process by executing the program read by the reading means at each step cycle;
An instruction means for instructing the designation means to designate a next program based on the information stored in the storage means, and a control means for rewriting the information stored in the second storage means and the third storage means. It is characterized by doing. Further, in the signal processing apparatus according to claim 6, wherein the San
The total number of programs that can be executed within the pulling cycle
Of the time length obtained by dividing the sampling period by the number of
A calculating means which operates in a step cycle and executes a predetermined number of steps of tone generation or effect processing in each sampling cycle;
A first memory for storing a plurality of programs having different numbers of steps from each other for generating a tone or effect processing;
A storage unit, a first selection unit that selects a plurality of programs from the plurality of programs, and a storage unit that operates in the step cycle, and stores the plurality of programs selected by the first selection unit And a second selecting unit that selects a plurality of programs to be executed simultaneously from among the plurality of programs stored in the second storing unit.
The arithmetic means executes a plurality of programs selected by the second selecting means at intervals corresponding to the number of steps of the program. Claim 7
In the described signal processing device, in a signal processing device that executes a program consisting of a plurality of steps for each sampling cycle, storage means for storing a plurality of programs,
Selecting means for selecting a program from among the plurality of programs , executable in the sampling cycle
The sampling period depends on the total number of steps in the program
In step cycle of division by time length, said selection means
It operates according to the selected program I, arithmetic means for performing tone generation or effect processing for each sampling period,
Control means for changing the program selected by the selection means when the total number of steps of the program selected by the selection means is larger than the number of steps executable within one sampling cycle of the calculation means. It is characterized by doing.

[0012]

FIG. 3 shows a circuit configuration of an electronic musical instrument provided with a signal processing device according to the present invention. In this electronic musical instrument, the generation of musical sounds and the application of effects are controlled by a microcomputer. Has become. The address / data bus 46 includes a CPU (central processing unit) 50,
A RAM 49, a ROM 48, a keyboard 47, an LCD 40, an operator 41, a sound source 42, a DSP 43, and the like are connected.
The keyboard 47 has a large number of keys. When each keyboard is operated, the operation is detected as key operation information. As the performance information input means, in addition to the keyboard 47, a performance information receiving device based on the MIDI standard may be connected to the address data bus 46, and the performance information may be input from another MIDI device. The CPU 50
Generates musical tones according to the program stored in M48,
Various processes for effect addition and the like are executed.
Regarding generation of a musical tone, the CPU 50 performs a process of detecting a key pressed on the keyboard 47, a process of supplying pitch information and a key-on signal relating to the pressed key to the sound source 42 to generate a digital musical tone signal, and the like.

The tone generator 42 has a plurality of tone channels for generating digital tone signals and excitation waveform signals, and tone signals from these channels are supplied to the DSP 43 in a divided manner. When a plurality of keys are pressed simultaneously on the keyboard 47, pitch information and key-on signals corresponding to these keys are supplied to a plurality of tone generation channels, and tone signals are simultaneously generated from the respective tone generation channels. The tone signal or the excitation waveform signal generated by the sound source 42 is sent to the DSP 43 to perform processing for imparting various effects,
Performs processing for musical tone generation. External RAM 33 is DSP
It is used for writing and reading data according to the instruction of the microprogram stored inside 43. DS
Detailed operations of the P43 and the external RAM 33 will be described later. The tone signal processed by the DSP 43 is output to the DAC 44. The DAC 44 performs digital / analog conversion, and the converted analog signal is sent to the sound system 45. The sound system 45 includes an amplifier and a speaker. After amplifying an analog signal to a predetermined level, the sound is emitted from the speaker as acoustic energy.

FIG. 2 is a diagram for explaining the operation of the signal processing apparatus according to the present invention. The area of the external RAM 33 used by each of the plurality of programs stored in the microphone program memory provided inside the DSP 43 is shown. It is shown. In the figure, 5 is stored in the microprogram memory.
One program is stored. These six programs are selected from a large number of programs stored in the ROM 48 and transferred to the microprogram memory according to an instruction from the CPU 50. In this embodiment, DS
Although the number of program steps that P43 can execute in one sampling cycle is 512, the microprogram memory may have a capacity of storing 512 or more steps. this is,
This is because it is necessary to load in advance a program that may be assigned in order to assign the program instantaneously.

The program to be actually executed is selected such that the total number of program steps among the programs transferred to the microprogram memory is 512 or less. Further, the same program may be designated and executed many times in one sampling cycle. Also, the execution order of the program can be freely changed. Although any combination may be used, in this embodiment, the number of programs that can be executed in one sampling cycle is up to four.

Of the microprogram memories shown in FIG. 2, programs shaded are programs to be executed, and the area of the external RAM used by these programs is indicated by arrows. External RAM
The area 33 is divided into five areas, of which area 1 is used by program 1, area 2 is used by program 4, area 4 is used by program 2, and area 5 is used by program 6. Further, it is shown that the area 3 is not used by any program and is an empty area.

These areas can be used in various situations,
The size can be changed. Also, you can freely set which program uses which area,
It is also possible to change the location of the area used by the program. For example, when the program 1 is a delay effect program, the size of the area 1 can be dynamically changed in accordance with the delay amount set by the operator 41 or predetermined. Also, when the sound source program of the algorithm including the feedback loop is stored in the program 4,
For example, the area 2 used so far can be dynamically assigned to the cleared area 3 in response to a new key depression from the keyboard 47.

FIG. 1 is a diagram for explaining the internal configuration of the signal processing device of the present invention. Reference numeral 1 denotes an address counter, which comprises a counter 2, a comparator 3, an area size register 4, a bottom address register 5, and an adder 6. There are a plurality of address counters 1, the number of which is equal to the number of programs that can be executed in one sampling cycle.
This actually operating program is called a channel. In this embodiment, there are a maximum of four channels, and channel A, channel B, channel C, and channel D are sequentially executed from the beginning of the sampling period.

The program assigned to each channel can be freely selected from programs stored in the microprogram memory. FIG. 4 shows how the programs assigned to the respective channels are sequentially executed within one sampling period. Since program A is assigned to channel A, program 4 is assigned to channel B, and program 2 is assigned to channel C,
It can be seen that the order of the assigned programs is independent of the order in which they are stored in the microprogram memory. Further, although the program 6 is assigned to the channel D, the program 4 which has been executed on the channel B may be assigned to the program 6.

As described above, the order and the number of times can be freely assigned. However, since the total number of steps of the program assigned to each channel cannot exceed the total number of steps that can be executed in one sampling period, attention must be paid to the assignment.
Even if the total number of steps is less than the total number of steps, it is necessary to prevent the program assigned to the next channel from being executed before the program is executed to the end. This is solved by management by the CPU.

Returning to FIG. 1, the description will be continued. Counter 2
Is supplied with a clock of φ0 having a period coinciding with the sampling period as shown in FIG. 4, so that the counter 2 counts by one every sampling period. Its output is supplied to the adder 6 as a two's complement representation, while also being supplied to the comparator 3. The size of one of the plurality of areas is supplied from the area size register 4 to the comparator 3. Then, when the output of the counter 2 matches the area size, a reset signal for resetting the counter 2 is output. Therefore, the counter 2 becomes 0 as soon as it outputs a value corresponding to the area size, so that the counter 2 substantially repeats the counting operation between 0 and the area size-1.

The output of the counter 2 and the bottom address of each area are supplied from the bottom address register 5 to the adder 6, and they are added. The output of the counter 2 is supplied as a two's complement expression. The output of the counter 2 is subtracted from the bottom address and output to the selector 7. An area size and a bottom address for determining an area in the external RAM 33 used by the program assigned to each channel are written from the CPU 50 to the plurality of address counters 1 via the interface 34.

The output of each address counter 1 is a selector 7
, And the select signal is controlled so as to be selected during the operation of the assigned program. The select signal is supplied from the counter 8. A clock φ0 rising at the beginning of one sampling period is supplied to the counter 8 as a reset signal, and the counter 8 outputs 0 at the beginning of one sampling period. Next, since the clock φ0 is also supplied to the program counter 10 as a reset signal, it becomes 0 at the beginning of the sampling period. The program counter 10 is supplied with a clock φ1 having a cycle corresponding to the execution time of one program step. Assuming that the total number of steps of the microprogram is 512, the clock φ1 is a clock having a period of 1/512 of the sampling period.

The output of the program counter 10 is the comparator 1
In addition to 1, 12, and 13, they are also supplied to the address register 18, the microprogram memory unit 29, and the like. Each of the comparators 11 to 13 has a top step register 1
From 4, 15, and 16 are supplied the first steps at which the programs assigned to the respective channels start executing. In this embodiment, the number of programs executed in one sampling cycle is four, but the number of top step registers is three. This is because the first step of channel A is 0 and the counter 8 is reset at clock φ0, so that the top step register of channel A is not required.

Top step registers 14, 15, 16
The first step at which the program assigned to the channels B, C, and D from the CPU 50 via the interface 34 starts to be executed is written in. by this,
It can be seen that the boundaries of each channel are also set freely.
This is necessary for efficiently using the DSP without restricting the program size to be allocated. When the output of the program counter 10 matches the start step of the program assigned to each channel, the comparators 11, 12,
13 outputs a coincidence signal, which is supplied to the counter 8 via the OR circuit 9. Therefore, the counter 8 counts at the boundary of each channel, and the selector 7 sequentially switches the outputs of the plurality of address counters 1 corresponding to each channel according to the counting result. Thereby, the external RA used by the program assigned to each channel is used.
The address of the area of M33 is switched according to the channel to be executed.

The output of the address counter 1 corresponding to each channel selected by the selector 7 is added to the output value of the address register 18 in the adder 17. The address register 18 has an address corresponding to the total number of steps 512 of the microprogram, and is read using the output value of the program counter 10 as an address. This reading timing is performed in synchronization with the reading of the microprogram memory 29. The address stored in the address register 18 is an address for accessing the external RAM 33, and is stored as a relative address with the leading address of the divided area of the external RAM 33 being 0. By adding the output of the address register 18 to the output of the address counter 1 in the adder 17,
It becomes the absolute address that is the actual address and becomes the external RAM
Address 33.

The operation unit 30 includes a multiplication unit and an addition unit, and includes a coefficient register for supplying a coefficient necessary for multiplication, according to a control signal from the microprogram memory 29.
A predetermined operation is performed, and the operation result is stored in the external RAM 33 via the selector 31 as necessary, and read out after a predetermined time elapses to perform further operation, thereby performing complicated signal processing. The final output is sent to DAC 24.

The microprogram section 29 has a microprogram memory,
The microprogram is written from the PU 50, and the microprogram is sequentially output according to the output of the program counter 10, the details of which are shown in FIG. In this figure, the parts from the program counter 10 to the top step register 16 are the same as those in FIG. The output of the OR circuit 9 and the clock φ
Since 0 is supplied and the output is supplied to the counter 107 as a reset signal, the counter 107 is reset at the head of each channel, counts by the clock φ1, and supplies the output to the adder 101.

On the other hand, four program top address registers 103 to 106 are provided corresponding to the channels.
The microprogram memory 100 to be assigned to each channel from the CPU via the interface 34
Of the program stored in the selector 102 is written and output to the selector 102. Referring to FIG. 2, the program top address register 1
03 is the start address of program 1, 104 is the start address of program 4, 105 is the start address of program 2, and 106 is the start address of program 6.

Since the counter 8 outputs 0, 1, 2, and 3 in accordance with the execution time slot of each channel, the selector 102 sets the start address of the program assigned to each of the channels A, B, C, and D. They are sequentially selected and output to the adder 101. The adder 101 adds the selected head address and the output of the counter 107 and supplies the result to the microprogram memory 100. The microprogram memory 100 reads the microprogram using the output given from the counter 107 as an address. The read microprogram is supplied as a control signal to the arithmetic unit 30 and each unit of the DSP 43 and the external RAM 33 to perform signal processing.

Returning to FIG. When a write or read signal is output from the microprogram memory unit 29 to the negative logic external RAM 33, the output of the AND circuit 28 is "0", so the output of the AND circuit 26 is also "0". “0” is supplied to the selector 32. At this time, the selector 32 outputs the output of the adder 17 to the external R
It is supplied to the AM 33 as an address. Selector 3
Since the output “0” of the AND circuit 26 is also supplied to 1, the selector 31 selects the signal line of the arithmetic unit 30. As a result, the operation unit 30 is connected to the data terminal of the external RAM.

Since the output of the AND circuit 26 is also supplied as a select signal to the selector 27, the AND circuit 2
6 is "0", the write enable signal output from the microprogram memory unit 29 is transferred to the external RAM.
33 to the write enable terminal. As a result, when the microprogram is reading or writing to the external RAM, the data terminal is connected to the operation unit and the address terminal is connected to the address output corresponding to the program assigned to each channel. RA
Reading and writing to M are performed. Note that an output enable signal from the microprogram memory is directly supplied to the output enable terminal of the external RAM 33.

On the other hand, when a write or read signal to or from the external RAM 33 of the microprogram memory unit 29 is not output, the output of the AND circuit 28 is "1" and is given to the AND circuits 20 and 26. The AND circuit 20 is also supplied with a clock φ1, and outputs a clock for counting the counter 19 for each step while there is no access to the external RAM 33. The counter 19 is provided with a reset signal from the CPU 50 via the interface 34.

The output of the counter 19 is supplied to an adder 21. The adder 21 adds the start address from the start address register 22 to the start address of the specific area to be erased in the external RAM 33. Adder 21
Uses the period when the external RAM 33 is not used,
The addresses to be erased are sequentially output from the start address of the area of the external RAM to be erased. The output is supplied to the selector 32, and is selected as an address for accessing the external RAM 33 when the output of the AND circuit 26 is "1". The output of the AND circuit 26 is supplied to selectors 27 and 32.
Is also supplied as a selection signal, and when the output value is "1", "0" is selected. Therefore, a write instruction is issued to the external RAM 33, and the data "0" is supplied to the adder 21. External RAM 33 corresponding to output
Will be written to the address.

The output of the adder 21 is also supplied to the comparator 23, is compared with the output of the adder 36, and outputs a reset signal to the flip-flop 25 when they match. The adder 36 adds "1" to the end address supplied from the end address register 24. A set signal is sent to the flip-flop 25 from the CPU 50 via the interface 34 and is set. The set flip-flop 25 outputs "1" to the AND circuit 26,
It is reset when the comparator 23 outputs a coincidence signal. Since the reset flip-flop 25 outputs “0” and sets the output of the AND circuit 26 to “0”, the selectors 27, 31, and 33 respectively operate the write enable signal from the microprogram memory 29 and the adder 17. And the output signal from the operation unit 30 are selected. The output of the adder 21 is also sent to the CPU 50 via the interface 34 to notify that the clearing has been completed.

The CPU 50 is the external RAM 33 to be cleared.
Is written into the start address register 22 using the start address of the area of the area No. as a start address. Further, the last address of the area is written to the end address register 24 as an end address. Thereafter, by sending a reset signal and a set signal to the counter 19 and the flip-flop 25, respectively, the microprogram memory is stored in the external RAM.
In the period during which the access to the address 33 is not performed, writing of “0” is continuously performed from the start address to the end address.
It is sent to 0 as a clear end flag. When the CPU 50 reads the clear end flag, it stores it as a cleared area and prepares for an allocation that requires the cleared area. Also,
If there is another area that needs to be cleared, clearing is performed in the same manner.

By adopting such a configuration, the external R
Since an arbitrary area can be erased during a period when the microprogram is not used for the AM 33, clearing can be performed while the microprogram is being executed, and the processing of the microprogram is not interrupted for clearing. Therefore, the configuration is particularly suitable for the purpose of dynamically assigning a clear area.

Next, an application example using the signal processing device will be described. FIG. 6 is a main flowchart for explaining the operation of the electronic musical instrument shown in FIG. When the power is turned on for the first time, initial settings are made in step 60, and the registers of each unit are cleared, initial values are loaded, and the like. In particular, for the DSP 43, a program defined by default and a coefficient and an address corresponding to the program are read from the ROM 48, and transferred to the microprogram memory 29, the coefficient register in the arithmetic unit 30, and the address register 18, respectively.

When the initial setting is completed, the assignment processing of step 61 is executed. This processing is a subroutine, and executes a program corresponding to the flowchart of FIG. First, at step 70, it is determined whether a note-on event has occurred. This is determined as “yes” upon detecting that any key on the keyboard 37 has been pressed, or upon receiving a note-on event from an external MIDI device (not shown), and proceeds to step 71.

In step 71, it is determined whether or not there is any unassigned channel among the four channels of the DSP 43. Here, the assignment refers to a channel that does not sound or is substantially not involved in output. The program assigned to that channel is running, but the output is throttled. If the determination is "yes", there are unused channels, so the process proceeds to step 72, where a program to be assigned based on tone parameters such as timbre and key code is determined.
Write the start address of the program to be assigned to the program top address register corresponding to the vacant channel.

If "no" is determined in step 71, the process proceeds to step 73, where the channel with the lowest volume is dumped and the sound generation is stopped. This forces a free channel. In step 74, the number of program steps in the vacant channel is compared with the number of program steps in the determined program. When the number of programs in the vacant channel is equal or larger, the assignment is possible. . The judgment is "n
In the case of "o", it is not possible to allocate to an empty channel, so the process proceeds to step 76 to determine a program again. Specifically, the size of the replaceable program is made small.

In step 75, the used size of the external memory is determined based on parameters such as tone color, key code, and delay time, and is assigned to a cleared area. This is executed by writing the area size in the area size register and the bottom address in the bottom address register in the address counter 1 corresponding to the empty channel. In step 77, the address data and coefficient data for the assigned program are stored in the address register 18,
The data is transferred to the area of the coefficient register within 0 corresponding to the assigned channel.

In step 78, a sound generation instruction is given to the corresponding channel of the sound source 42 to generate sound. Sound source 42 and D
The channels of SP43 are assumed to be the same for the sake of simplicity. Also, it sends a sound generation instruction to the corresponding channel of the DSP 43. Specifically, this starts the interpolation of the coefficients and the start of the generation of the envelope. However, since this depends on the algorithm of the program, it will not be described in detail.

In step 80, in order to clear an area of the external RAM which is not used and not cleared, the start address and the end address of the area are written in the start address register 22 and the end address register 24. When the process ends, the process returns to the main routine.

If it is determined in step 70 that there is no note-on event, the flow advances to step 78 to determine whether there is a note-off event. If there is a note-off, the process proceeds to a step 79, where a key-off process is performed for the sound source channel and the DSP channel that are sounding with the key code for which the note-off is performed.

In step 82, when the channel immediately before the vacant channel generated by the key-off is used and the size of the program allocated immediately before is smaller than the previously allocated program, Since there are unused program steps, the top step register corresponding to the unused channel is rewritten so that unused program steps do not occur. This is to make the program steps of the vacant channels as large as possible and to deal with a case where a large program is allocated. After that, the process of step 76 is performed. If it is determined in step 78 that there is no note-off event, the process returns to the main routine.

Returning to the main routine, step 62 is executed. This step is also a subroutine shown in FIG. In step 90, it is determined whether the delay time has been changed. Here, when the delay time is changed by a parameter change message from the operator 41 or an external MIDI device (not shown), a necessary external RAM area corresponding to the delay time is determined in step 91.
In step 92, it is determined whether the area can be actually allocated. This is because when the area is reduced, allocation is possible, but when the area is increased, there may be no unused external RAM area. If the assignment cannot be made, the process returns to step 90 and waits for a change in the delay time again. At this time, an error message may be displayed on the LCD 40 to urge the player to change the delay time.

At step 92, if allocation is possible, at step 93, the area size corresponding to the area determined at step 91 and the bottom address are set to the area size corresponding to the channel to which the effect is allocated. The data is transferred to the register 4 and the bottom address register 5. In step 94, the start address and end address of the area that needs to be cleared when the area is reduced are written to the start address register 22 and the end address register 24, the counter 19 is reset, the flip-flop 25 is set, and the clearing is started. Let it. Then, the process returns to the main routine. If it is determined in step 90 that the delay time has not been changed, the process returns to the main routine.

Returning to the main routine, in step 63, the interface 35 is accessed to read the clear end flag, and in step 64, it is determined whether or not the clear is completed. If the clearing is completed, step 65
To store the free area and prepare for the next allocation. If there is another area that needs to be cleared, a clear instruction is performed again. When that process ends, other processes are performed in step 66 and the process returns to step 61. Step 64
If it is determined that clearing has not been completed, the routine proceeds to step 66, where other processing is performed. Thus step 6
By repeatedly executing steps 1 to 66, the clear end flag is periodically read, so that the clear end time can always be recognized.

[0050]

As described above, in this signal processing device, the memory area used by the program can be changed, so that the memory can be used efficiently. Also, a program for generating or processing a musical tone can be selected according to the performance information, and a musical tone can be generated or processed in accordance with the selected program. be able to. Further, since the memory area that needs to be cleared is cleared at a timing when the program does not use the memory, there is an effect that the clearing can be performed regardless of the execution of the program.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing device of the present invention.

FIG. 2 is a diagram illustrating contents stored in a microprogram memory and an external RAM.

FIG. 3 is a block diagram of an electronic musical instrument including the signal processing device of the present invention.

FIG. 4 is a time chart for explaining the operation of the signal processing device of the present invention.

FIG. 5 is a block diagram of a microprogram memory unit of the signal processing device of the present invention.

FIG. 6 is a flowchart of an electronic musical instrument to which the signal processing device of the present invention is applied.

FIG. 7 is a flowchart of an assignment process.

FIG. 8 is a flowchart of an effect process.

[Explanation of symbols]

1: Address counter 3: Comparator 4: Area size register 5: Bottom address register 6: Adder
7: Selector 8: Counter 10: Program counter 11 to 13: Comparator 14 to 16: Top step register 18: Address register 22: Start address register 24: End address register 2
5: flip-flop 26: AND circuit 29: microprogram memory unit 30: arithmetic unit 33: external RA
M

Claims (7)

(57) [Claims] 1. A signal processing device for executing a program having a plurality of steps at each sampling period, wherein the program is executable within the sampling period.
The sampling period was divided by the total number of steps
A calculating means which operates at a time- period step period and performs tone generation or effect processing at each sampling period; and a storage means which operates at a predetermined period later than the step period
A first storage unit for storing a plurality of programs for performing tone generation or effect processing; and a first for selecting some of the plurality of programs from among the plurality of programs stored in the first storage unit. Selecting means, storage means operating in the step cycle, second storage means for storing the plurality of programs, performance information receiving means for receiving performance information, A second selection unit that selects at least one program from the plurality of programs, wherein the calculation unit executes the at least one program selected in real time in the step cycle, A signal processing device for performing tone generation or effect processing. 2. When the performance information receiving means receives the performance information, the performance information receiving means includes an allocating means for allocating the performance information to any one of a plurality of channels, and the arithmetic means performs tone generation or effect processing for the plurality of channels. Wherein the calculating means executes the at least one program selected in real time in the assigned channel in the step cycle to perform tone generation or effect processing for a plurality of channels. The signal processing device according to claim 1. 3. A signal processing device for executing a program consisting of a plurality of steps for each sampling period, a performance information receiving means for receiving performance information including delay time information indicating a delay time, and a plurality of programs for effect processing. A first storage unit for storing a program to be executed from the plurality of programs in real time according to the performance information; a second storage unit; Allocating means for allocating a storage area of the second storage means in real time within a range corresponding to the delay time information, and effect processing including delay processing according to the selected program using the allocated storage area And a calculation means for performing the processing in real time. 4. A program memory for storing a program for signal processing, a memory means including a plurality of memory areas used by the stored program, and an arithmetic means for executing the program stored in the program memory A clear instructing unit that issues an instruction to clear at least one memory region among the plurality of memory regions; and a detecting unit that detects a timing at which the program being executed by the arithmetic unit does not use the memory unit. And a clearing means for clearing the memory area designated by the clearing means at the timing detected by the detecting means. 5. A signal processing device capable of executing musical tone generation or effect processing for a predetermined number of steps for each sampling period, wherein the first storage means stores a plurality of programs each having a different number of steps; A second storage unit for storing information on a storage position of a head step of each of the plurality of programs; a third storage unit for storing information on a storage position of another step of each of the plurality of programs; Specifying means for sequentially specifying a program to be executed among the plurality of programs; and a program executable within the sampling period.
The sampling period was divided by the total number of steps
A read address of a program designated by the designation means is generated based on the information stored in the second storage means for each step cycle of the time length, and the program is read from the first storage means in accordance with the read address. reading means for reading out step by step, the step by step period, by executing a program read out of the reading unit, the calculating means and the information stored in said third memory means for executing the tone generation or effect processing A signal processing apparatus, comprising: an instruction unit that instructs the specification unit to specify a next program based on the information, and a control unit that rewrites information stored in the second storage unit and the third storage unit. 6. Executable within a sampling period
The sampling period is determined by the total number of steps in the program.
It operates with a step period of the divided time length, and
Computing means for executing a predetermined number of steps of tone generation or effect processing for each of the step periods, and storage means for operating at a predetermined period later than the step period
A first storage unit for storing a plurality of programs having different numbers of steps for tone generation or effect processing; a first selection unit for selecting a plurality of programs from the plurality of programs; A storage unit that operates in a step cycle, wherein the second storage unit stores a plurality of programs selected by the first selection unit, and the plurality of programs are simultaneously executed from among the plurality of programs stored in the second storage unit Second selection means for selecting a plurality of programs to be executed, and wherein the calculation means
A signal processing device for executing a plurality of programs selected by a selection unit for a period corresponding to the number of steps of the program. 7. A signal processing apparatus for executing a program comprising a plurality steps every sampling period, and storage means for storing a plurality of programs, selecting means for selecting a program from among the plurality of programs, the sampling period Executable programs within
The sampling period was divided by the total number of steps
Step period of time length, and operates in accordance with the selected program by said selecting means, and calculating means for performing tone generation or effect processing for each sampling period, the total number of steps is the arithmetic means of the program selected by said selection means A control unit that changes the program selected by the selection unit when the number of steps is larger than the number of steps executable within one sampling period.