JP3416011B2 - Electronic tone generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument, a karaoke apparatus, and desktop music (DTM: De).
CMOS (Complementary Metal Ox) such as sk Top Music
sound source LSI (Large
The present invention relates to an electronic musical sound generating device applied to a device that electronically generates a musical sound by a Scale Integrated Circuit).

[0002]

2. Description of the Related Art Conventionally, there are known electronic musical instruments capable of simultaneously producing a plurality of tones in a time division manner. Such an electronic musical instrument stores waveform data of musical tones corresponding to keyboard operations in a waveform ROM.
By time-divisionally reading from (Read Only Memory) and assigning to a sound generation channel (musical sound generation channel) to generate sound, the number of channels prepared for the generation of a musical sound can be generated simultaneously.

[0003]

By the way, in the conventional electronic musical instrument as described above, it is the speaker driving circuit that consumes the most power, and in order to obtain a general sound volume, the speaker driving circuit It requires about one digit more power than the tone generator circuit (tone generator).

[0004] Therefore, there is a digital electronic musical instrument in which power is saved by shifting from the mainstream 5V power source to a 3V power source by omitting the speaker. However, such an electronic musical instrument does not attempt to save power more than the power required for the speaker.

That is, in the conventional electronic musical instrument, although power saving has been promoted by the speaker, there is no one aiming at power saving in the tone generator circuit itself, so that total power saving can be achieved. could not.

In particular, in the sound source circuit of the conventional electronic musical instrument, regardless of the channels to be sounded and the channels not to be sounded, the calculation is performed in time division for all the prepared channels. The power required was very wasteful. For this reason, some battery-powered electronic musical instruments and the like can be used only for several days due to the battery life.

Therefore, the present invention has been made to eliminate the above-mentioned drawbacks, and promotes power saving of a tone generator LSI of an apparatus for electronically generating a musical tone and its peripheral logic (waveform ROM, etc.). Accordingly, it is an object of the present invention to provide an electronic musical sound generating device capable of achieving total power saving.

[0008]

[Means for Solving the Problems] Under such a purpose,
The first invention is to generate a plurality of musical sound data in a time division manner,
An electronic tone generator that outputs tone data for a plurality of tone generation channels, wherein a plurality of control data for generating tone data and channel information indicating a usage state of tone generation channels are externally stored for each tone generation channel. And a read control means for controlling the reading of the storage means so that a plurality of control data and channel information are read from the storage means in synchronization with the time slots of the sound generation channels. The read control means, based on the channel information read from the storage means, reads out only the control data of the sounding channel in use for the calculation time slot continuously in the left-justified order, and then calculates the remaining calculation time. In the slot, the reading of the storage means is controlled so that the same control data is read. 2nd invention is the said 1st invention, Comprising:
The same control data is characterized in that it is the control data of the last channel.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment will be described.

An electronic musical tone generating apparatus according to the present invention, for example,
It is applied to an electronic musical instrument 1 as shown in FIG.

As shown in FIG. 1, the electronic musical instrument 1 includes a keyboard 10, an operation panel 20, a sequencer (hereinafter referred to as SEQ) 40, a tone generator (hereinafter also referred to as wave generator) 50, A host CPU (Cent) connected to the operation panel 20, the SEQ 40, and the wave generator 50 and supplied with the output of the keyboard 10.
ralProcessing Unit) 30 and wave generator 5
A wavetable 60 connected to 0, a digital / analog converter (hereinafter referred to as a DAC) 70 to which the output of the wave generator 50 is supplied, and a DAC 70.
And a speaker 80 to which the output of is supplied. An external sound source device (not shown) such as another electronic musical instrument can be connected to the host CPU 30, and a MIDI (Musical Instrument Digital Int.
erface) signals such as external control information are supplied.

The wave generator 50 is a host CP.
The assignment memory 100 to which the output of U30 is supplied via the input terminal I51, the wavetable address generator 200 and the envelope generator 300 to which the output of the assignment memory 100 is supplied, and the envelope memory connected to the envelope generator 300. 400, an accumulator 500 and a system clock generator 600 to which the output of the assignment memory 100 is respectively supplied, and a multiplier 700 to which the output of the envelope generator 300 and the output of the wavetable 60 from the input terminal I54 are supplied. I have it. The assignment memory 100 also includes an addressing circuit 10
1 is also supplied, and the output of the wavetable address generator 200 is supplied to the wavetable 60 via the output terminal I53. Further, the output of the addressing circuit 401 is supplied to the envelope memory 400, and the envelope memory 400
Is output to the host CPU 30 via the output terminal I52. Furthermore, the accumulator 50
The output of the multiplier 700 is also supplied to 0, and the accumulator 500
The output of is supplied to the DAC 70 via the output terminal I55.

In the electronic musical instrument 1 as described above, for example, 16 channels are prepared as tone generation channels (musical tone generation channels), and 16 channels (16 tones) of musical tones are generated in a time division manner so that they can be simultaneously pronounced. Has been done.

Therefore, first, a series of operations of the electronic musical instrument 1 will be described.

The host CPU 30 is composed of, for example, a microcomputer, receives the key operation information of the keyboard 10, the operation information of the operation panel 20, the output information of the SEQ 40, the MIDI information of the above-mentioned external sound source device, and the like. Input commands such as pronunciation commands and mute commands based on each information
It is supplied to the wave generator 50 via 51.

In the wave generator 50, the command information from the host CPU 30 supplied via the input terminal I51 is stored in the assignment memory 100. The information (control data) stored in the assignment memory 100 is read in a time division manner, and the read control data is used to generate a read address of the wave table 60.
00 and an envelope generator 300 that generates an envelope perform arithmetic processing.

Wavetable address generator 2
The read address generated at 00 is supplied to the wavetable 60 via the output terminal I53. The wavetable 60 is composed of a ROM and outputs waveform data to the input terminal I54 according to the read address from the output terminal I53. Therefore, the waveform data which is the output of the wavetable 60 is supplied from the input terminal I54 to the multiplier 700.

The wave table 60 is composed of a RAM or a flash RAM, and the wave generator 50
It is also possible to allow the host CPU 30 to access (R / W) when is not operating.

The envelope value calculated by the envelope generator 300 is also supplied to the multiplier 700.

Therefore, the multiplier 700 multiplies the waveform data read from the wavetable 60 according to the read address of the wavetable address generator 200 by the envelope value obtained by the envelope generator 300.

The accumulator 500 accumulates the multiplication result of the multiplier 700 and outputs the accumulation result for 16 channels in one sample period.

The accumulation result of this accumulator 500 becomes the output of the wave generator 50, and D is output via the output terminal I55.
It is supplied to the AC 70, converted into an analog signal by the DAC 70, and then emitted from the speaker 80.

Next, the inside of the wave generator 50 will be specifically described.

Here, FIG. 2 shows the wave generator 5.
2 is a timing chart showing a timing clock at 0, and the USE signal and timing signals t0 to t in the figure
7, ts0 to ts15 are generated by the system clock generator 600. The Dadr signal in the figure is generated by the addressing circuit 101.

First, the USE signal indicates time division (here, time division of 16 channels of ch.0 to ch.15), and when the channel of the provided time slot is used, 1 "and" 0 "when not used. Therefore, in this figure, the used channel is ch. 0 and ch. It becomes 2 channels of 2.

The timing signal t0 is always output regardless of the value of the USE signal, and the USE signal of each time division channel is latched by the timing signal t0. The other timing signals t1 to t7 are always output regardless of the value of the USE signal, and the latch clock is applied to the latch circuit forming the pipeline described later.

The timing signals ts0 to ts15 correspond to the channel ch. 0-ch. Corresponding to 15 respectively,
It is a signal that becomes "1" in the case of the corresponding channel.

The Dadr signal is assigned to the assignment memory 10
It controls the output data of 0 and comprises number information dx1 and address information dx2 for each channel. Then, at the timing of the timing signal t0, the channel ch. The X number information dx1 and the address information dx2 are output to the assignment memory 100.

That is, at the timing of the timing signal ts0, the channel ch. 0 number information d01 (= ch.
0) and channel c in assignment memory 100
h. The address information d02 indicating the storage location of the information of 0 is output to the assignment memory 100, and the channel c
h. 1 number information d11 (= ch.1) and the channel ch. The address information d12 indicating the storage location of the information of No. 1 is the assignment memory 100.
To the channel ch.
2-ch. Fifteen number information dx1 and address information dx2 are output to the assignment memory 100.

In accordance with the Dadr signal as described above, channel ch. X information is output, but here, channel ch. When X is an unused channel, various information on that channel is not output from the assignment memory 100.

Therefore, in the Dadr signal, unused channels (channel ch. 1 and ch.
3 to ch. 15), the used channel output immediately before that (channels ch.0 and ch.
The content of the address information dx2 of 2) is output again as the address information dx2 of the unused channel.

Therefore, in FIG. 2 above, channel c
h. In the case of 1, the channel information of the channel ch. The address information of channel ch. In the case of 3, the channel information of the channel ch. The address information of No. 2 is output again.

Regarding the channel number information dx1,
It is always the corresponding channel number.

The details of the USE signal, the system clock generator 600 for generating the timing signals t0 to t7 and ts0 to ts15, and the addressing circuit 101 for generating the Dadr signal will be described later.

Therefore, first, the assignment memory 100
Will be specifically described.

The assignment memory 100, for example, as shown in FIG. 0-ch. For each 15, eight addresses corresponding to the above-described timing signals t0 to t7 are provided.

USE information indicating whether the channel is a used channel or an unused channel is stored in the address corresponding to the timing signal t0, and enable information is stored in the address corresponding to the timing signal t1. ing.

Further, the loop top information is stored in the address corresponding to the timing signal t2, the loop end information is stored in the address corresponding to the timing signal t3, and the loop top information is stored in the address corresponding to the timing signal t4.
Frequency number (hereinafter, referred to as F number) information is stored, bias address information is stored at an address corresponding to the timing signal t5, and envelope target value (hereinafter, E target) is stored at an address corresponding to the timing signal t6. Value) / envelope speed (hereinafter referred to as E speed) information is stored, and loudness information is stored at an address corresponding to the timing signal t7.

The various information (control data) for each channel as described above is stored by the host CPU 30, and the various stored information is stored in the wavetable address generator 200 according to the above-mentioned Dadr signal generated by the addressing circuit 101. Are read by.

The USE information stored in the address corresponding to the timing signal t0 is information for generating the above-mentioned USE signal, and the USE information of the channel assigned by the host CPU 30 when the key is pressed is "1". Is set to "0" and the channel for which the envelope release is completed after key release is confirmed in the envelope memory 400, it is reset to "0".

Details of various information stored in the assignment memory 100 will be described later. Further, here, various kinds of information are arranged at the addresses corresponding to the timing signals t0 to t7, but the arrangement is not limited to this.

Next, the addressing circuit 101 for generating the above-mentioned Dadr signal will be concretely described.

For example, as shown in FIG. 4, the addressing circuit 101 is supplied with the latch circuit 111 to which the USE information of each channel of the assignment memory 100 is supplied, and the output of the latch circuit 111 via the OR circuit 116. Selector 114, the latch circuit 115 to which the output of the selector 114 is supplied, the counter 112, and the counter 1
And a counter 113 to which 12 outputs are supplied.
The E information is output in a time division manner. The outputs of the counter 112 and the selector 114 are also supplied to the assignment memory 100, and the outputs of the counter 113 and the latch circuit 115 are supplied to the selector 114. In addition, the timing signal t shown in FIG.
0 is applied, and the timing signal t1 shown in FIG. 2 is applied to the latch circuit 115.

Addressing circuit 101 as described above
When the tone generation channel is not used, the selector 114 and the latch circuit 115 re-output the address information of the tone generation channel in use which was output immediately before.

That is, in the addressing circuit 101, the latch circuit 11 is a gate type latch circuit, which obtains the USE information of the assignment memory 100 at the falling timing of the timing signal t0,
It is supplied to the selector 114 via the R circuit 116.

At this time, the counter 112 outputs the count value according to the clock signal ck to the assignment memory 100.
And to the counter 113. The counter 113 supplies a count value according to the count value from the counter 112 to the A terminal of the selector 114.

The selector 114 selects the output of the counter 113 supplied to the A terminal when the output of the OR circuit 116 is "1", that is, when the USE information is "1" (used channel). Assignment memory 100
And the output of the OR circuit 116 is “0”, that is, the USE information is “0” (unused channel), the output of the latch circuit 115 supplied to the B terminal. Select to assign assignment memory 1
00 and the latch circuit 115.

The latch circuit 115 is a clock edge type latch circuit, which obtains the output of the selector 114 at the falling timing of the timing signal t1 and supplies it to the B terminal of the selector 114.

With the configuration as described above, the latch circuit 11
5, the address information of the latest used channel (here, channel ch.0 or ch.2) is always stored. Then, in the case of an unused channel, the contents of the latch circuit 115, that is, the address information of the immediately previous used channel is supplied to the assignment memory 100 again. As a result, in the case of an unused channel, the assignment memory 100 does not output information on the unused channel.

Next, the wavetable address generator 200 which operates by reading out various kinds of information stored in the above-mentioned assignment memory 100 will be specifically described.

Wavetable address generator 2
00 is, for example, as shown in FIG. 5, latch circuits 201 to 206 to which the information read from the assignment memory 100 is supplied, an adder 210 to which the outputs of the latch circuits 203 and 206 are supplied, and a latch. A comparator 211 to which each output of the circuit 202 and the adder 210 is supplied,
A selector 212 to which the outputs of the latch circuit 204, the adder 210 and the comparator 211 are supplied, and an adder 213 to which the outputs of the latch circuit 201 and the selector 212 are supplied.
A latch circuit 207 to which the output of the adder 213 is supplied,
FACC memory 214 to which output of selector 212 is supplied
And the gate 2 to which the output of the FACC memory 214 is supplied.
16 and the output of the latch circuit 207 becomes the output of the wavetable address generator 200 and is supplied to the wavetable 60. The gate 216 is controlled by the output of the latch circuit 205, and the output of the gate 216 is the output of the latch circuit 20.
6 is supplied. Furthermore, FACC
The memory 214 is adapted to be read by the output of the addressing circuit 215.

The latch circuits 201 to 207 include
Timing signals t1 to t7 as shown in FIG. 2 are applied to these latch circuits 201 to 207, respectively.
The pipeline is composed of.

Therefore, for example, ch. When the operation for 0 is performed, the latch circuit 201 obtains the bias address information read from the assignment memory 100 at the falling timing of the timing signal t5 and supplies it to the adder 213. The bias address information is a value indicating from which address of the wavetable 60 the waveform being calculated is written, that is, information indicating the start address of the tone color.

Further, the latch circuit 203 obtains the F number information read from the assignment memory 100 by the timing signal t4 and supplies it to the adder 210. This F number information is a value for generating a frequency,
It is accumulated by the adder 210.

Further, the latch circuit 202 obtains the loop end information read from the assignment memory 100 by the timing signal t3 and supplies it to the A terminal of the comparator 211, and the latch circuit 204 receives the timing signal t2. , Loop top information read from the assignment memory 100 is supplied to the B terminal of the selector 212.
The loop end information and the loop top information are information for setting the waveform reading method to the Head + Loop method, for example, information for generating an address as shown in FIG. Since the wavetable address generator 200 calculates 16 channels, it goes without saying that it is possible to simultaneously generate up to 16 types of addresses read by the Head + Loop method during one sampling period.

Further, the latch circuit 205 obtains the enable information read from the assignment memory 100 by the timing signal t1 and supplies it to the gate 216.
This enable information is temporarily “OFF” by the host CPU 30 at the time of a key-on event, and at this time, the FACC (F number accumulation result) stored in the FACC memory 214 is cleared.

Further, the latch circuit 206 obtains FACC from the gate 216 by the timing signal t4 and supplies it to the adder 210.

Then, the adder 210 includes the latch circuit 20.
F number information from 3 and FA from the latch circuit 205
CC is added, and the addition result is supplied to the B terminal of the comparator 211 and the A terminal of the selector 212 as FACC.

The comparator 211 compares the loop end information from the latch circuit 202 supplied to its A terminal with the FACC from the adder 210 supplied to its B terminal, and the loop end information indicates the addition result. If it is greater than or equal to (A ≦ B), that is, FACC, which is the cumulative value of the F number
Reaches the loop end, the result is selected by the selector 212.
Supply to.

According to the comparison result from the comparator 211, the selector 212 selects the loop top information from the latch circuit 204 when the accumulated value of the F number reaches the loop end, and conversely, the accumulated value of the F number. Is not reached to the loop end, the FACC from the adder 210 is selected.
Then, the selector 212 stores the selected loop top information or FACC in the FACC memory 214, and supplies the upper bit information (b16 to b31) of the information to the adder 213.

The adder 213 adds the bias address information from the latch circuit 201 and the high-order bit information (b16 to b31) from the selector 212 and supplies the addition result to the latch circuit 207.

The latch circuit 207 receives the timing signal t4.
Thus, the addition result from the adder 213 is obtained and output as a read address of the wave table 60 via an output buffer (not shown).

The information stored in the FACC memory 214 is read out as FACC by the gate 216 and output to the latch circuit 206. At this time,
Enable information is supplied from the latch circuit 205 to the gate 216. This enable information is
The PU 30 is temporarily turned off at the time of a key-on event, and the FACC is cleared at this time.

The used channel ch. The operation at 2 o'clock is also the same as the above-mentioned used channel ch. Since it is the same as 0:00, detailed description thereof will be omitted.

On the other hand, in the wavetable address generator 200, ch. When the calculation is performed on the channel ch. 1 from the addressing circuit 101 to the assignment memory 100 in the section of the timing signals t1 to t7, as described above. 1 immediately before the used channel, that is, the channel ch.
Since the address information of the channel ch.0 is supplied again from the assignment memory 100 except the section of the timing signal t0. The information of 1 is not output. Therefore, the wavetable address generator 200 includes the unused channel ch. 1 used channel ch. The information of 0 will be held.

The unused channel ch. 3 to ch. 15
The operation at the time of use channel ch. Since it is the same as 1 o'clock, detailed description thereof will be omitted.

Therefore, the unused channel ch. 1 and ch. 3 to ch. In the fifteen time slots, each circuit in the wavetable address generator 200 continues to hold the same value during this time, and the CMO that constitutes the circuit.
The S element does not switch. This allows
Since the read address of the wavetable 60 does not change, it is not necessary to switch the output of the wavetable 60.

Next, the envelope generator 300
Will be specifically described.

The envelope generator 300 includes, for example, as shown in FIG. 7, the latch circuits 301 to 301 to which the information read from the assignment memory 100 is supplied.
302, a multiplier 309 to which the output of the latch circuit 301 is supplied, a subtractor 306 and a multiplier 307 to which the output of the latch circuit 302 is respectively supplied, and outputs of the latch circuit 303 and the envelope memory 400. A gate 310, a latch circuit 304 to which the output of the gate 310 is supplied, an adder 308 to which the outputs of the latch circuit 304 and the multiplier 307 are supplied, and a latch circuit 305 to which the output of the multiplier 309 is supplied. The output of the latch circuit 305 is supplied to the multiplier 700 as the output of the envelope generator 300.
The output of the latch circuit 304 is also supplied to the subtractor 306, and the output of the subtractor 306 is also supplied to the multiplier 307. Further, the output of the adder 308 is supplied to the multiplier 309 and the envelope memory 400, respectively. Then, the latch circuit 3
01, 302, 303, 304 and 305 have timing signals t7, t6, t1 and t as shown in FIG.
7 and t7 are given respectively.

Envelope generator 3 as described above
00 is, for example, the cumulative value of the envelope is EACC, and EACC = (E target value−EACC) × E speed + EA
The operation formula CC makes the envelope gradually approach the E target value.

That is, in this envelope generator 300, ch. When the operation for 0 is performed, the latch circuit 301 obtains the loudness information read from the assignment memory 100 at the falling timing of the timing signal t7 and supplies it to the multiplier 309. This loudness information is a parameter for controlling the envelope value as a whole,
The multiplier 309 multiplies it with EACC and outputs it.

Further, the latch circuit 302 obtains the E target value / E speed information read from the assignment memory 100 by the timing signal t6 and supplies the E target value information to the A terminal of the subtractor 306. , E speed information is supplied to the multiplier 307.

Further, the latch circuit 303 obtains the enable information read from the assignment memory 100 by the timing signal t1 and supplies it to the gate 310.
This enable information is temporarily “OFF” by the host CPU 30 at the time of a key-on event, and at this time, EACC (accumulated value of envelope) supplied to the gate 310 is cleared.

Further, the latch circuit 304 obtains EACC from the gate 310 by the timing signal t7 and supplies it to the B terminal of the subtractor 306 and the adder 308.

Then, the subtractor 306 uses the E target value information from the latch circuit 302 supplied to its A terminal to obtain the EACC from the latch circuit 304 supplied to its B terminal.
Is subtracted (E target value-EACC). Therefore, the subtractor 306 determines how much the EACC has not reached the E target value.

The multiplier 307 multiplies the subtraction result of the subtractor 306 and the E speed information from the latch circuit 302, that is, the rate at which the EACC reaches the E target value ((E target value-EACC) ×). E speed), and the multiplication result is supplied to the adder 308.

The adder 308 adds the multiplication result of the multiplier 307 and the EACC from the latch circuit 304, that is, the previous EACC ((E target value-EACC) * E speed + EACC), and the addition result is this time. Is supplied to the multiplier 309 and the envelope memory 400.

The multiplier 309 receives the EA from the adder 308.
The CC and the loudness information from the latch circuit 301 are multiplied, and the multiplication result is supplied to the latch circuit 305.

The latch circuit 305 outputs the timing signal t7.
Thus, the multiplication result from the multiplier 309 is obtained. The multiplication result latched by the latch circuit 305 is supplied to the multiplier 200 as the envelope value output from the envelope generator 300.

The used channel ch. The operation at 2 o'clock is also the same as the above-mentioned used channel ch. Since it is the same as 0:00, detailed description thereof will be omitted.

On the other hand, in the envelope generator 300, ch. 1 is performed in the same manner as the above-mentioned wavetable address generator 200, the address ch. 1 immediately before the used channel, that is, the channel ch. Since the address information of the channel ch.0 is supplied again from the assignment memory 100 except the section of the timing signal t0. 1
Information is not output. Therefore, the envelope generator 300 includes the unused channel ch. 1 used channel ch. The information of 0 will be held.

The unused channel ch. 3 to ch. 15
The operation at the time of use channel ch. Since it is the same as 1 o'clock, detailed description thereof will be omitted.

Therefore, the unused channel ch. 1 and ch. 3 to ch. In the time slot of 15, each circuit in the envelope generator 300 keeps the same value during this period and is in a state of not switching. As a result, the read address of the wave table 60 does not change, so that the output of the wave table 60 does not need to be switched.

Next, the accumulator 500 will be specifically described.

The accumulator 500 is, for example, as shown in FIG. 8, the latch circuit 5 to which the multiplication result of the multiplier 700 is supplied.
01, a latch circuit 502 to which the information read from the assignment memory 100 is supplied, and a latch circuit 502.
Circuit 503 to which the output of
01 and the output of the latch circuit 503, the gate 510, and the adder 51 to which the output of the gate 510 is supplied.
1 and the latch circuit 50 to which the output of the adder 511 is supplied
4 and a latch circuit 513 and a gate 512 to which the output of the latch circuit 504 is respectively supplied. The output of the latch circuit 513 is supplied to the DAC 70 as the output of the accumulator 500, that is, the output of the wave generator 50. It is done like this. The output of the gate 512 is
It is adapted to be supplied to the adder 511. The latch circuits 501 to 504 are respectively supplied with the timing signal t0 shown in FIG. 2, and the latch circuit 513 receives the channel ch. 1
Timing signal ts1 is given. In addition, the gate 512 outputs the timing signal ts1 to the inverter 5
12a.

Since the timing signal t0 is always output regardless of the use or non-use of the channel as described above, the latch circuits 501 to 504 need to use the channel.
The timing signal t0 is always applied regardless of the unused state. In addition, the timing signal ts1 also uses the channel,
Since it is always output regardless of unused, the latch circuit 51
3 and the gate 512 are always supplied with the timing signal ts1 regardless of whether the channel is used or not.

The accumulator 500 as described above accumulates 16-channel musical tone data (sample point values) generated by time division.

As described above, when the USE signal is "1", that is, when the channel is the used channel, the wavetable address generator 200 reads the waveform data from the wavetable 60, and
An envelope is generated by the envelope generator 300, and the read waveform data and the generated envelope are multiplied by the multiplier 700. On the other hand, when the USE signal is “0”, that is, when the channel is an unused channel,
Since the wavetable address generator 200 and the envelope generator 300 hold the previous data, the multiplier 700 outputs the previous multiplication result. Therefore, in this case, it is necessary to clear (gate) the multiplication result.

Therefore, the accumulator 500 gates the data from the multiplier 700 input at the timing of the unused channel.

That is, first, as described above, since the envelope is supplied from the envelope generator 300 to the multiplier 700 at the timing of the timing signal t7, the multiplier 700 also supplies the latch circuit 501 at the timing of the timing signal t7. The multiplication result is supplied.

The latch circuit 501 is provided to re-latch at the timing signal t0 next to the timing signal t7 in consideration of the ease of timing.
The timing signal t0 is used to obtain the multiplication result from the multiplier 700 and supply it to the gate 510.

On the other hand, the latch circuits 502 and 503 are provided to set the delay caused by the arithmetic processing of the wavetable address generator 200 and the envelope generator 300 for one channel.
Therefore, the latch circuit 502 determines that the timing signal t0
Thus, the output of the assignment memory 100 is obtained and supplied to the latch circuit 503 in the next stage. The latch circuit 503 obtains the output of the latch circuit 502 according to the timing signal t0 and supplies it to the gate 510 as a control signal.

In response to the control signal from the latch circuit 503, the gate 510 supplies the data from the latch circuit 501 to the adder 511 as it is in the case of the used channel, and in the case of the unused channel, the latch circuit 501.
The data from is cleared and supplied to the adder 511.

The adder 511 adds the output of the gate 510 and the output of the gate 512 and supplies the result to the latch circuit 504. The latch circuit 504 obtains the addition result from the adder 511 by the timing signal t0 and outputs the result to the gate 512. It supplies to the adder 511 via. Such accumulation processing is performed by the channel ch. 0-ch. It will be held for 15 days.

At this time, the gate 512 is connected to the inverter 5
The timing signal ts1 supplied via 12a clears the data (accumulation result) from the latch circuit 504 at the time when the accumulation process for 16 channels is started.
As described above, since the data supplied to the adder 511 by the latch circuits 501 to 503 is delayed by one channel, the channel ch. When 1,
The channel ch. Data of 0 is input. Therefore, the timing of clearing the contents (accumulation result) of the latch circuit 504 is the timing of the timing signal ts1.

The 16-channel accumulation result obtained as described above is supplied to the latch circuit 513, and the latch circuit 513 obtains the 16-channel accumulation result by the timing signal ts1. Is supplied to the DAC 70 as the output of the accumulator 500.

As described above, in the first embodiment, in a time slot of an unused channel, the address information of the used channel immediately before the unused channel is sent from the addressing circuit 110 to the assignment memory 100. By outputting again, information of unused channels is not read from the assignment memory 100, and the number of times of switching of CMOS elements of each circuit provided after the moment memory 100 is reduced as much as possible during this period. As a result, total power saving can be achieved. In particular, a general-purpose LSI is mainly composed of CMOS, which consumes a large amount of power at the time of switching. Therefore, regardless of Low / High of the output level, the number of switching times of each circuit is reduced as much as possible to further save power. Can be achieved. Further, by reducing the power consumption, the amount of electromagnetic waves emitted can be relatively reduced.

In the above-described first embodiment, the wave generator 50 described above is provided outside the wave table 60 in order to generate musical tone data.
Although the waveform data is obtained from the above, the present invention is not limited to this, and the waveform data may be generated inside the wave generator 50. That is, the present invention is not limited to a wave generator that employs a method of reading waveform data from an externally provided waveform ROM, but may be a sine synthesis method or FM.
It can also be applied to a wave generator that employs a sound source method.

Further, in the above-described first embodiment, the timing signals t1 to t7 are always output, but
For example, by making the configuration of the system clock generator 600 as shown in FIG. 9, the output of the timing signals t1 to t7 is output when the USE signal is “0” as shown in FIG. Even if it is not performed, the number of times of switching can be reduced.

That is, when the USE signal is "1",
Since it is a used channel, a pipeline latch clock is generated at the timing signals t1 to t7, and when the USE signal is "0", it is an unused channel, and as shown by the dotted line in FIG. Make sure that the latch clock is not generated. Therefore, the channel ch. 1 and ch. 3 to ch. In the time slot of 15, the latch clocks of the timing signals t1 to t7 are omitted.

Therefore, in this case, the unused channel ch. 1 and ch. 3 to ch. In 15 time slots, the wavetable address generator 2
Not only the latch circuits 201 to 207 in 00, but also the circuits (adder 210, comparator 211, selector 212, adder 213) provided thereafter do not operate,
During this period, the same value is continuously held, and the CMOS elements forming the circuit are not switched. As a result, the read address of the wave table 60 does not change, so that the output of the wave table 60 does not need to be switched. In the envelope generator 300, unused channel ch. 1 and ch. 3 to ch. In the time slot of 15, not only the latches of the latch circuits 301 to 305 but also the subtractor 306, the multiplier 307, and the adder 3
08 and the multiplier 309 do not operate either, and keep the same value during this period, and the CMOS elements forming the circuit are in a state of not switching.

Further, in the above-described first embodiment, the musical sound generated by the speaker 80 is emitted, but instead of the speaker 80, a headphone or an earphone is provided and the headphone or the earphone is emitted. You may As a result, further power saving can be achieved.

Next, a second embodiment will be described.

In the above-described first embodiment, the addressing circuit 110 generates the Dadr signal as shown in FIG. 2 so that the unused channel information is not read from the assignment memory 100. However, in the second embodiment, for example, instead of the addressing circuit 110, as shown in FIG.
By providing the addressing circuit 110a as shown in FIG. 1 and generating the Dadr ′ signal as shown in FIG. 12 by the addressing circuit 110a, only the information of the used channel or the information of the last channel is continuously output from the assignment memory 100. It is configured to be read.

Since the components other than the addressing circuit 110a and the Dadr 'signal generated by the addressing circuit 110a in the second embodiment are the same as those in the first embodiment, the detailed description thereof will be omitted. The description is omitted here, and only the points different from the first embodiment will be described.

First, in the Dadr 'signal generated by the addressing circuit 110a, as shown in FIG.
The address information of the used channels (channels ch. 0 and ch. 2) is justified, and the address information of the remaining unused channels (channels ch. 1 and ch. (Channel c
h. 15) Address information.

Further, in order to generate the above-mentioned Dadr 'signal, for example, the tone generation channel ch. 0-ch. 15, a timing signal (shift clock) SCK for searching 15, a reset signal RST,
And a timing signal (channel clock) CCK for reading the data of the next channel.

The reset signal RST is a signal that generates a pulse only once in 16 channels, and the timing signal CCK is a signal that generates a pulse in each channel. However, regarding the timing signal CCK, the channel c
h. At 0, the reset signal RST also generates a pulse, so the counter 113 of the addressing circuit 110a, which will be described later, is in the reset state during this period.

Each of these signals SCK, RST and CCK
Is supplied to the addressing circuit 110a, and
Although not shown, the addressing circuit 401 for the envelope memory 400 and the addressing circuit 215 for the FACC memory 214 of the wavetable address generator 200 are also supplied.

Therefore, the addressing circuit 110a is
As shown in FIG. 11, the NOT circuit 111 to which the output of the assignment memory 100 is supplied, and the NOT circuit 11
AND circuit 114 to which the output of 1 is supplied, OR circuit 115 to which the output of AND circuit 114 is supplied, AND circuit 116 to which the output of OR circuit 115 is supplied, and
A counter 113 to which the output of the circuit 116 is supplied; a NAND circuit 117 to which the output of the counter 113 is supplied;
NOT circuit 11 to which the output of NAND circuit 117 is supplied
9 and a gate 11 to which the output of the NOT circuit 119 is supplied.
8a and the gate 11 to which the output of the gate 118a is supplied
8b, the output of the counter 113 is also supplied to the assignment memory 100, and the output of the NAND circuit 117 is also supplied to the AND circuit 116. Further, the clock signal ck is given to the counter 112, and the timing signal t0 is given to the gates 118a and 118b. Further, the AND circuit 11
The timing signal SCK described above is given to 4 and OR
The circuit 115 is supplied with the timing signal CCK, and the gates 118a and 118b are respectively supplied with the reset signal RST. And from the gate 118b,
An END signal is output, and the END signal is supplied to the accumulator 500, which will be described in detail later.

Addressing circuit 110a as described above
First, the count value of the counter 112 is always supplied to the assignment memory 100.

On the other hand, the counter 113 outputs the reset signal RS.
When reset by T, the "0" output of the counter 113 causes the assignment memory 100 to output the sound channel c according to the count value (t0) of the counter 112.
h. The USE information of 0 is read. Here, the timing signal CCK is also generated during the reset signal RST, but the reset signal RST is not counted up because it has a higher priority. Also, the sound generation channel ch. 0 is
Here, since it is the used channel, the USE information in the read information is “1”. Therefore, the USE signal whose USE information is “1”, that is, “1” is supplied to the AND circuit 114 via the NOT circuit 111.

At this time, the timing signal SCK is supplied to the AND circuit 114, and the output (= “0”) of the NOT circuit 111 invalidates the timing signal SCK to the AND circuit 114. Counter 1
In 13, the count is not performed, and the count value output from the counter 113 is “0”. Therefore, in the assignment memory 100, according to the count value (t1 to t7) of the counter 112, the sound generation channel ch. Various information of 0 is read.

Then, when the timing signal CCK is applied to the OR circuit 115 at the beginning of the next operation time slot 1, the counter 113 counts up to "1" and the assignment memory 100 outputs the counter 11 to the counter 11.
According to the count value (t0) of 2, the sound generation channel ch.
The USE information of 1 is read.

This sound generation channel ch. Since 1 is an unused channel here, USE in the read information
The information is “0”. Therefore, the USE signal whose USE information is “0”, that is, “0” is supplied to the AND circuit 114 via the NOT circuit 111.

At this time, the timing signal SCK is supplied to the AND circuit 114, and the output of the NOT circuit 111 (= "1") makes the timing signal SCK to the AND circuit 114 valid and the counter 113 It is counted up and the next sound generation channel ch. Go to 2. That is, in this case, the sound generation channel ch. 1 is not read out, and the next tone generation channel ch. Go to 2.

Sound generation channel ch. 2 is the channel used here, so the above-described sounding channel ch. In the same manner as for the assignment memory 100, the sound generation channel ch. 2 is read out, and the arithmetic time slot 1 indicates the sound generation channel ch. It is used for the calculation of 2.

In the next operation time slot 2, the timing signal CCK is applied to the OR circuit 115, so that the tone generation channel ch. 3 USE information is read out, but sound channel ch. 3 is an unused channel here, so that the above-mentioned sound generation channel ch. In the same manner as for the assignment memory 100, the sound generation channel ch. 2 is not read out, and the next tone generation channel ch. Go to 4.

As described above, the sound generation channel ch. 1
5 is completed, that is, when the output of the counter 113 reaches "15" (Q4 to Q7 are all "1"), the output causes the tone generation channel ch. 1
The information of No. 5 is read from the assignment memory 100. This pronunciation channel ch. Reading of 15 information is
The remaining time, that is, all empty calculation time slots (here, time slots for 14 channels) are repeatedly performed.

Therefore, from the assignment memory 100, the used channels (channel ch. 0 and channel c.
h. Since only the information of 2) is continuously output, as a result, in the wavetable address generator 200 and the envelope generator 300, the calculation of the used channel is performed forward. In the empty calculation time slot, the last channel (channel ch.
Since the information of 15) is repeatedly output from the assignment memory 100, as a result, the wavetable address generator 200 and the envelope generator 300 are generated.
Then, the CMOS element of the internal circuit is not switched, and the calculation result of the final channel is held during this period.

From the wavetable address generator 200 and the envelope generator 300, first, the tone generation channel ch. 0 is output, and then the sound generation channel ch. 2 is output, and thereafter, the sound generation channel ch. 15 calculation results will be supplied for 14 channels.

Therefore, the wavetable address generator 200 and the envelope generator 300
In the accumulator 500 provided in the subsequent stage, first, the sound generation channel ch. 0 is supplied, and then the tone generation channel ch. 2 is supplied, and thereafter, the sound generation channel ch. 15 calculation results will be supplied for 14 channels.

Therefore, in the accumulator 500, the tone generation channel ch. Only the calculation result of 15 is valid, and sound channel ch. It is necessary to ignore the calculation result of 15.

Therefore, here, the internal configuration of the accumulator 500 is, for example, as shown in FIG.
AND circuit 505 is provided between the latch circuit 503 and the latch circuit 503, and the END signal obtained by the addressing circuit 110a is applied to the AND circuit 505.

This END signal is a signal as shown in FIG. 12, and the first tone generation channel ch. A signal indicating an empty time slot excluding 15 time slots,
It is generated by the gate circuits 118a and 118b shown in FIG.

As a result, when the END signal is "1", the latch circuit 503 does not operate, and in the accumulator 500, the tone generation channel ch. 0 calculation result, sound channel ch. 2 calculation result and the first pronunciation channel c
h. The calculation results of 15 will be accumulated.

As described above, also in the second embodiment, it is possible to reduce the number of times of switching, so that it is possible to achieve total power saving as in the first embodiment described above.

[0129]

As described above, according to the first invention,
Based on the channel information indicating the usage status of the sounding channel (whether it is in use or not), the control data of the sounding channel in use (read-out address of the waveform data in the waveform memory is set to the calculation time slot). Only the plurality of control data (for each of the wave table address generator for generating and the envelope generator for generating the envelope value) are continuously read from the storage means in the forward packing, and then the same control is performed in the remaining calculation time slots. Since the data is read from the storage means, the output of the storage means can be in a non-switching state in the operation time slot after the control data of the sounding channel in use is read. As a result, during this time, the arithmetic elements and the like inside the apparatus are not switched. Therefore, for example, the number of times of switching inside the circuit (wave generator) for generating musical sound data including the wavetable address generator and the envelope generator can be reduced, so that total power saving of the device can be achieved. To reiterate, since a CMOS that consumes the most power for switching is the mainstream in configuring a general-purpose LSI, the present invention is applied to the output level Lo.
Further power saving can be promoted by reducing the number of times of switching of each element as much as possible without being restricted by w / High. By promoting such power saving, it is possible to relatively reduce the radiation amount of electromagnetic waves.
According to the second invention, in the first invention, the control data of the sounding channel in use is continuously read from the storage means, and then the control data of the last channel is read in the remaining operation time slots. Therefore, the output of the storage means does not switch while the control data of the final channel is continuously output. Therefore, the number of times of switching can be reduced. Although the CMOS has been shown here as an element that consumes a large amount of power during switching, the effect of the present invention is not limited to CMOS because any element having similar characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an electronic musical instrument to which an electronic musical sound generating device according to the present invention is applied in a first embodiment.

FIG. 2 is a timing chart showing a timing clock in the wave generator of the electronic musical instrument.

FIG. 3 is a diagram for explaining a memory format of an assignment memory of the electronic musical instrument.

FIG. 4 is a block diagram showing a configuration of an addressing circuit of the electronic musical instrument.

FIG. 5 is a block diagram showing a configuration of a wavetable address generator of the electronic musical instrument.

FIG. 6 is a diagram for explaining an address generated by the Head + Loop method.

FIG. 7 is a block diagram showing a configuration of an envelope generator of the electronic musical instrument.

FIG. 8 is a block diagram showing a configuration of an accumulator of the electronic musical instrument.

FIG. 9: In a time slot of an unused channel,
FIG. 6 is a block diagram showing a configuration of a system clock generator when a latch clock given to a latch circuit is omitted.

FIG. 10 is a timing chart showing a timing clock in a wave generator when a latch clock given to a latch circuit is omitted in a time slot of an unused channel.

FIG. 11 is a block diagram showing a configuration of an addressing circuit of an electronic musical instrument to which the electronic musical sound generating device according to the present invention is applied in the second embodiment.

FIG. 12 is a timing chart showing clocks for timing of the Dadr signal and the END signal.

FIG. 13 is a timing signal SCK and a reset signal RST.
3 is a timing chart showing a clock of a timing of a timing signal CCK.

FIG. 14 is a block diagram showing a configuration of an accumulator of the electronic musical instrument.

[Explanation of symbols]

1 electronic musical instrument 10 keyboard 20 Operation panel 30 host CPU 40 sequencer 50 wave generator 60 wave table 70 DAC 80 speakers 100 assignment memory 200 Wavetable Address Generator 300 envelope generator 400 envelope memory 500 accumulator 600 system clock generator I51 to I55 I / O terminals

Claims (2)

(57) [Claims] 1. A plurality of musical tone data are generated in a time division manner,
An electronic musical tone generator that outputs musical tone data for a plurality of tone generation channels, wherein a plurality of control data for generating tone data and channel information indicating the usage state of the tone generation channels are stored from the outside for each tone generation channel. And a read control means for controlling the reading of the storage means so that a plurality of control data and channel information are read from the storage means in synchronization with the time slots of the sound generation channels. The read control means, based on the channel information read from the storage means, reads out only the control data of the sounding channel in use for the calculation time slot continuously in the left-justified order, and then calculates the remaining calculation time. The electronic music is characterized in that the reading of the storage means is controlled so that the same control data is read in the slots. Generating device. 2. The electronic musical tone generating apparatus according to claim 1, wherein the same control data is control data of a final channel.