JPH08322001A - Video data fetch circuit - Google Patents

Abstract

PURPOSE: To fetch data satisfactorily even when the timing of a video is deviated from that of a horizontal synchronizing signal. CONSTITUTION: This circuit is provided with line memory 20 which fetches video line by line, a fetch control circuit 22 which controls fetch, a counter 24 and a decoder 26 which detect the fetch completion timing of one line, a decoder 28 which supplies delay to the horizontal synchronizing signal 21, a VCO 30 which supplies a clock to the counter 24 and the decoder 28, and a frequency divider 32. The output of the frequency divider 32 is provided with the same frequency and phase as that of the horizontal synchronizing signal 21. The decoder 28 outputs a fetch initialization signal 50 by adding the delay set at the outside. Since a fetch operation is initialized by such signal, the delay is offset and normal fetch is performed even when the timing of the video is remarkably deviated from that of the horizontal synchronizing signal 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video data fetch circuit for temporarily storing an area to be displayed on a child screen in a line memory in order to display the child screen on the screen of a display device.

[0002]

2. Description of the Related Art Some television receivers have a function of displaying images of two channels simultaneously by displaying a child screen on a part of a parent screen.

FIG. 1 is a circuit configuration diagram for displaying a child screen 14 on a parent screen 10. Here, it is assumed that the A channel image is displayed on the main screen 10 and the B channel image is displayed on the child screen 14.

As shown in the figure, this configuration has an A / D converter 2 for A / D converting a B channel image, a child screen display control circuit 4 for processing the converted image data for a child screen, and a processing. A video memory 6 for storing the captured image data,
D / that converts the video read from this memory to D / A
The A converter 8 includes a selector 12 for selecting a desired image from the A channel image and the D / A converted B channel image. The small screen display control circuit 4 is mainly composed of two circuits, a writing circuit and a reading circuit (not shown) for the video memory 6.

In this configuration, the child screen display control circuit 4
Is the digitized B channel image data
Write to the video memory 6 in synchronization with the horizontal sync signal of the channel. On the other hand, reading is performed in synchronization with the horizontal synchronization signal of the A channel. This is because the parent screen 10 is displaying the A channel. Sub-screen display control circuit 4
When the scanning line scans the area of the child screen 14, the selector 12 is switched to the B channel side and the child screen 14 is displayed. The reduction ratio of the child screen 14 with respect to the parent screen 10 is determined by the configuration of the read circuit of the video memory 6. For example,
When it is desired to make the height and width of the child screen 14 one-third of that of the parent screen 10, the reading of the video memory 6 is performed in the horizontal direction at a speed three times faster than the normal speed, and the weighted average is taken every three lines in the vertical direction. Good.

FIG. 2 is a block diagram of a writing circuit for the video memory 6, that is, a video data fetching circuit in the sub-screen display control circuit 4. This circuit includes a line memory 20 that captures video data line by line, a capture control circuit 22 that controls capture of the image data, and a counter 2 that inputs a pixel clock 23 that has a scan time of one pixel as a cycle.
4. Includes a decoder 26 that decodes this output and determines the end timing of capturing one line. The pixel clock 23 is generated by the VCO 30, and is divided by the frequency divider 32.
It is compared with the horizontal synchronizing signal 21 in the phase comparator 34,
The frequency as the pixel clock 23 is stably maintained. That is, for example, if the number of pixels included in one line is 40
When set to 0, the output of the VCO 30 is correctly divided by 400 by the divider 32. The frequency-divided signal (hereinafter referred to as "frequency divider output signal 36") has the same frequency and phase as the horizontal synchronizing signal 21, and this also has high frequency stability.

When the capture of one line is completed, the capture control circuit 22 suspends the capture of the video data into the line memory 20 and returns to the head of the line memory 20. Since the head of one line of the video data comes after the horizontal synchronizing signal 21, the counter 24 and the fetch control circuit 22 are first reset by the frequency divider output signal 36 synchronized with the horizontal synchronizing signal 21 of the B channel. . The video data taken in the line memory 20 is sequentially written in the video memory 6, and this data is read out at a desired timing to display a small screen.

FIG. 3 shows a B-channel image 40 sent from a broadcasting station and an image 44 of an area to be actually displayed on the sub-screen.
It is a figure which shows the relationship of. Video 40 for one screen from the broadcasting station
Is sent in synchronization with the horizontal sync signal 21, but normally,
Since an invalid image is included at the end of the image 40, this part is uniformly discarded and the image 44 for the small screen is cut out. As a result, good child screen display is possible.

[0009]

However, the child screen 1
In the display of No. 4, the video first passes through the sync separation circuit, the chroma decoder (both not shown), etc., so that there may be a timing difference with the horizontal sync signal 21. FIG. 4 is a diagram showing this deviation. The point P in the figure shows the center point of the original image 40, and here, as a result of the delay, it is shifted to the right. Therefore, if the child screen 14 is displayed as it is, the image is shifted to the right, which affects the display quality. For example, when the small screen display control circuit 4 is made into an LSI and sold, this deviation causes arbitrary variations in various television receivers of a plurality of set makers, which causes a problem. The present invention provides a video data capturing circuit in consideration of such a point.

[0010]

According to the present invention, when an area to be displayed on a child screen arrives, a capture control means for storing the image data in order from the head of the line memory, and an original image for displaying the child screen. And adjusting means for applying timing adjustment to the horizontal synchronizing signal transmitted in synchronization with. Further, in the present invention, the adjusting means is a delay circuit capable of setting a delay amount from the outside.

[0011]

When the timing of the horizontal synchronizing signal for the sub-screen is adjusted, the storage of the video data in the line memory is stopped every time the adjusted horizontal synchronizing signal is generated, and when the area to be displayed next arrives, Storage of video data is restarted from the beginning of the line memory. Further, in the present invention, the horizontal synchronization signal is provided with a delay set from the outside.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings.

FIG. 5 is a block diagram of a video data capturing circuit according to this embodiment. Here, the same configurations as those in FIG.

As shown in this figure, the feature of this embodiment is that a new decoder 28 is provided and the position of the image 44 to be cut out for the small screen is variable. The decoder 28 refers to the status of the frequency division in the frequency divider 32, and outputs a fetch initialization signal 50 when this matches the externally adjusted delay value. The fetch initialization signal 50 may be considered as a signal obtained by adding a desired delay value to the horizontal synchronizing signal 21, and this signal is the counter 24 and the fetch control circuit 2.
Reset 2.

Here, since the internal circuit of the frequency divider 32 has a normal counter configuration, it is possible to externally set the count value for realizing the desired delay value in the decoder 28 by using this counter. This setting is performed by setting a predetermined voltage (power supply voltage, ground voltage, etc.) on a setting pin that is provided in advance for adjustment.
May be applied, the number of clocks may be specified by a rotary switch or a DIP switch, and a register may be set by software. In any case, since the internal circuit of the frequency divider 32 counts the pixel clock 23 having a high frequency, the delay amount can be set finely.

FIG. 6 shows the position of the image 44 to be cut out when the image and the horizontal synchronizing signal 21 have the deviation shown in FIG.

As shown in this figure, the clipping is performed so that the point P is located at the center of the image 44 area (the intersection of the diagonal lines).
In the case of the figure, since the timing shift is large, the video 44 to be cut out deviates from the frame of the original video 40. According to the present embodiment, the delay amount of the decoder 28 can be reduced even in such an extreme case. It can be dealt with by taking it large. Specifically, the time difference between the center of the original image 40 (point Q in the figure) and the point P is measured, and this is used as the delay amount for the decoder 28.
Should be set to. The setting can be performed on a manufacturing line or the like when manufacturing a television receiver.

In the present embodiment, the decoder 28 refers to the frequency division status of the frequency divider 32, but the decoder 28 may be replaced with a shift register.
In this case, the horizontal synchronizing signal 21 (or the output signal of the frequency divider 32) is used as the input signal and the pixel clock is used as the shift clock. Here, a predetermined output signal of the shift register (a signal obtained by delaying the horizontal synchronizing signal 21 by n clocks and setting this n) according to a desired delay value may be taken as the initialization signal 50.

In this embodiment, the delay value is generated digitally by counting clocks, but an analog method may be considered. That is, a method is conceivable in which, for example, an LC delay circuit is inserted at the position of the decoder 28 and the LC circuit constant is adjusted on the manufacturing line or the like.

As described above, according to the present embodiment, not only the child screen display is kept good, but also the timing shift is absorbed by the video data capturing circuit, so that the design flexibility of the television receiver can be improved. . Therefore, the present invention
When converted to I, its versatility is high.

[0021]

As described above, since the video data fetching operation is initialized by the horizontal synchronizing signal whose timing can be adjusted, even if the timing of the video and the horizontal synchronizing signal are deviated from each other at any timing, good sub-screen display is possible. .

Further, since the delay amount at the time of adjusting the timing can be set from the outside, it is possible to cope with any deviation.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for displaying a child screen 14 on a parent screen 10.

FIG. 2 is a diagram showing a configuration of a conventional video data capturing circuit.

[Fig. 3] B channel image 40 sent from the broadcasting station
FIG. 9 is a diagram showing a relationship between an image 44 of an area to be actually displayed on the child screen.

FIG. 4 is a diagram showing a shift between an image and a horizontal synchronizing signal 21.

FIG. 5 is a diagram showing a configuration of a video data capturing circuit according to an embodiment of the present invention.

6 is a diagram showing a position of an image 44 to be cut out when the image and the horizontal synchronizing signal 21 have the deviation shown in FIG.

[Explanation of symbols]

22 capture control circuit, 24 counter, 26 decoder, 28 decoder, 30 VCO, 32 frequency divider,
34 Phase comparator.

Claims (2)

[Claims] 1. A video data capturing circuit for temporarily storing, in line units, an area to be displayed on the sub-screen of an input video in order to display the sub-screen on the screen of a display device. When a region to be displayed arrives, a fetch control unit that sequentially stores the video data from the beginning of the line memory, and an adjusting unit that adjusts the timing of a horizontal sync signal transmitted in synchronization with the input video. When the horizontal synchronization signal of which the timing is adjusted is generated, the acquisition control means stops the storage in the line memory and returns to the head of the line memory, and when the area to be displayed next arrives. A video data capturing circuit characterized by restarting the storage of video data from the head of the line memory. 2. The video data capturing circuit according to claim 1, wherein the adjusting means is a delay circuit capable of setting a delay amount from the outside.