JPH08321612A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: To suppress the deceleration of hot carries of a semiconductor element by the tencile stress in a high melting point metallic silicide after the heat treatment in a polycide gate structure semiconductor device. CONSTITUTION: A well region 1 and an element isolation region 2 are formed on a semiconductor substrate 0, next, a gate oxide film 3 to be a gate insulating film and a polycrystalline silicon 4 are grown and a CVD tungsten silicide film 5 is deposited furthermore, CVD O3-TEOS SiO2 film 6 as a compression stress film are deposited. Next, the gate oxide film, the polycrystalline silicon, the CVD tungsten silicide film, the SiO2 film 6 are simultaneously etched away to form a gate insulating film and a gate electrode and after forming an LDD structured source/drain regions, an interlayer insulating film 10 is deposited on the whole surface of the semiconductor substrate 0. Next, after flattening the interlayer insulating film 10 in a reflow step, another interlayer insulating film 12 and a wiring 13 are formed finally to form a passivation film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a polycide gate structure which enables high speed operation, in which a semiconductor element due to stress applied to an interface between the gate insulating film and the semiconductor The present invention relates to a semiconductor device capable of suppressing deterioration and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a semiconductor device having a polycide gate structure, there has been reported a decrease in hot carrier reliability due to stress applied to an interface between a gate insulating film and a semiconductor, 1994
EEE International Reliability Physics Symposium,
It was given in Lecture No. 2A.1, Apr. 1994 (IMEC, Belgium).

A summary of the contents of this report is "0.7 μ
LDD nMOSFE fabricated by mCMOS process
In a semiconductor device having a T, Ti silicide / polysilicon gate structure, the influence of the stress exerted on the interface between the gate insulating film and the semiconductor on the hot carrier deterioration when a stress is forcibly applied from the outside has been investigated. Has been found to work in the direction of suppressing the deterioration of the semiconductor element, and conversely, in the case of tensile stress, it works in the direction of accelerating the deterioration of the semiconductor element. It will be.

[0004]

In a semiconductor element having a refractory metal silicide / polysilicon gate (polycide) structure, refractory metal silicide returns to room temperature after a heat treatment such as reflow in an interlayer insulating film process. It is known that there is tensile stress in the film.

Therefore, it is an object of the present invention to suppress accelerated deterioration of hot carriers in a semiconductor element due to tensile stress in a refractory metal silicide film after heat treatment in a semiconductor device having a polycide gate structure which enables high speed operation. A semiconductor device and a method for manufacturing the same are provided.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device in which a polycide gate has a polysilicon film, a refractory metal silicide film, and a film having a compressive stress in the film after a heat treatment in a subsequent step (compressive stress). It is characterized in that it is formed of three layers (film).

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
In the above, the compressive stress film is an insulating film or an amorphous semiconductor film.

A method of manufacturing a semiconductor device according to a third aspect is the method of manufacturing a semiconductor device having a polycide gate structure, wherein a refractory metal film is formed on a polysilicon film,
When patterning into a gate electrode shape, the area of the refractory metal film is smaller than the area of the polysilicon film.

A method of manufacturing a semiconductor device according to a fourth aspect is the method of manufacturing a semiconductor device according to the first or second aspect, wherein a refractory metal film is formed on a polysilicon film, and a gate electrode shape is formed. When the patterning is performed, the area of the refractory metal film is smaller than the area of the polysilicon film.

A semiconductor device according to a fifth aspect is the semiconductor device according to the first aspect.
Alternatively, the semiconductor device according to claim 2 or the semiconductor device manufactured by the manufacturing method according to claim 3 or 4, wherein the polycide gate is arranged along a crystal plane orientation of (110). And

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a polycide gate is formed into a two-layer structure by depositing a polysilicon film and a silicide film, and after patterning into a gate shape, a compressive stress film is formed on the substrate. It is characterized in that it is formed on the entire surface.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the compressive stress film is an insulating film.

The semiconductor device according to claim 8 is the semiconductor device according to claim 6.
Alternatively, a semiconductor device manufactured by the method for manufacturing a semiconductor device described in 7 is characterized in that the polycide gate is arranged along the (110) crystal plane orientation.

The structure and operation of the present invention will be specifically described below. In the step of forming the dual polycide gate in the method for manufacturing a semiconductor device of the present invention, after the n-type polysilicon film and the p-type polysilicon film are formed on the gate insulating film, the refractory metal or refractory metal silicide is subjected to CV.
A film including a step of forming by a D method or a sputtering method and having a compressive stress in the film on the refractory metal or refractory metal silicide by a heat treatment of a subsequent step, such as TEO.
In this process, an insulating film made of S as a raw material or an amorphous semiconductor such as a-Ge is formed by a CVD method and patterned into a gate shape.

By the process described above, the tensile stress in the refractory metal silicide film is relaxed by the film having the compressive stress on the film, and the stress applied to the interface between the gate insulating film and the semiconductor is effectively zero. Alternatively, since compressive stress can be used, accelerated deterioration of hot carriers in the semiconductor element due to tensile stress in the refractory metal silicide film can be suppressed. The refractory metal used here includes tungsten, titanium, chromium, cobalt and the like.

Further, when forming the polysilicon gate having the three-layer structure as described above, a refractory metal film is formed on the polysilicon film, and the difference in etching rate between the polysilicon film and the refractory metal film is utilized. By making the area of the refractory metal film smaller than that of the polysilicon film, it is possible to reduce the influence of tensile stress in the refractory metal silicide film formed in a later step on the drain side of the gate electrode. . Therefore, accelerated deterioration of hot carriers in the semiconductor element can be suppressed.

Further, the compressive stress of the internal stress is maximized by utilizing the plane orientation dependence of the internal stress of the gate oxide film (1
10) If a polysilicon gate is formed along the surface, the tensile stress in the refractory metal silicide film is relaxed by the compressive stress applied to the interface between the gate insulating film and the semiconductor,
The stress applied to the interface between the gate insulating film and the semiconductor can be effectively reduced to zero or compressive stress.

Further, the polysilicon gate has a two-layer structure of a polysilicon film and a silicide film, and an insulating film using TEOS as a raw material or a compressive stress film such as an amorphous semiconductor film such as a-Ge is formed on the entire surface of the substrate by the CVD method. Then, the polysilicon gate is covered with the compressive stress film. That is, the compressive stress of the compressive stress film relaxes the tensile stress in the refractory metal silicide film, and has a larger effect on the interface between the gate insulating film and the semiconductor than the tensile stress in the refractory metal silicide film. Therefore, the stress applied to the interface between the gate insulating film and the semiconductor can be effectively reduced to zero or compressive stress.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1 shows a tungsten silicide film formed by depositing a tungsten silicide film with a film thickness of 500Å on the entire surface of a silicon semiconductor substrate by a CVD method and continuously applying an annealing temperature from room temperature to 900 ° C. in a nitrogen atmosphere. It shows changes in stress in the film. In the figure, the arrow indicates the direction of temperature change.

From this result, it is understood that when the temperature is returned to room temperature after the heat treatment at 850 ° C., the tensile stress of about 1000 MPa exists in the tungsten silicide film.

Instead of the tungsten silicide film,
After depositing the CVD 03-TEOS silicon oxide film and the CVD amorphous Ge on the entire surface of the silicon semiconductor substrate, annealing was performed at 850 ° C. in a nitrogen atmosphere, and stress was measured at room temperature. The results are shown in [Table 1].

[0022]

[Table 1] (Stress in film at room temperature after annealing at 850 ° C)

From the results of [Table 1], CVD at room temperature
It was found that compressive stress exists in the film of both the O3-TEOS silicon oxide film and the CVD amorphous Ge.

Therefore, the gate forming step of the MOS transistor of the LDD structure having the polycide gate as shown in FIGS. 2A to 2E and the step of forming the interlayer insulating film and the wiring in the subsequent wiring step. A semiconductor element was manufactured by.

In this embodiment, first, as shown in FIG. 2A, a well region 1 and an element isolation region 2 are formed on a semiconductor substrate 0 by a known technique to form a gate oxide film (silicon oxide film). Oxide film 3 and polycrystalline silicon 4 are grown or deposited by a known technique, and a CVD tungsten silicide film 5 is deposited to a film thickness of 500 to 800 Å, and then a silicon oxide film made of O3-TEOS as a raw material as a compressive stress film. 6 (CVD O3-TEOS SiO
₂ films) were deposited to a film thickness of 1000 to 1500 Å.

Next, as shown in FIG. 2B, the gate oxide film 3, the polycrystalline silicon 4, the CVD tungsten silicide film 5, and the silicon oxide film 6 are simultaneously etched to form a gate insulating film and a gate electrode. .

Next, as shown in FIG. 2C, after forming the source / drain regions of the LDD structure by a known technique, the interlayer insulating film 10 was deposited on the entire surface of the semiconductor substrate 0. In FIG. 2C, 7 is a side wall, 8 is a drain, and 9 is a source.

Then, in the reflow step of FIG. 2D, the interlayer insulating film 10 was flattened at a temperature of 850.degree. At this time, the CVD tungsten silicide film 5 and the silicon oxide film 6 receive heat, respectively, so that tensile stress exists in the CVD tungsten silicide film 5 and compressive stress exists in the silicon oxide film 6, respectively. As a result of the offsetting of the stress, the influence of stress is almost eliminated at the interface between the gate oxide film 3 and the semiconductor substrate 0.

Next, as shown in FIG. 2E, an interlayer insulating film 12 and a wiring 13 were formed by a known technique, and finally a passivation film 14 was formed. The sample obtained through the above steps was designated as "Sample 1". Further, instead of the silicon oxide film 6, "Sample 2" in which amorphous Ge having the same film thickness was deposited by the CVD method was prepared, and as a control, "Sample 3" having no compressive stress film was also prepared.

Next, the MOS transistors (W / L = 0.35 / 10) on Samples 1, 2 and 3 were subjected to the same conditions (Vd =
5.8V, Vg = 2.3V, 60 minutes), Gm
Was measured. The results are shown in Fig. 3. From this result, the effect of suppressing hot carrier deterioration of the compressive stress film was confirmed.

Example 2 A semiconductor element was manufactured by a gate forming step of an LDD structure MOS transistor having a polycide gate and a step of forming an interlayer insulating film and wiring in a wiring step of the subsequent steps.

In this embodiment, first, as shown in FIG. 4A, a well region 1 and an element isolation region 2 are formed on a semiconductor substrate 0 by a known technique to form a gate oxide film (silicon oxide film). An oxide film 3 and polycrystalline silicon 4 were grown or deposited by a known technique. After depositing the CVD tungsten film 15 to a film thickness of 500 to 800Å, the gate oxide film 3, the polycrystalline silicon 4, and the CVD tungsten film 15 were simultaneously etched to form a gate insulating film and a gate electrode. At that time, the difference in etching rate between the gate oxide film 3, the polycrystalline silicon 4, and the CVD tungsten film 15 was utilized to form a step as shown in FIG. 4B. By doing so, the CVD tungsten film 1 is effectively
The film area of No. 5 could be made smaller than that of polycrystalline silicon 4.

Next, as shown in FIG. 4C, after forming the source / drain regions of the LDD structure by a known technique, the interlayer insulating film 10 was deposited on the entire surface of the semiconductor substrate 0.
Then, the interlayer insulating film 10 was flattened at 850 ° C. in the reflow process of FIG. At this time, the CVD tungsten film 15 and the gate oxide film 3 each receive heat to generate C
The VD tungsten film 15 reacts with the polycrystalline silicon 4,
A CVD tungsten silicide film 5 was formed. Then, tensile stress exists in the CVD tungsten silicide film 5 and compressive stress exists in the gate oxide film 3. However, due to the cancellation of the respective stresses, the influence of the stress is almost eliminated at the interface between the gate oxide film 3 and the semiconductor substrate 0.

Next, as shown in FIG. 4E, the interlayer insulating film 12 and the wiring 13 were formed by a known technique, and finally the passivation film 14 was formed. This was designated as “Sample 4”. Also, with the same gate film structure as a control,
“Sample 5” having no step on the gate was also manufactured. And C
After depositing a silicon oxide film made of 03-TEOS as a raw material on the VD tungsten film 15 by the CVD method, a “sample 6” having a step and a “sample 7” having no step were also formed by gate patterning.

Next, the MOS transistors (W / L = 0.35 / 10) of Samples 4 to 7 were subjected to the same conditions (Vd = 5.8).
Vm, Vg = 2.3V, 60 minutes), and the change rate of Gm was compared. Results are shown in FIG. From this result, the effect of suppressing hot carrier deterioration when the gate is provided with a step was confirmed. In addition, compressive stress is applied to the CVD tungsten film 1
It was found that the effect of suppressing the hot carrier deterioration was further improved by depositing on top of No. 5.

Example 3 Stress in an oxide film was measured when a thermal oxide film having a film thickness of 100 Å was formed at 850 ° C. on the entire surface of a silicon semiconductor substrate having plane orientations of (100), (110) and (111). The results are shown in [Table 2].

[0037]

[Table 2]

From Table 2, it can be seen that the stress in the oxide film (compressive stress in this case) becomes maximum on the (110) plane. Therefore, a semiconductor element was manufactured on the silicon semiconductor substrate having the above-mentioned plane orientation by the same process as in Example 1. Then, the MOS transistors (W / L = 0.35 / 10) on each substrate are set under the same conditions (Vd = 5.8V, Vg = 2.3V, 60 minutes).
Then, the rate of change in Gm was compared. FIG. 6 shows the results. From this result, the deterioration of the (110) plane silicon semiconductor substrate was minimized, and the effect of suppressing hot carrier deterioration was confirmed.

Example 4 A semiconductor element was manufactured by the gate forming step of an LDD structure MOS transistor having a polycide gate and the step of forming an interlayer insulating film and wiring in the wiring step of the subsequent steps.

First, as shown in FIG. 7A, a well region 1 and an element isolation region 2 are formed on a semiconductor substrate 0 by a known technique, and a gate oxide film (silicon oxide film) 3 serving as a gate insulating film is formed. Polycrystalline silicon 4 was grown or deposited by known techniques. After depositing the CVD tungsten silicide film 5 with a film thickness of 500 to 800 Å, FIG.
Gate oxide film 3, polycrystalline silicon 4, CV
The D tungsten silicide film 5 was simultaneously etched to form a gate insulating film and a gate electrode.

Next, as shown in FIG. 7C, a silicon oxide film 1 made of O3-TEOS is used as a compressive stress film.
7 (O3-TEOS SiO ₂ film) from 1000 to 150
It was deposited on the entire surface of the semiconductor substrate 0 with a film thickness of 0Å.

Then, as shown in FIG. 7D, after forming the source / drain regions of the LDD structure by a known technique, the interlayer insulating film 10 was deposited on the entire surface of the semiconductor substrate 0.
Then, in the reflow process shown in FIG.
0 was flattened at 850 ° C. At this time, the CVD tungsten silicide film 5 and the silicon oxide film 17 are respectively subjected to heat, so that tensile stress is present in the CVD tungsten silicide film 5 and compressive stress is present in the silicon oxide film 17.

However, in this case, the silicon oxide film 17 is C
Since the VD tungsten silicide film 5 is covered, the compressive stress in the silicon oxide film 17 acts more effectively, and the respective stresses cancel each other, resulting in the interface between the gate oxide film 3 and the semiconductor substrate 0. Has almost no influence of stress, or the stress is applied in the direction of compressive stress. Then, as shown in FIG. 7F, the interlayer insulating film 12 and the wiring 13 were formed by a known technique, and finally the passivation film 14 was formed. This was designated as “Sample 8”. In addition, “Sample 1” was used as a control.

Next, the MOS transistors (W / L = 0.35 / 10) on Samples 1 and 8 were subjected to the same conditions (Vd =
5.8V, Vg = 2.3V, 60 minutes), Gm
The rate of change of was compared. The results are shown in Fig. 8. From this result, the effect of suppressing hot carrier deterioration when the gate was covered with the compressive stress film was confirmed.

[0045]

As is apparent from the above description, claim 1
In the semiconductor device described in the item 2 or 2, since the polycide gate is formed of three layers of a polysilicon film, a refractory metal silicide film, and a compressive stress film, the tensile stress in the refractory metal silicide film is compressive stress. Since the stress of the polycide gate is relaxed by the film and the stress of the polycide gate can be effectively reduced to zero or compressive stress, accelerated deterioration of hot carriers of the semiconductor element can be suppressed. The semiconductor device according to claim 3, wherein in the method of manufacturing a semiconductor device having a polycide gate structure, when a refractory metal film is formed on a polysilicon film and patterned into a gate electrode shape, the area of the refractory metal film is increased. Is smaller than the area of the polysilicon film, it is possible to reduce the influence of the tensile stress in the refractory metal silicide film formed in a later step on the drain side of the gate electrode. Therefore, accelerated deterioration of hot carriers in the semiconductor element can be suppressed. In the method of manufacturing a semiconductor device according to claim 4, when manufacturing the semiconductor device according to claim 1 or 2, when a refractory metal film is formed on a polysilicon film and patterned into a gate electrode shape, By making the area of the melting point metal film smaller than the area of the polysilicon film, the effect of the compressive stress film on the refractory metal silicide film is added, and the refractory metal silicide formed on the drain side of the gate electrode in a later step. The influence of tensile stress in the film can be made smaller. Therefore, accelerated deterioration of hot carriers in the semiconductor element can be suppressed. In the semiconductor device according to claim 5 or 8, the polycide gate has (11
Since the internal stress (compressive stress) in the gate oxide film is larger than that of any other surface orientation by being arranged along the crystal plane orientation of 0), the tensile stress in the refractory metal silicide film is Internal stress (compressive stress) in the gate oxide film
The stress of the polycide gate is effectively reduced to zero or compressive stress. Therefore, accelerated deterioration of hot carriers in the semiconductor element can be suppressed. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein a polycide gate is formed into a two-layer structure by depositing a polysilicon film and a silicide film, and after patterning into a gate shape, a compressive stress film is formed on the entire surface of the substrate. The polysilicon gate is covered with a compressive stress film by forming it, and the compressive stress of the compressive stress film is less than the tensile stress in the refractory metal silicide film while relaxing the tensile stress in the refractory metal silicide film. Since the influence on the interface between the gate insulating film and the semiconductor becomes larger than that, the stress at the interface between the gate oxide film and the silicon semiconductor substrate can be effectively reduced to zero or compressive stress. Therefore, accelerated deterioration of hot carriers in the semiconductor element can be suppressed.

[Brief description of drawings]

FIG. 1 is a graph showing changes in stress during annealing of CVD tungsten silicide.

FIG. 2 is an explanatory view of the manufacturing process of the semiconductor device according to the embodiment of the invention, which is a sectional view of the semiconductor device.

FIG. 3 is a graph showing the relationship between the film structure of a MOS transistor and hot carrier deterioration.

FIG. 4 is an explanatory view of a manufacturing process of a semiconductor device according to another embodiment, which is a sectional view of the semiconductor device.

FIG. 5 is a graph showing a relationship between presence / absence of a step and hot carrier deterioration in a film structure of a MOS transistor.

FIG. 6 is a graph showing the relationship between the plane orientation of a silicon semiconductor substrate forming a MOS transistor and hot carrier deterioration.

FIG. 7 is an explanatory view of the manufacturing process of the semiconductor device according to still another embodiment, which is a sectional view of the semiconductor device.

FIG. 8 is a graph showing a relationship between process differences and hot carrier deterioration of MOS transistors.

[Explanation of symbols]

0 semiconductor substrate 1 well region 2 element isolation region 3 gate oxide film 4 polycrystalline silicon 5 CVD tungsten silicide film 6 silicon oxide film (CVD O3-TEOS SiO
₂ film) 7 sidewall 8 drain 9 source 10, 12 interlayer insulating film 13 wiring 14 passivation film 15 CVD tungsten film 17 silicon oxide film (O3-TEOS SiO ₂ film)

Claims (8)

[Claims] 1. A polycide gate is formed of three layers of a polysilicon film, a refractory metal silicide film, and a film having compressive stress in the film after heat treatment in a subsequent step (hereinafter, compressive stress film). Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the compressive stress film is an insulating film or an amorphous semiconductor film. 3. A method of manufacturing a semiconductor device having a polycide gate structure, wherein when a refractory metal film is formed on a polysilicon film and patterned into a gate electrode shape, the area of the refractory metal film is changed to that of the polysilicon film. A method for manufacturing a semiconductor device, characterized in that the area is smaller than the area. 4. The method of manufacturing a semiconductor device according to claim 1, wherein when forming a refractory metal film on a polysilicon film and patterning into a gate electrode shape, an area of the refractory metal film is formed. Is smaller than the area of the polysilicon film. 5. The semiconductor device according to claim 1 or 2, or the semiconductor device manufactured by the manufacturing method according to claim 3 or 4, wherein the polycide gate is (11).
0) The semiconductor device is arranged along the crystal plane orientation of 0). 6. A semiconductor device characterized in that a polycide gate is formed in a two-layer structure by depositing a polysilicon film and a silicide film, and after patterning into a gate shape, a compressive stress film is formed over the entire surface of the substrate. Manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the compressive stress film is an insulating film. 8. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 6, wherein the polycide gate is arranged along the (110) crystal plane orientation. Semiconductor device.