JPH08321594A - Production of soi substrate - Google Patents

Production of soi substrate

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Publication number
JPH08321594A
JPH08321594A JP8062534A JP6253496A JPH08321594A JP H08321594 A JPH08321594 A JP H08321594A JP 8062534 A JP8062534 A JP 8062534A JP 6253496 A JP6253496 A JP 6253496A JP H08321594 A JPH08321594 A JP H08321594A
Authority
JP
Japan
Prior art keywords
substrate
ions
region
silicon substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8062534A
Other languages
Japanese (ja)
Other versions
JP3097827B2 (en
Inventor
Tetsuya Nakai
哲弥 中井
Takayuki Shingyouchi
隆之 新行内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP08062534A priority Critical patent/JP3097827B2/en
Publication of JPH08321594A publication Critical patent/JPH08321594A/en
Application granted granted Critical
Publication of JP3097827B2 publication Critical patent/JP3097827B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/30Hydrogen technology
    • Y02E60/32Hydrogen storage

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  • Element Separation (AREA)

Abstract

PURPOSE: To suppress dislocation defect of an Si layer in the vicinity of surface of a substrate by implanting He ions, which do not react on silicon in the vacuum, into a silicon substrate to form a region damaged by ion implantation in the substrate and then subjecting the substrate to high temperature annealing in oxidizing atmosphere. CONSTITUTION: He ions, H ions, Ar ions or Si ions are implanted into a silicon substrate in the vacuum to form a region 12 damaged by ion implantation. In the region 12, a silicon atom is discharged from the lattice position to produce an interstitial silicon atom 14 and a hole 15 is formed at the lattice position. When the silicon substrate 11 is annealed at 1000-1400 deg.C in oxidizing atmosphere, oxygen atoms 16 are diffused through diffusion control into the substrate while oxidizing an Si layer on the surface of substrate to form an oxide layer 11c. He and the like does not react on silicon and discharged to the outside of substrate in the atmosphere and the diffused oxygen forms SiOx preferentially because of the holes 15 existing in the region 12 damaged by ion implantation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は絶縁層上にシリコン層を
形成するSOI(Silicon-On-Insulator)基板の製造方
法に関する。更に詳しくはSIMOX(Separation by
Implanted Oxygen)技術によるSOI基板の製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an SOI (Silicon-On-Insulator) substrate in which a silicon layer is formed on an insulating layer. For more details, SIMOX (Separation by
The present invention relates to a method for manufacturing an SOI substrate by Implanted Oxygen) technology.

【0002】[0002]

【従来の技術】SOI基板は将来の超高集積回路(UL
SI)基板として注目されてきている。このSOI基板
の製造方法には、シリコン基板同士を絶縁膜を介して貼
り合わせる方法、絶縁性基板又は絶縁性薄膜を表面に有
する基板の上にシリコン薄膜を堆積させる方法、SIM
OX法などがある。このSIMOX法は、シリコン基板
の内部に絶縁層を埋込む法の1つであって、具体的には
シリコン基板内部に高濃度の酸素イオンを注入した後、
高温でアニール処理してこのシリコン基板表面から所定
の深さの領域に埋込みシリコン酸化層を形成し、その表
面側のSi層を活性領域とする方法である。このSIM
OX法ではシリコン基板内部に酸素を一度に過剰にイオ
ン注入することにより、格子位置のシリコン原子を放出
して格子間シリコン原子にするとともに格子位置に空孔
を形成する。引き続いて、高温アニール処理してシリコ
ン基板を体積膨張させることにより、注入した酸素イオ
ンと格子間シリコン原子を再配列させてイオン注入損傷
領域に極めて短時間のうちにシリコン酸化層を析出させ
ている。
2. Description of the Related Art SOI substrates are used in future ultra-high integrated circuits (UL).
SI) has attracted attention as a substrate. This SOI substrate manufacturing method includes a method of bonding silicon substrates to each other via an insulating film, a method of depositing a silicon thin film on an insulating substrate or a substrate having an insulating thin film on its surface, and SIM.
OX method and the like. This SIMOX method is one of the methods of burying an insulating layer inside a silicon substrate. Specifically, after implanting high-concentration oxygen ions inside the silicon substrate,
In this method, an embedded silicon oxide layer is formed in a region of a predetermined depth from the surface of the silicon substrate by annealing at a high temperature, and the Si layer on the surface side is used as an active region. This SIM
In the OX method, oxygen is excessively ion-implanted into the silicon substrate at a time, so that silicon atoms at lattice positions are released to interstitial silicon atoms and vacancies are formed at lattice positions. Subsequently, high-temperature annealing treatment is performed to expand the volume of the silicon substrate to rearrange the implanted oxygen ions and interstitial silicon atoms to deposit a silicon oxide layer in the ion-implanted damaged region in an extremely short time. .

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来のS
IMOX法では過剰な格子間シリコン原子により微小欠
陥を生じ、この微小欠陥は高温アニール処理による再配
列時に基板表面近傍で成長して転位欠陥を形成し易い不
具合があった。また上記方法ではイオン注入する酸素の
原子量が比較的大きく、このために高い加速電圧を要す
ることから、注入した基板表面からの深さ方向に酸素濃
度が広く分布し易く、しかも基板表面が粗くなり、埋込
みシリコン酸化層の境界が急峻でない傾向があった。特
に埋込みシリコン酸化層を基板表面から深く形成しよう
とするとその傾向が顕著であった。換言すれば、酸素イ
オン注入の場合には、SOI基板の表面粗さが大きく、
しかもイオン注入損傷領域が広くなり易く、その分だけ
アニール処理で所定の深さ領域に境界が急峻な埋込みシ
リコン酸化層を形成することが困難であった。更に上記
方法では酸素イオン注入の際に、イオン注入装置からF
e,Ni,Cu,Zn,Crなどの重金属が不純物とし
てシリコン基板の表面近傍に高い濃度で侵入し易い。こ
れらの重金属が基板表面の活性領域のSi層に存在する
とデバイスとなったときの電気特性に大きな影響を及ぼ
す問題点があった。
However, the conventional S
In the IMOX method, excessive interstitial silicon atoms generate microdefects, and these microdefects tend to grow near the substrate surface during rearrangement by high-temperature annealing to easily form dislocation defects. Further, in the above method, since the atomic amount of oxygen to be ion-implanted is relatively large and therefore a high acceleration voltage is required, the oxygen concentration is likely to be widely distributed in the depth direction from the implanted substrate surface, and the substrate surface becomes rough. The boundary of the buried silicon oxide layer tended not to be steep. This tendency was remarkable especially when the buried silicon oxide layer was formed deeply from the substrate surface. In other words, in the case of oxygen ion implantation, the surface roughness of the SOI substrate is large,
In addition, the ion-implanted damaged region is apt to be widened, and it has been difficult to form a buried silicon oxide layer having a steep boundary in a predetermined depth region by annealing. Further, in the above method, when oxygen ion implantation is performed, F
Heavy metals such as e, Ni, Cu, Zn, and Cr easily infiltrate into the vicinity of the surface of the silicon substrate at high concentration as impurities. If these heavy metals are present in the Si layer in the active region of the substrate surface, there is a problem that the electrical characteristics of the device are greatly affected.

【0004】本発明の目的は、基板表面の活性領域のS
i層に転位欠陥を形成しにくいSOI基板の製造方法を
提供することにある。本発明の別の目的は、比較的低い
加速電圧により、基板表面粗さを小さくして、かつ所定
の深さ領域に境界が急峻で層厚の小さな埋込みシリコン
酸化層を形成し得るSOI基板の製造方法を提供するこ
とにある。本発明の更に別の目的は、基板中の重金属を
低減し得るSOI基板の製造方法を提供することにあ
る。
An object of the present invention is to add S in the active region of the substrate surface.
An object of the present invention is to provide a method for manufacturing an SOI substrate in which dislocation defects are hard to form in the i layer. Another object of the present invention is to provide an SOI substrate which has a relatively low accelerating voltage to reduce the substrate surface roughness and to form a buried silicon oxide layer having a sharp boundary and a small layer thickness in a predetermined depth region. It is to provide a manufacturing method. Still another object of the present invention is to provide a method for manufacturing an SOI substrate which can reduce heavy metals in the substrate.

【0005】[0005]

【課題を解決するための手段】請求項1に係る発明は、
図1(a)〜図1(d)に示すように、シリコン基板1
1に真空中で少なくともHeイオン、Hイオン、Arイ
オン又はSiイオンを注入することによりシリコン基板
11内部にイオン注入損傷領域12を形成する工程と、
イオン注入損傷領域12が形成されたシリコン基板11
を酸化性雰囲気中で1000℃〜1400℃の温度でア
ニール処理してシリコン基板11表面から所定の深さの
領域に埋込みシリコン酸化層13を形成して基板表面に
単結晶Si層11aを形成する工程とを含むSOI基板
10の製造方法である。
The invention according to claim 1 is
As shown in FIGS. 1A to 1D, a silicon substrate 1
Forming an ion-implanted damage region 12 inside the silicon substrate 11 by implanting at least He ions, H ions, Ar ions or Si ions in a vacuum in 1;
Silicon substrate 11 on which ion implantation damage region 12 is formed
Is annealed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere to form a buried silicon oxide layer 13 in a region of a predetermined depth from the surface of the silicon substrate 11 to form a single crystal Si layer 11a on the surface of the substrate. The manufacturing method of the SOI substrate 10 including the steps.

【0006】図1(a)に示すシリコン基板11に真空
中でHeイオン、Hイオン、Arイオン又はSiイオン
を注入すると、図1(b)に示すようにイオン注入損傷
領域12が形成され、このイオン注入損傷領域12では
格子位置のシリコン原子が放出されて格子間シリコン原
子14(図中、※印で示す)になるとともに格子位置に
空孔15(図中、○印で示す)が形成される。続いて酸
化性雰囲気中で1000℃〜1400℃の温度でこのシ
リコン基板11をアニール処理すると、図1(c)及び
(d)に示すように酸素原子16(図中、●印で示す)
は基板表面でSi層を酸化することにより酸化層11c
を形成しつつ基板内部に拡散律速により拡散していく。
He等はシリコンと反応しないため、雰囲気中の基板外
に放出される。拡散してきた酸素原子はイオン注入損傷
領域12の空孔15の存在により優先的にSiOxを形
成する。この拡散律速により酸化が進行するために格子
間シリコン原子の急激な発生はなく、微小欠陥は殆ど発
生せず、転位欠陥を抑制することができる。
When He ions, H ions, Ar ions or Si ions are implanted into the silicon substrate 11 shown in FIG. 1A in a vacuum, an ion implantation damage region 12 is formed as shown in FIG. 1B. In this ion-implanted damage region 12, silicon atoms at the lattice position are released to become interstitial silicon atoms 14 (indicated by * in the figure) and vacancies 15 (indicated by ○ in the figure) are formed at the lattice position. To be done. Subsequently, when the silicon substrate 11 is annealed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere, oxygen atoms 16 (indicated by ● in the figure) are obtained as shown in FIGS. 1 (c) and 1 (d).
Oxide layer 11c by oxidizing the Si layer on the substrate surface
Is diffused inside the substrate while forming the film.
Since He and the like do not react with silicon, they are released to the outside of the substrate in the atmosphere. The diffused oxygen atoms preferentially form SiOx due to the existence of the holes 15 in the ion implantation damage region 12. Oxidation proceeds due to this diffusion control, so that interstitial silicon atoms are not abruptly generated, micro defects are hardly generated, and dislocation defects can be suppressed.

【0007】請求項2に係る発明は、図2(a)〜図2
(e)に示すように、シリコン基板11に真空中で少な
くともHeイオン又はHイオンを注入することによりシ
リコン基板11内部にイオン注入損傷領域12を形成す
る工程と、イオン注入損傷領域12が形成されたシリコ
ン基板11を800℃〜1000℃の温度でアニール処
理してイオン注入損傷領域12に注入されたHe原子又
はH原子をこの損傷領域12より放出して空孔領域15
を形成する工程と、この空孔領域15が形成されたシリ
コン基板11を酸化性雰囲気中で1000℃〜1400
℃の温度でアニール処理してシリコン基板11表面から
所定の深さの領域に埋込みシリコン酸化層13を形成し
てシリコン基板表面に単結晶Si層11aを形成する工
程とを含むSOI基板10の製造方法である。この方法
によれば、Si原子(図中、sを円で囲んで表す)が配
列したシリコン基板を800℃〜1000℃の温度でア
ニール処理することにより、He原子又はH原子(図
中、hを円で囲んで表す)を確実に基板外に放出し、そ
れに伴って生じた空孔領域15に酸素原子(図中、●印
で示す)が酸化性雰囲気のアニール処理により侵入して
SiOxを形成するため、埋込みシリコン酸化層をより
一層安定して形成することができる。
The invention according to claim 2 is shown in FIGS.
As shown in (e), the step of forming the ion-implanted damaged region 12 inside the silicon substrate 11 by implanting at least He ions or H ions into the silicon substrate 11 in a vacuum, and the ion-implanted damaged region 12 are formed. The silicon substrate 11 is annealed at a temperature of 800 ° C. to 1000 ° C., and He atoms or H atoms implanted in the ion-implanted damaged region 12 are released from the damaged region 12 to form the vacancy region 15.
And the silicon substrate 11 in which the hole regions 15 are formed in an oxidizing atmosphere at 1000 ° C. to 1400 ° C.
A step of annealing at a temperature of ° C to form a buried silicon oxide layer 13 in a region of a predetermined depth from the surface of the silicon substrate 11 and form a single crystal Si layer 11a on the surface of the silicon substrate. Is the way. According to this method, a silicon substrate on which Si atoms (s is surrounded by a circle in the drawing) are arranged is annealed at a temperature of 800 ° C. to 1000 ° C., so that He atoms or H atoms (h in the drawing, h Is surrounded by a circle), and oxygen atoms (indicated by a black circle in the figure) enter the vacancy region 15 generated by the intrusion by an annealing treatment in an oxidizing atmosphere to remove SiOx. Since it is formed, the buried silicon oxide layer can be formed more stably.

【0008】請求項3に係る発明は、図3(a)〜図3
(e)に示すように、シリコン基板21に真空中で少な
くともHeイオン又はHイオンを注入することによりシ
リコン基板21内部にイオン注入損傷領域22を形成す
る工程と、イオン注入損傷領域22が形成されたシリコ
ン基板21を800〜1400℃の温度でアニール処理
してイオン注入損傷領域22に注入されたHe原子又は
H原子をこの領域22より放出して空孔領域23を形成
する工程と、シリコン基板21内部に酸素イオンを注入
して空孔領域23を中心にSiOx領域24を形成する
工程と、SiOx領域24が形成されたシリコン基板2
1を酸化性雰囲気中で1000℃〜1400℃の温度で
アニール処理してシリコン基板21表面から所定の深さ
の領域に埋込みシリコン酸化層26を形成してシリコン
基板表面に単結晶Si層21aを形成する工程とを含む
SOI基板20の製造方法である。この方法によれば、
基板外へのHe原子又はH原子(図中、hを円で囲んで
表す)の放出により生じた空孔領域23に酸素原子(図
中、●印で示す)がイオン注入により侵入してSiOx
を形成するため、請求項1又は2に係る発明に比べて埋
込みシリコン酸化層を更により一層安定して形成するこ
とができる。
The invention according to claim 3 is shown in FIGS.
As shown in (e), a step of implanting at least He ions or H ions in the silicon substrate 21 in a vacuum to form the ion-implanted damaged region 22 inside the silicon substrate 21, and the ion-implanted damaged region 22 is formed. Annealing the silicon substrate 21 at a temperature of 800 to 1400 ° C. to release He atoms or H atoms implanted in the ion-implanted damage region 22 from this region 22 to form a vacancy region 23; 21 and a step of implanting oxygen ions into the inside to form the SiOx region 24 around the vacancy region 23, and the silicon substrate 2 on which the SiOx region 24 is formed.
1 is annealed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere to form a buried silicon oxide layer 26 in a region of a predetermined depth from the surface of the silicon substrate 21 to form a single crystal Si layer 21a on the surface of the silicon substrate. A method of manufacturing the SOI substrate 20 including a step of forming. According to this method
Oxygen atoms (indicated by ● in the figure) enter the vacancy region 23 generated by the release of He atoms or H atoms (h is circled in the figure) out of the substrate by ion implantation and SiOx.
Therefore, the buried silicon oxide layer can be formed much more stably as compared with the invention according to claim 1 or 2.

【0009】請求項4に係る発明は、請求項1〜3いず
れかに係る発明であって、アニール処理して埋込シリコ
ン酸化層13,26を形成した後にシリコン基板11,
21表面を研磨する工程を更に含むSOI基板の製造方
法である。この方法によれば、基板の表面粗さをより小
さくすることができ、マイクロラフネスがより小さい単
結晶Si層11a、21aが得られる。請求項5に係る
発明は、請求項1〜4いずれかに係る発明であって、注
入するイオンがHeイオン又はHイオンであるとき、そ
のイオン注入時のドーズ量が1×1016/cm2〜5×
1017/cm2で、加速電圧が40keV〜200ke
VであるSOI基板の製造方法である。請求項6に係る
発明は、請求項1〜5いずれかに係る発明であって、埋
込シリコン酸化層13,26を形成するためのアニール
処理が酸化性雰囲気中、10〜100気圧下で行われる
SOI基板の製造方法である。この方法によれば、埋込
みシリコン酸化層をより一層安定して形成することがで
きる。
The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the silicon substrate 11, after the buried silicon oxide layers 13, 26 are formed by annealing.
21 is a method for manufacturing an SOI substrate further including a step of polishing the surface. According to this method, the surface roughness of the substrate can be further reduced, and the single crystal Si layers 11a and 21a having smaller microroughness can be obtained. The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein when the ions to be implanted are He ions or H ions, the dose amount at the time of ion implantation is 1 × 10 16 / cm 2. ~ 5x
10 17 / cm 2 , acceleration voltage is 40 keV to 200 ke
This is a method for manufacturing an SOI substrate of V. The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the annealing treatment for forming the buried silicon oxide layers 13 and 26 is performed in an oxidizing atmosphere at 10 to 100 atm. This is a method of manufacturing an SOI substrate. According to this method, the buried silicon oxide layer can be formed more stably.

【0010】[0010]

【発明の実施の形態】本発明において、注入するイオン
がArイオン又はSiイオンの場合には、Ar又はSi
の原子量はHeと比べて大きいため、埋込みシリコン酸
化層の表面からの深さに応じてそのイオン注入時のドー
ズ量は1×1015/cm2〜1×1017/cm2であり、
このときの加速電圧は150keV〜200keVであ
る。本発明のイオン注入時の基板温度は500℃〜70
0℃が好ましく、600℃が更に好ましい。アニール処
理は、酸化性雰囲気中、1000℃〜1400℃の温度
範囲で1〜8時間行われる。この処理温度は1300℃
〜1400℃が好ましく、1350℃が更に好ましい。
またその時間は4〜8時間が好ましく、6時間程度が更
に好ましい。酸化性雰囲気としては、10〜100%濃
度の酸素雰囲気が挙げられ、100%濃度に近い高濃度
の酸素雰囲気が好ましい。またイオン注入損傷領域に注
入されたHe原子又はH原子をこの損傷領域より放出し
て空孔領域を形成するためのアニール処理の雰囲気は
0.5〜3%O2、残部不活性ガスの混合ガス雰囲気が
好ましい。酸素を僅かに含むのは、基板表面の荒れを防
ぐためである。シリコン基板の表面研磨はシリコンウェ
ーハ用研磨機、レンズ研磨機などにより軽く行われる。
この研磨では基板表面が厚さ50オングストローム〜5
00オングストローム、好ましくは100オングストロ
ーム程度の深さ磨滅させることが望ましい。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, when the implanted ions are Ar ions or Si ions, Ar or Si is used.
Since the atomic weight of is larger than that of He, the dose amount during ion implantation is 1 × 10 15 / cm 2 to 1 × 10 17 / cm 2 depending on the depth from the surface of the buried silicon oxide layer,
The acceleration voltage at this time is 150 keV to 200 keV. The substrate temperature at the time of ion implantation of the present invention is 500 ° C. to 70 ° C.
0 ° C is preferable, and 600 ° C is more preferable. The annealing treatment is performed in an oxidizing atmosphere at a temperature range of 1000 ° C to 1400 ° C for 1 to 8 hours. This processing temperature is 1300 ℃
1400 degreeC is preferable and 1350 degreeC is more preferable.
The time is preferably 4 to 8 hours, more preferably about 6 hours. Examples of the oxidizing atmosphere include an oxygen atmosphere having a concentration of 10 to 100%, and a high-concentration oxygen atmosphere having a concentration close to 100% is preferable. Further, the atmosphere of the annealing treatment for releasing the He atoms or the H atoms injected into the ion-implanted damaged region from the damaged region to form the vacancy region is 0.5 to 3% O 2 , and the remaining inert gas is mixed. A gas atmosphere is preferred. The small amount of oxygen is contained in order to prevent the surface of the substrate from being roughened. The surface of a silicon substrate is lightly polished by a silicon wafer polishing machine, a lens polishing machine, or the like.
In this polishing, the substrate surface has a thickness of 50 Å to 5 Å.
It is desirable to ablate to a depth of about 100 Å, preferably about 100 Å.

【0011】特に注入イオンがHeイオン又はHイオン
の場合には、He,Hは原子量が小さいため、従来の酸
素イオン注入と比べて、基板の表面近傍のSi層の転位
欠陥が生じにくくなると同時に酸素イオンよりも低い加
速電圧で所定の深さにイオン注入損傷領域を形成するこ
とができる。この加速電圧が低いことに起因して、イオ
ン注入損傷領域に境界が急峻で層厚の小さな埋込みシリ
コン酸化層を形成し易くなり、結果としてSiO2の析
出制御が容易となる。またイオン注入時にSi層表面の
スパッタリングが減少し、基板の表面粗さが小さくな
る。同時に装置内壁のスパッタリングが大幅に低減さ
れ、基板への重金属の汚染が低減される。
In particular, when the implanted ions are He ions or H ions, since the atomic weight of He and H is small, dislocation defects in the Si layer near the surface of the substrate are less likely to occur as compared with conventional oxygen ion implantation. The ion implantation damage region can be formed at a predetermined depth with an acceleration voltage lower than that of oxygen ions. Due to the low acceleration voltage, it becomes easy to form a buried silicon oxide layer having a sharp boundary and a small layer thickness in the ion-implanted damage region, and as a result, it becomes easy to control the precipitation of SiO 2 . Further, during ion implantation, sputtering on the surface of the Si layer is reduced and the surface roughness of the substrate is reduced. At the same time, the sputtering of the inner wall of the device is significantly reduced, and the contamination of the substrate with heavy metals is reduced.

【0012】[0012]

【実施例】次に、本発明の実施例を比較例とともに図面
に基づいて詳しく説明する。 <実施例1>図1(a)及び(b)に示すように、厚さ
625μmのシリコン基板11の所定の領域に次の条件
でHeイオン(He+)を注入した。 加速電圧: 40 keV ドーズ量: 1.0×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板11の表面から約
0.3μmのイオン注入損傷領域12が形成された。イ
オン注入後、図1(c)及び(d)に示すようにシリコ
ン基板11を酸素(100%)の雰囲気中で1325
℃、8時間アニール処理を施して、上記イオン注入損傷
領域12を埋込シリコン酸化層13に変え、SOI基板
10を得た。11aは基板表面側のSi層、11bは基
板裏面側のSi層をそれぞれ示す。
Embodiments of the present invention will now be described in detail with reference to the drawings together with comparative examples. Example 1 As shown in FIGS. 1A and 1B, He ions (He + ) were implanted into a predetermined region of a 625 μm thick silicon substrate 11 under the following conditions. Acceleration voltage: 40 keV Dose amount: 1.0 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. By this ion implantation, an ion implantation damage region 12 of about 0.3 μm was formed from the surface of the silicon substrate 11. After the ion implantation, as shown in FIGS. 1C and 1D, the silicon substrate 11 is subjected to 1325 in an oxygen (100%) atmosphere.
Annealing treatment was performed at 8 ° C. for 8 hours to change the ion-implanted damaged region 12 into a buried silicon oxide layer 13 to obtain an SOI substrate 10. Reference numeral 11a denotes a Si layer on the front surface side of the substrate, and 11b denotes a Si layer on the back surface side of the substrate.

【0013】<実施例2>加速電圧を60keVにした
以外は実施例1と同様にしてイオン注入損傷領域を埋込
みシリコン酸化層に変えたSOI基板を得た。
<Example 2> An SOI substrate was obtained in which the ion implantation damage region was replaced with a buried silicon oxide layer in the same manner as in Example 1 except that the acceleration voltage was set to 60 keV.

【0014】<実施例3>実施例1のHeイオン(He
+)の代わりに次の条件でHイオン(H+)を注入した。 加速電圧: 40 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板の表面から約0.5
μmのイオン注入損傷領域が形成された。イオン注入
後、イオン注入損傷領域を形成したシリコン基板を実施
例1と同様にして高温でアニール処理を施して、上記イ
オン注入損傷領域を埋込シリコン酸化層に変え、SOI
基板を得た。
<Embodiment 3> The He ions (He) of Embodiment 1
Instead of + ), H ions (H + ) were implanted under the following conditions. Accelerating voltage: 40 keV Dose amount: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. About 0.5 from the surface of the silicon substrate by this ion implantation.
A μm ion-implanted damage region was formed. After the ion implantation, the silicon substrate on which the ion-implanted damaged region is formed is annealed at a high temperature in the same manner as in Example 1 to change the ion-implanted damaged region into a buried silicon oxide layer, and the SOI
A substrate was obtained.

【0015】<実施例4>実施例1のHeイオン(He
+)の代わりに次の条件でArイオン(Ar+)を注入し
た。 加速電圧: 200 keV ドーズ量: 5×1016/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板の表面から約0.2
μmのイオン注入損傷領域が形成された。イオン注入
後、イオン注入損傷領域を形成したシリコン基板を実施
例1と同様にして高温でアニール処理を施して、上記イ
オン注入損傷領域を埋込シリコン酸化層に変え、SOI
基板を得た。
<Embodiment 4> The He ion (He) of Embodiment 1
Instead of + ), Ar ions (Ar + ) were implanted under the following conditions. Accelerating voltage: 200 keV Dose amount: 5 × 10 16 / cm 2 Substrate heating temperature: 600 ° C. About 0.2 from the surface of the silicon substrate by this ion implantation.
A μm ion-implanted damage region was formed. After the ion implantation, the silicon substrate on which the ion-implanted damaged region is formed is annealed at a high temperature in the same manner as in Example 1 to change the ion-implanted damaged region into a buried silicon oxide layer, and the SOI
A substrate was obtained.

【0016】<実施例5>実施例1のHeイオン(He
+)の代わりに次の条件でSiイオン(Si+)を注入し
た。 加速電圧: 200 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板の表面から約0.3
μmのイオン注入損傷領域が形成された。イオン注入
後、イオン注入損傷領域を形成したシリコン基板を実施
例1と同様にして高温でアニール処理を施して、上記イ
オン注入損傷領域を埋込シリコン酸化層に変え、SOI
基板を得た。
<Embodiment 5> The He ions (He) of Embodiment 1
Instead of + ), Si ions (Si + ) were implanted under the following conditions. Accelerating voltage: 200 keV Dose amount: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. About 0.3 from the surface of the silicon substrate by this ion implantation.
A μm ion-implanted damage region was formed. After the ion implantation, the silicon substrate on which the ion-implanted damaged region is formed is annealed at a high temperature in the same manner as in Example 1 to change the ion-implanted damaged region into a buried silicon oxide layer, and the SOI
A substrate was obtained.

【0017】<実施例6>図2(a)及び(b)に示す
ように、厚さ625μmのシリコン基板11の所定の領
域に次の条件でHeイオン(He+)を注入した。 加速電圧: 40 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板11の表面から約
0.3μmのイオン注入損傷領域12が形成された。イ
オン注入後、図2(c)及び(d)に示すようにシリコ
ン基板11をAr99%でO21%の混合ガス雰囲気中
で1000℃、1時間アニール処理を施して、イオン注
入損傷領域12に注入されたHe原子をこの損傷領域1
2より放出して空孔領域15を形成し、この空孔領域1
5が形成されたシリコン基板11を酸素(100%)雰
囲気中で1325℃の温度でアニール処理してシリコン
基板11表面から所定の深さの領域に埋込みシリコン酸
化層13に変え、SOI基板10を得た。11aは基板
表面側のSi層、11bは基板裏面側のSi層をそれぞ
れ示す。
Example 6 As shown in FIGS. 2A and 2B, He ions (He + ) were implanted into a predetermined region of a silicon substrate 11 having a thickness of 625 μm under the following conditions. Acceleration voltage: 40 keV Dose amount: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. By this ion implantation, an ion implantation damage region 12 of about 0.3 μm was formed from the surface of the silicon substrate 11. After ion implantation, the silicon substrate 11 is annealed at 1000 ° C. for 1 hour in a mixed gas atmosphere of Ar 99% and O 2 1% as shown in FIGS. He atoms injected into the damaged region 1
2 to form a vacancy region 15, and this vacancy region 1
The silicon substrate 11 on which No. 5 is formed is annealed at a temperature of 1325 ° C. in an oxygen (100%) atmosphere to convert the surface of the silicon substrate 11 into a buried silicon oxide layer 13 in a region of a predetermined depth. Obtained. Reference numeral 11a denotes a Si layer on the front surface side of the substrate, and 11b denotes a Si layer on the back surface side of the substrate.

【0018】<実施例7>加速電圧を60keVにした
以外は実施例6と同様にして空孔領域を埋込みシリコン
酸化層に変えたSOI基板を得た。
<Example 7> An SOI substrate was obtained in which the vacancy region was replaced with a buried silicon oxide layer in the same manner as in Example 6 except that the acceleration voltage was set to 60 keV.

【0019】<実施例8>実施例6のHeイオン(He
+)の代わりに次の条件でHイオン(H+)を注入した。 加速電圧: 40 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板の表面から約0.5
μmのイオン注入損傷領域が形成された。イオン注入
後、イオン注入損傷領域を形成したシリコン基板を実施
例6と同様に処理してSOI基板を得た。
<Embodiment 8> The He ions (He) of Embodiment 6
Instead of + ), H ions (H + ) were implanted under the following conditions. Accelerating voltage: 40 keV Dose amount: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. About 0.5 from the surface of the silicon substrate by this ion implantation.
A μm ion-implanted damage region was formed. After the ion implantation, the silicon substrate on which the ion implantation damaged region was formed was treated in the same manner as in Example 6 to obtain an SOI substrate.

【0020】<比較例1>厚さ625μmのシリコン基
板の所定の領域(例えば、基板表面から約0.4μmの
領域)に次の条件で酸素イオン(O+)を注入した。 加速電圧: 120 keV ドーズ量: 0.4×1018/cm2 基板加熱温度:600℃ シリコン基板11に酸素イオン注入した後、Ar97%
でO23%の混合ガス雰囲気中で1325℃、6時間シ
リコン基板をアニール処理してSOI基板を得た。
Comparative Example 1 Oxygen ions (O + ) were implanted under the following conditions into a predetermined region (for example, a region of about 0.4 μm from the substrate surface) of a 625 μm thick silicon substrate. Accelerating voltage: 120 keV Dose amount: 0.4 × 10 18 / cm 2 Substrate heating temperature: 600 ° C. After implanting oxygen ions into the silicon substrate 11, Ar 97%
Then, the silicon substrate was annealed at 1325 ° C. for 6 hours in a mixed gas atmosphere of O 2 3% to obtain an SOI substrate.

【0021】<実施例9>図3(a)及び(b)に示す
ように、厚さ625μmのシリコン基板21の所定の領
域に次の条件でHeイオン(He+)を注入した。 加速電圧: 40 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板21の表面から約
0.3μmのイオン注入損傷領域22が形成された。イ
オン注入後、図3(c)及び(d)に示すようにシリコ
ン基板21をAr99%でO21%の混合ガス雰囲気中
で1325℃、2時間アニール処理を施して、イオン注
入損傷領域22に注入されたHe原子をこの損傷領域2
2より放出して空孔領域23を形成した。
Example 9 As shown in FIGS. 3A and 3B, He ions (He + ) were implanted into a predetermined region of a silicon substrate 21 having a thickness of 625 μm under the following conditions. Accelerating voltage: 40 keV Dose amount: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. By this ion implantation, an ion implantation damage region 22 of about 0.3 μm was formed from the surface of the silicon substrate 21. After the ion implantation, the silicon substrate 21 is annealed at 1325 ° C. for 2 hours in a mixed gas atmosphere of 99% Ar and 1% O 2 as shown in FIGS. He atoms injected into the damaged region 2
2 to form void regions 23.

【0022】引き続き、次の条件でシリコン基板21内
部に酸素イオン(O+)を注入した。 加速電圧: 150 keV ドーズ量: 4×1017/cm2 基板加熱温度:600℃ シリコン基板21に酸素イオン注入した後、Ar99%
でO21%の混合ガス雰囲気中で1360℃、4時間シ
リコン基板をアニール処理を施してSOI基板を得た。
Subsequently, oxygen ions (O + ) were implanted into the silicon substrate 21 under the following conditions. Accelerating voltage: 150 keV Dose amount: 4 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. After implanting oxygen ions into the silicon substrate 21, Ar 99%
Then, the silicon substrate was annealed at 1360 ° C. for 4 hours in a mixed gas atmosphere of O 2 1% to obtain an SOI substrate.

【0023】<実施例10>イオン注入損傷領域22を
形成したシリコン基板21をAr99%でO21%の混
合ガス雰囲気中で1000℃、2時間アニール処理を施
した以外は、シリコン基板を実施例9と同様に処理して
SOI基板を得た。
<Embodiment 10> A silicon substrate was used except that the silicon substrate 21 having the ion-implanted damaged region 22 was annealed at 1000 ° C. for 2 hours in a mixed gas atmosphere of Ar 99% and O 2 1%. The same process as in Example 9 was carried out to obtain an SOI substrate.

【0024】<評価> (a) 欠陥の密度 実施例1〜実施例10と比較例1の各SOI基板の基板
表面のSi層中の転位欠陥密度を測定した。この転位欠
陥密度はSOI基板を酸化クロムを含む溶液により基板
表面をエッチングし、エッチングで拡大した転位欠陥を
電子顕微鏡で観察することにより求めた。その結果を表
1に示す。
<Evaluation> (a) Defect Density The dislocation defect density in the Si layer on the substrate surface of each of the SOI substrates of Examples 1 to 10 and Comparative Example 1 was measured. The dislocation defect density was obtained by etching the SOI substrate with a solution containing chromium oxide and observing the dislocation defects enlarged by etching with an electron microscope. Table 1 shows the results.

【0025】[0025]

【表1】 [Table 1]

【0026】表1から明らかなように、酸素イオン注入
後にArとO2の混合ガス雰囲気中で高温アニール処理
した比較例1の転位欠陥密度と比べて、Siと反応しな
いHe、H、Ar、Siのイオンを注入した後にO2
囲気又はArとO2の混合ガス雰囲気中で高温アニール
処理した実施例1〜実施例10の転位欠陥密度は、いず
れも小さかった。特に軽い元素であるHeとHをイオン
注入した実施例1〜実施例3、実施例6〜実施例10の
転位欠陥密度は極めて小さかった。
As is clear from Table 1, compared with the dislocation defect density of Comparative Example 1 which was annealed at high temperature in a mixed gas atmosphere of Ar and O 2 after oxygen ion implantation, He, H, Ar, which do not react with Si, The dislocation defect densities of Examples 1 to 10 which were annealed at high temperature in an O 2 atmosphere or a mixed gas atmosphere of Ar and O 2 after implanting Si ions were all low. Particularly, the dislocation defect densities of Examples 1 to 3 and 6 to 10 in which the light elements He and H were ion-implanted were extremely low.

【0027】(b) SOI基板の表面粗さ 実施例1、実施例6、実施例9及び比較例1の各SOI
基板表面の2μm×2μmの領域における表面粗さを原
子間力顕微鏡を用いて測定した。その結果を表2に示
す。表2において、Raは表面粗さのうち平均粗さ、Rm
axは最大高さ、Rzは十点平均粗さを意味する。
(B) Surface Roughness of SOI Substrate Each SOI of Example 1, Example 6, Example 9 and Comparative Example 1
The surface roughness in a 2 μm × 2 μm region on the substrate surface was measured using an atomic force microscope. The results are shown in Table 2. In Table 2, Ra is the average roughness of the surface roughness, Rm
ax means maximum height, and Rz means ten-point average roughness.

【0028】[0028]

【表2】 [Table 2]

【0029】表2から明らかなように、比較例1のSO
I基板の表面粗さは著しく大きかったのに対して、実施
例1、実施例6及び実施例9のSOI基板の表面粗さは
小さくなり、初期のシリコンウェーハ程度であった。
As is clear from Table 2, the SO of Comparative Example 1
The surface roughness of the I substrate was remarkably large, whereas the surface roughness of the SOI substrates of Example 1, Example 6 and Example 9 was small, and was about the initial silicon wafer.

【0030】(c) 重金属の濃度 実施例1及び比較例1のアニール処理後の各SOI基板
の表面Si層中の重金属の濃度を原子吸収法により測定
した。その結果を表3に示す。
(C) Heavy Metal Concentration The concentration of heavy metal in the surface Si layer of each SOI substrate after the annealing treatment of Example 1 and Comparative Example 1 was measured by the atomic absorption method. Table 3 shows the results.

【0031】[0031]

【表3】 [Table 3]

【0032】表3から明らかなように、比較例1のSO
I基板の表面Si層では特にFe,Ni,Cuの重金属
の汚染が顕著であるのに対して、実施例1の表面Si層
ではこれらの重金属濃度が減少していた。
As is clear from Table 3, the SO of Comparative Example 1
Contamination of heavy metals such as Fe, Ni, and Cu was particularly remarkable in the surface Si layer of the I substrate, whereas the concentration of these heavy metals was reduced in the surface Si layer of Example 1.

【0033】(d) 埋込みシリコン酸化層の境界 実施例1、実施例2、実施例6、実施例7、実施例9、
実施例10及び比較例1の各SOI基板の断面を透過電
子顕微鏡で観察し、埋込みシリコン酸化層の境界の急峻
性を観察した。その結果、比較例1の埋込みシリコン酸
化層の境界がそれ程急峻でないのに対して、実施例1、
2、6、7、9、10の埋込みシリコン酸化層の境界は
急峻であった。特に実施例1、実施例6の埋込みシリコ
ン酸化層は加速電圧が実施例2、実施例7よりそれぞれ
低いため、実施例2、実施例7より急峻であった。
(D) Boundary of buried silicon oxide layer Example 1, Example 2, Example 6, Example 7, Example 9,
The cross sections of the SOI substrates of Example 10 and Comparative Example 1 were observed with a transmission electron microscope, and the steepness of the boundary of the embedded silicon oxide layer was observed. As a result, the boundary of the buried silicon oxide layer of Comparative Example 1 is not so steep, while the boundary of Example 1,
The boundaries of the buried silicon oxide layers 2, 6, 7, 9, 10 were steep. In particular, the buried silicon oxide layers of Example 1 and Example 6 had an acceleration voltage lower than that of Examples 2 and 7, respectively, and thus were steeper than those of Examples 2 and 7.

【0034】[0034]

【発明の効果】以上述べたように、本発明のSOI基板
の製造方法によれば、シリコン基板に真空中でシリコン
と反応しないHeイオン等を注入して基板内部にイオン
注入損傷領域を形成した後、この基板を酸化性雰囲気中
で高温でアニール処理するか、又はこの高温のアニール
処理の前に別のアニール処理をして空孔領域を形成する
か、又はこの空孔領域を形成した後、酸素イオンを注入
することにより、酸素原子が基板内部に拡散律速により
拡散し、イオン注入により形成された空孔の存在により
優先的にイオン注入損傷領域に埋込みシリコン酸化層を
形成することができる。従来の酸素イオン注入が極めて
短時間に埋込みシリコン酸化層を形成して格子間シリコ
ン原子を急激に生じていたのに対して、この酸化は拡散
律速で進行するため、格子間シリコン原子の急激な発生
はなく、転位欠陥を抑制することができる。特に注入イ
オンがHeイオン又はHイオンのような原子量が小さい
元素のイオンである場合には、より一層基板の表面近傍
のSi層の転位欠陥が生じにくくなるとともに、酸素イ
オンに比べて低い加速電圧で所定の深さにイオン注入損
傷領域を形成できる。換言すれば、同じ加速電圧でも酸
素イオン注入と比べて本発明のイオン注入ではより深い
領域に埋込みシリコン酸化層を形成することができる。
この低い加速電圧は境界が急峻で層厚の小さな埋込みシ
リコン酸化層の形成を容易にし、SiO2の析出制御を
容易にする。またイオン注入時にSi層表面のスパッタ
リングが減少し、基板の表面粗さが小さくなる。同時に
装置内壁のスパッタリングが大幅に低減され、基板への
重金属の汚染が低減される。
As described above, according to the method for manufacturing an SOI substrate of the present invention, He ions or the like that do not react with silicon in a vacuum are implanted into a silicon substrate to form an ion implantation damaged region inside the substrate. After that, the substrate is annealed at a high temperature in an oxidizing atmosphere, or another anneal process is performed before the high temperature anneal to form a vacancy region, or after the vacancy region is formed. By implanting oxygen ions, oxygen atoms diffuse into the substrate by diffusion control, and the presence of the vacancy formed by the ion implantation can preferentially form a buried silicon oxide layer in the ion implantation damaged region. . While conventional oxygen ion implantation forms a buried silicon oxide layer in a very short time and abruptly generates interstitial silicon atoms, this oxidation progresses in a diffusion-controlled manner, so that abrupt changes in interstitial silicon atoms occur. There is no occurrence, and dislocation defects can be suppressed. In particular, when the implanted ions are He ions or ions of an element having a small atomic weight such as H ions, dislocation defects in the Si layer near the surface of the substrate are more difficult to occur, and the acceleration voltage is lower than that of oxygen ions. The ion implantation damage region can be formed at a predetermined depth. In other words, even with the same acceleration voltage, the buried silicon oxide layer can be formed in a deeper region by the ion implantation of the present invention as compared with the oxygen ion implantation.
This low accelerating voltage facilitates formation of a buried silicon oxide layer having a sharp boundary and a small layer thickness, and facilitates control of precipitation of SiO 2 . Further, during ion implantation, sputtering on the surface of the Si layer is reduced and the surface roughness of the substrate is reduced. At the same time, the sputtering of the inner wall of the device is significantly reduced, and the contamination of the substrate with heavy metals is reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のSOI基板の製造方法を模
式的に示す図。
FIG. 1 is a diagram schematically showing a method of manufacturing an SOI substrate according to an embodiment of the present invention.

【図2】本発明の別の実施例のSOI基板の製造方法を
模式的に示す図。
FIG. 2 is a diagram schematically showing a method for manufacturing an SOI substrate according to another embodiment of the present invention.

【図3】本発明の更に別の実施例のSOI基板の製造方
法を模式的に示す図。
FIG. 3 is a diagram schematically showing a method of manufacturing an SOI substrate according to still another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10,20 SOI基板 11,21 シリコン基板 11a,21a 基板表面のSi層 12,22 イオン注入損傷領域 13,26 埋込みシリコン酸化層 14 格子間シリコン原子 15,23 空孔領域 16,25 酸素原子 24 SiOx領域 10, 20 SOI substrate 11, 21 Silicon substrate 11a, 21a Si layer on substrate surface 12,22 Ion implantation damage region 13,26 Buried silicon oxide layer 14 Interstitial silicon atom 15,23 Vacancy region 16,25 Oxygen atom 24 SiOx region

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/76 R Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/76 R

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板(11)に真空中で少なくとも
Heイオン、Hイオン、Arイオン又はSiイオンを注
入することにより前記シリコン基板(11)内部にイオン注
入損傷領域(12)を形成する工程と、 前記イオン注入損傷領域(12)が形成されたシリコン基板
(11)を酸化性雰囲気中で1000℃〜1400℃の温度
でアニール処理して前記シリコン基板(11)表面から所定
の深さの領域に埋込みシリコン酸化層(13)を形成して前
記基板表面に単結晶Si層(11a)を形成する工程とを含
むことを特徴とするSOI基板の製造方法。
1. A step of forming an ion-implanted damaged region (12) inside the silicon substrate (11) by implanting at least He ions, H ions, Ar ions or Si ions into the silicon substrate (11) in a vacuum. And a silicon substrate on which the ion implantation damage region (12) is formed
(11) is annealed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere to form a buried silicon oxide layer (13) in a region of a predetermined depth from the surface of the silicon substrate (11) to form the surface of the substrate. And a step of forming a single crystal Si layer (11a) on the substrate.
【請求項2】 シリコン基板(11)に真空中で少なくとも
Heイオン又はHイオンを注入することにより前記シリ
コン基板(11)内部にイオン注入損傷領域(12)を形成する
工程と、 前記イオン注入損傷領域(12)が形成されたシリコン基板
(11)を800℃〜1000℃の温度でアニール処理して
前記領域(12)に注入されたHe原子又はH原子を前記領
域(12)より放出して空孔領域(15)を形成する工程と、 前記空孔領域(15)が形成されたシリコン基板(11)を酸化
性雰囲気中で1000℃〜1400℃の温度でアニール
処理して前記シリコン基板(11)表面から所定の深さの領
域に埋込みシリコン酸化層(13)を形成して前記基板表面
に単結晶Si層(11a)を形成する工程とを含むことを特
徴とするSOI基板の製造方法。
2. A step of forming an ion-implanted damaged region (12) inside the silicon substrate (11) by implanting at least He ions or H ions into the silicon substrate (11) in a vacuum, and the ion-implanted damage. Silicon substrate with regions (12) formed
A step of annealing (11) at a temperature of 800 ° C. to 1000 ° C. to release He atoms or H atoms injected into the region (12) from the region (12) to form a vacancy region (15). And annealing the silicon substrate (11) in which the void regions (15) are formed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere to form a region having a predetermined depth from the surface of the silicon substrate (11). And a step of forming a buried silicon oxide layer (13) on the surface of the substrate to form a single crystal Si layer (11a) on the surface of the substrate.
【請求項3】 シリコン基板(21)に真空中で少なくとも
Heイオン又はHイオンを注入することにより前記シリ
コン基板(21)内部にイオン注入損傷領域(22)を形成する
工程と、 前記イオン注入損傷領域(22)が形成されたシリコン基板
(21)を800〜1400℃の温度でアニール処理して前
記領域(22)に注入されたHe原子又はH原子を前記領域
(22)より放出して空孔領域(23)を形成する工程と、 前記シリコン基板(21)内部に酸素イオンを注入して前記
空孔領域(23)を中心にSiOx領域(24)を形成する工程
と、 前記SiOx領域(24)が形成されたシリコン基板(21)を
酸化性雰囲気中で1000℃〜1400℃の温度でアニ
ール処理して前記シリコン基板(21)表面から所定の深さ
の領域に埋込みシリコン酸化層(26)を形成して前記基板
表面に単結晶Si層(21a)を形成する工程とを含むこと
を特徴とするSOI基板の製造方法。
3. A step of forming an ion implantation damage region (22) inside the silicon substrate (21) by implanting at least He ions or H ions into the silicon substrate (21) in a vacuum, and the ion implantation damage. Silicon substrate with regions (22) formed
(21) is annealed at a temperature of 800 to 1400 ° C., and He atoms or H atoms injected into the region (22) are added to the region.
(22) to form vacancy regions (23), and oxygen ions are implanted into the silicon substrate (21) to form SiOx regions (24) around the vacancy regions (23). And a step of annealing the silicon substrate (21) on which the SiOx region (24) is formed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere to obtain a predetermined depth from the surface of the silicon substrate (21). A step of forming a buried silicon oxide layer (26) in the region and forming a single crystal Si layer (21a) on the surface of the substrate.
【請求項4】 アニール処理して埋込シリコン酸化層(1
3,26)を形成した後にシリコン基板(11,21)表面を研磨す
る工程を更に含む請求項1〜3いずれか記載のSOI基
板の製造方法。
4. An embedded silicon oxide layer (1
The method of manufacturing an SOI substrate according to claim 1, further comprising a step of polishing the surface of the silicon substrate (11, 21) after forming (3, 26).
【請求項5】 注入するイオンがHeイオン又はHイオ
ンであるとき、そのイオン注入時のドーズ量が1×10
16/cm2〜5×1017/cm2で、加速電圧が40ke
V〜200keVである請求項1〜4いずれか記載のS
OI基板の製造方法。
5. When the implanted ions are He ions or H ions, the dose amount at the time of implanting the ions is 1 × 10.
16 / cm 2 to 5 × 10 17 / cm 2 , acceleration voltage is 40 ke
It is V-200 keV, S in any one of Claims 1-4.
Manufacturing method of OI substrate.
【請求項6】 埋込シリコン酸化層(13,26)を形成する
ためのアニール処理が酸化性雰囲気中、10〜100気
圧下で行われる請求項1ないし5いずれか記載のSOI
基板の製造方法。
6. The SOI according to claim 1, wherein the annealing treatment for forming the buried silicon oxide layer (13, 26) is performed in an oxidizing atmosphere under 10 to 100 atm.
Substrate manufacturing method.
JP08062534A 1995-03-20 1996-03-19 Method for manufacturing SOI substrate Expired - Fee Related JP3097827B2 (en)

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JP08062534A JP3097827B2 (en) 1995-03-20 1996-03-19 Method for manufacturing SOI substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-60219 1995-03-20
JP6021995 1995-03-20
JP08062534A JP3097827B2 (en) 1995-03-20 1996-03-19 Method for manufacturing SOI substrate

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Publication Number Publication Date
JPH08321594A true JPH08321594A (en) 1996-12-03
JP3097827B2 JP3097827B2 (en) 2000-10-10

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999039380A1 (en) * 1998-02-02 1999-08-05 Nippon Steel Corporation Soi substrate and method for manufacturing the same
JP2002527907A (en) * 1998-10-15 2002-08-27 コミツサリア タ レネルジー アトミーク Method of manufacturing a material layer embedded in another material
JP2004235253A (en) * 2003-01-28 2004-08-19 Fujitsu Ltd Method of manufacturing semiconductor substrate
JP2007027475A (en) * 2005-07-19 2007-02-01 Shin Etsu Handotai Co Ltd Method for manufacturing direct bonded wafer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200478682Y1 (en) * 2014-11-05 2015-11-13 유재정 Multipurpose drying unit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999039380A1 (en) * 1998-02-02 1999-08-05 Nippon Steel Corporation Soi substrate and method for manufacturing the same
EP1052687A1 (en) * 1998-02-02 2000-11-15 Nippon Steel Corporation Soi substrate and method for manufacturing the same
US6617034B1 (en) 1998-02-02 2003-09-09 Nippon Steel Corporation SOI substrate and method for production thereof
EP1052687A4 (en) * 1998-02-02 2007-08-15 Nippon Steel Corp Soi substrate and method for manufacturing the same
JP2002527907A (en) * 1998-10-15 2002-08-27 コミツサリア タ レネルジー アトミーク Method of manufacturing a material layer embedded in another material
JP2004235253A (en) * 2003-01-28 2004-08-19 Fujitsu Ltd Method of manufacturing semiconductor substrate
JP4531339B2 (en) * 2003-01-28 2010-08-25 富士通セミコンダクター株式会社 Manufacturing method of semiconductor substrate
JP2007027475A (en) * 2005-07-19 2007-02-01 Shin Etsu Handotai Co Ltd Method for manufacturing direct bonded wafer

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