JPH1174276A - Epitaxial silicon semiconductor substrate and its manufacture - Google Patents

Epitaxial silicon semiconductor substrate and its manufacture

Info

Publication number
JPH1174276A
JPH1174276A JP24765797A JP24765797A JPH1174276A JP H1174276 A JPH1174276 A JP H1174276A JP 24765797 A JP24765797 A JP 24765797A JP 24765797 A JP24765797 A JP 24765797A JP H1174276 A JPH1174276 A JP H1174276A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
silicon semiconductor
substrate
epitaxial
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24765797A
Other languages
Japanese (ja)
Inventor
Sumio Miyazaki
澄夫 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP24765797A priority Critical patent/JPH1174276A/en
Publication of JPH1174276A publication Critical patent/JPH1174276A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial silicon semiconductor substrate that performs improved gettering for all heavy metal impurities, irrespective of diffusion coefficients in silicon. SOLUTION: After mirror polishing a silicon semiconductor substrate 1, ions are implanted from the surface of the substrate, so as to form a dislocation/ distortion layer 2 near the surface of the substrate, and a silicon epitaxial layer 3 is formed on the surface of the substrate through an epitaxial growth. Thus, there is no adverse effects in a region approximately several μm from the surface to be used for the device process, and gettering can be performed for heavy metal elements, irrespective of high or low diffusion coefficients in silicon.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、エピタキシャル
シリコン半導体基板の改良に係り、半導体基板製造プロ
セスにおいて、半導体基板を鏡面研磨後の工程からエピ
タキシャル層を形成する以前の工程でシリコン半導体基
板表面側よりイオン注入を行うことにより、重金属不純
物のゲッタリング能力を向上させたエピタキシャルシリ
コン半導体基板とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an epitaxial silicon semiconductor substrate. In a semiconductor substrate manufacturing process, a semiconductor substrate is mirror-polished to a step before forming an epitaxial layer from a surface of a silicon semiconductor substrate. The present invention relates to an epitaxial silicon semiconductor substrate having improved gettering ability of heavy metal impurities by performing ion implantation, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体デバイスの微細化に伴い、
WELL拡散層の形成に高エネルギーイオン注入が用い
られるようになり、また、接合深さをより浅くするため
に、デバイスプロセスの温度は1000℃以下の低温で
行われるようになってきた。このために、酸素外方拡散
が充分に起こらず表面近傍でのDZ層の形成が困難にな
ることから、基板の酸素濃度を低下させることが行われ
てきたが、表面近傍での結晶欠陥の発生を完全に抑制す
ることは困難であった。
2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices,
High energy ion implantation has been used to form the WELL diffusion layer, and the device process has been performed at a low temperature of 1000 ° C. or less in order to make the junction depth shallower. For this reason, since oxygen outward diffusion does not sufficiently occur and it is difficult to form a DZ layer near the surface, the oxygen concentration of the substrate has been reduced. It was difficult to completely suppress the occurrence.

【0003】かかる状況から、結晶欠陥をほぼ完全に含
まない高品質のエピタキシャル層をシリコンウェーハ上
に成長させたいわゆるシリコンエピタキシャルウェーハ
が、今日の高集積デバイスに多く用いられるようになっ
てきた。
[0003] Under such circumstances, a so-called silicon epitaxial wafer in which a high-quality epitaxial layer substantially free of crystal defects is grown on a silicon wafer has come to be widely used in today's highly integrated devices.

【0004】従来、エピタキシャルシリコン半導体基板
として使用されるウェーハは、おおよそ、 インゴット
からのスライス→ラッピング→エッチング→鏡面研磨
なる工程にて製造されている。
Conventionally, a wafer used as an epitaxial silicon semiconductor substrate is roughly sliced from an ingot → lapping → etching → mirror polishing.
It is manufactured in the following process.

【0005】このエピタキシャルシリコン半導体基板の
ゲッタリング源としては、基板裏面に損傷を施すBSD
タイプ、エッチングまたは鏡面研磨後、減圧CVD法等
で裏面側表面に多結晶シリコン膜を形成するPBSタイ
プのものがあり、またボロンを高濃度にドープした基板
を用いたり、さらにシリコン半導体基板内部の酸素析出
物によるもの(IG)等がある。
As a gettering source of this epitaxial silicon semiconductor substrate, a BSD which damages the back surface of the substrate is used.
After the etching or mirror polishing, there is a PBS type in which a polycrystalline silicon film is formed on the back side surface by a low pressure CVD method or the like, and a substrate doped with boron at a high concentration is used. There is an oxygen precipitate (IG) and the like.

【0006】[0006]

【発明が解決しようとする課題】エピタキシャルシリコ
ン半導体基板において、表面より重金属汚染が生じた場
合にシリコン中での拡散係数が大きい重金属元素(鉄、
銅等)は通常のデバイス工程の熱処理で基板裏面のゲッ
タリング源および基板内部のゲッタリング源まで十分に
拡散が可能である。
SUMMARY OF THE INVENTION In the epitaxial silicon semiconductor substrate, when heavy metal contamination occurs from the surface, a heavy metal element (iron, iron, etc.) having a large diffusion coefficient in silicon.
Copper and the like can be sufficiently diffused to the gettering source on the back surface of the substrate and the gettering source inside the substrate by heat treatment in a normal device process.

【0007】しかし、シリコン中での拡散係数が小さい
重金属元素(モリブデン等)はシリコン半導体基板裏面
のゲッタリング源およびシリコン半導体基板内部のゲッ
タリング源まで十分に拡散できず、エピタキシャル層に
残っていることを本発明者は確認した。
However, heavy metal elements (such as molybdenum) having a small diffusion coefficient in silicon cannot sufficiently diffuse to the gettering source on the back surface of the silicon semiconductor substrate and the gettering source inside the silicon semiconductor substrate, and remain in the epitaxial layer. The present inventors have confirmed this.

【0008】また、このような状態ではエピタキシャル
シリコン半導体基板のライフタイムを悪くすることを本
発明者は確認し、報告(宮崎他;第40回応物予稿19
93年春30p‐ZP‐12)した。
Further, the present inventors have confirmed that in such a state, the life time of the epitaxial silicon semiconductor substrate is deteriorated, and have reported (Miyazaki et al .;
It was 30p-ZP-12 in the spring of 1993.

【0009】この発明は、シリコン中での拡散係数が大
きい元素、小さい元素共に十分にゲッタリング可能な、
すなわち全ての重金属不純物のゲッタリング能力を向上
させたエピタキシャルシリコン半導体基板とその製造方
法の提供を目的とする。
According to the present invention, an element having a large diffusion coefficient in silicon and an element having a small diffusion coefficient can be sufficiently gettered.
That is, it is an object of the present invention to provide an epitaxial silicon semiconductor substrate having improved gettering ability of all heavy metal impurities and a method of manufacturing the same.

【0010】[0010]

【課題を解決するための手段】発明者らは、重金属不純
物のゲッタリング能力を向上させるゲッタリング源を目
的に種々検討した結果、イオン注入による転位・歪み層
の導入に着目した。すなわち、半導体デバイスプロセス
では高エネルギーイオン注入が用いられるが、従来のエ
ピタキシャルシリコン半導体基板製造プロセスにおいて
は、シリコン半導体基板にエピタキシャル層を形成する
以前の工程でイオン注入を施すことはない。それは、イ
オン注入により生じた表面近傍の転位、歪み等の存在
は、デバイスに悪影響を与えるためである。
Means for Solving the Problems The inventors of the present invention have conducted various studies for a gettering source for improving the gettering ability of heavy metal impurities, and have focused on the introduction of dislocation / strain layers by ion implantation. That is, high energy ion implantation is used in a semiconductor device process, but in a conventional epitaxial silicon semiconductor substrate manufacturing process, ion implantation is not performed in a step before an epitaxial layer is formed on a silicon semiconductor substrate. This is because the presence of dislocations, strains, and the like near the surface caused by ion implantation adversely affects the device.

【0011】発明者らは、イオン注入による転位・歪み
層の導入を目的に種々検討した結果、シリコン半導体基
板を鏡面研磨後、基板表面よりイオン注入を行い基板表
面近傍に転位・歪み層を形成し、その後基板表面にシリ
コン層をエピタキシャル成長、成膜することにより、デ
バイスプロセスで使用される表面より数μm程度の領域
においては何ら悪影響がないことを知見し、この発明を
完成した。
As a result of various studies aimed at introducing a dislocation / strain layer by ion implantation, the inventors of the present invention have conducted a mirror polishing of a silicon semiconductor substrate and then implanted ions from the substrate surface to form a dislocation / strain layer near the substrate surface. Then, the inventors have found that there is no adverse effect in a region about several μm from the surface used in the device process by epitaxially growing and forming a silicon layer on the substrate surface, and completed the present invention.

【0012】この発明による、基板表面近傍にイオン注
入による転位・歪み層を有し、基板表面上に成膜したエ
ピタキシャルシリコン層を有するエピタキシャルシリコ
ン半導体基板は、エピタキシャル層付近にゲッタリング
源をもつことで、シリコン中での拡散係数の大きい重金
属元素、小さい重金属元素にかかわらずゲッタリングが
可能であり、かつデバイス工程に供される領域がデバイ
スに何ら悪影響のないエピタキシャルシリコン半導体基
板である。
According to the present invention, an epitaxial silicon semiconductor substrate having a dislocation / strain layer formed by ion implantation near the substrate surface and having an epitaxial silicon layer formed on the substrate surface has a gettering source near the epitaxial layer. Thus, gettering is possible regardless of a heavy metal element having a large diffusion coefficient in silicon and a heavy metal element having a small diffusion coefficient, and a region provided for a device process is an epitaxial silicon semiconductor substrate having no adverse effect on a device.

【0013】[0013]

【発明の実施の形態】シリコン半導体基板におけるMo
不純物の電気特性への影響を調べるため、CZ法による
6インチ、P(100)、N(100)、酸素濃度12
×1017atoms/cc(ASTM F‐121、1
979)、比抵抗11Ωcmのシリコン半導体基板を用
い、Mo水溶液でスピンコート汚染後、乾燥酸素中10
00℃、10分の熱処理を行った。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Mo on a silicon semiconductor substrate
In order to investigate the influence of the impurities on the electric characteristics, 6 inches by PZ method, P (100), N (100), oxygen concentration 12
× 10 17 atoms / cc (ASTM F-121, 1
979), using a silicon semiconductor substrate with a specific resistance of 11 Ωcm, spin coating with Mo aqueous solution,
Heat treatment was performed at 00 ° C. for 10 minutes.

【0014】汚染後の表面のMo濃度及び熱処理後の酸
化膜中のMo濃度は、気相分解法により回収後、ICP
‐MS(ネブライザー法)により分析した。評価につい
ては、再結合ライフタイム(τr)の測定はμ‐wav
e Photoconductive Decay(μ
‐PCD)法により行った。その結果を図2にモリブデ
ン(Mo)の表面汚染量とシリコンの再結合ライフタイ
ムの関係を示すごとく、Moはシリコンの再結合ライフ
タイムを悪くすることがわかる。
The concentration of Mo on the surface after the contamination and the concentration of Mo in the oxide film after the heat treatment are determined by ICP after recovery by a gas phase decomposition method.
-Analyzed by MS (nebulizer method). For evaluation, the measurement of recombination lifetime (τr) is μ-wav.
e Photoconductive Decay (μ
-PCD) method. As a result, FIG. 2 shows the relationship between the surface contamination amount of molybdenum (Mo) and the recombination lifetime of silicon. It can be seen that Mo deteriorates the recombination lifetime of silicon.

【0015】また、表1にMo、鉄(Fe)および銅
(Cu)のシリコン中での拡散距離を比較した表を示
す。この表より、MoはFeやCuに比べ拡散速度が極
めて遅い元素であることがわかる。例えば、エピタキシ
ャルシリコン半導体基板表面側よりMo汚染が起こった
場合、厚さ600μmのエピタキシャルシリコン半導体
基板の裏面側へ到達するには、1000℃で1000時
間以上の時間を要するため裏面に形成したゲッタリング
源では通常行われているデバイス工程の熱処理中にはゲ
ッタリング不可能であることが容易に想像できる。
Table 1 shows a comparison of diffusion distances of Mo, iron (Fe) and copper (Cu) in silicon. From this table, it can be seen that Mo is an element whose diffusion rate is much lower than that of Fe or Cu. For example, when Mo contamination occurs from the front side of the epitaxial silicon semiconductor substrate, it takes 1000 hours or more at 1000 ° C. to reach the back side of the epitaxial silicon semiconductor substrate having a thickness of 600 μm. It is easy to imagine that gettering is not possible during the heat treatment of the device process that is normally performed at the source.

【0016】従って、シリコン中での拡散速度の遅い元
素をゲッタリングするにはエピタキシャルシリコン半導
体基板に用いるシリコン半導体基板の表面近傍にゲッタ
リング源を形成する必要がある。
Therefore, to getter an element having a low diffusion rate in silicon, it is necessary to form a gettering source near the surface of the silicon semiconductor substrate used for the epitaxial silicon semiconductor substrate.

【0017】[0017]

【表1】 [Table 1]

【0018】図1に基づいてこの発明によるエピタキシ
ャルシリコン半導体基板の製造方法を説明する。図1A
に示すごとく、シリコン半導体基板1表面よりイオン注
入を行う。このイオン注入により図1Bに示すごとく、
該基板1の表面近傍には転位・歪み層2が形成され、こ
の部分がゲッタリング源となる。表面近傍に形成された
ゲッタリング源により、拡散係数の小さい元素について
もゲッタリングが可能となる。
Referring to FIG. 1, a method for manufacturing an epitaxial silicon semiconductor substrate according to the present invention will be described. FIG. 1A
As shown in the figure, ions are implanted from the surface of the silicon semiconductor substrate 1. By this ion implantation, as shown in FIG.
A dislocation / strain layer 2 is formed near the surface of the substrate 1, and this portion serves as a gettering source. The gettering source formed near the surface enables gettering even for an element having a small diffusion coefficient.

【0019】しかしながら、イオン注入により形成され
たゲッタリング源である転位・歪み層2は、このまま基
板を使用するとデバイス形成領域内に存在するため、イ
オン注入により生じた転位・歪み等によりデバイスに悪
影響を及ぼすため、図1Cに示すごとく、イオン注入を
施しゲッタリング源の転位・歪み層2を形成した基板1
にエピタキシャル層3を形成することにより、デバイス
プロセスで使用される領域、すなわち表面より数μm程
度はエピタキシャル層3であり、転位・歪み等は存在し
ないためデバイスに供することが可能である。
However, the dislocation / strain layer 2, which is a gettering source formed by ion implantation, is present in the device formation region when the substrate is used as it is, so that the dislocation / strain caused by the ion implantation adversely affects the device. As shown in FIG. 1C, a substrate 1 on which a dislocation / strain layer 2 of a gettering source is formed by performing ion implantation.
By forming the epitaxial layer 3 on the substrate, the region used in the device process, that is, the epitaxial layer 3 is about several μm from the surface, and it can be used for a device because there is no dislocation or distortion.

【0020】さらに、この発明によるエピタキシャルシ
リコン半導体基板は、エピタキシャル層3の近くにゲッ
タリング源が存在しているため、従来のエピタキシャル
シリコン半導体基板よりもゲッタリング能力が優れてい
る。
Furthermore, the gettering source is present near the epitaxial layer 3 in the epitaxial silicon semiconductor substrate according to the present invention, so that the gettering ability is superior to the conventional epitaxial silicon semiconductor substrate.

【0021】この発明において、ゲッタリング源である
転位・歪み層を形成するためのイオン注入の条件は、要
求されるゲッタリング源の強度、表面からの深さなどに
応じて、イオンの注入量、注入エネルギー等を適宜選定
することにより制御可能である。好ましくは、イオン種
は水素、ヘリウム等の軽元素でデバイスへの影響のない
ものがよい。注入量は、1×1015atoms/cm2
以上、1×1018atoms/cm2以下がよい。注入
エネルギーは、30keV〜300keVがよい。
In the present invention, the conditions of the ion implantation for forming the dislocation / strain layer as the gettering source depend on the required intensity of the gettering source, the depth from the surface, and the like. It can be controlled by appropriately selecting the implantation energy and the like. Preferably, the ionic species is a light element such as hydrogen or helium which does not affect the device. The injection amount is 1 × 10 15 atoms / cm 2
As described above, the density is preferably 1 × 10 18 atoms / cm 2 or less. The implantation energy is preferably 30 keV to 300 keV.

【0022】[0022]

【実施例】比抵抗10Ωcm、酸素濃度12〜15×1
17atoms/cc(ASTMF‐121、197
9)のシリコン半導体基板(1)と、このシリコン半導
体基板(1)に比抵抗10Ωcm、酸素濃度12〜15
×1017/atoms/ccのエピタキシャル層を設け
たエピタキシャルシリコン半導体基板(2)、さらに前
記エピタキシャルシリコン半導体基板(2)と同等のス
ペックからなるこの発明の製造方法によるエピタキシャ
ルシリコン半導体基板(3)を作製した。なお、イオン
注入の条件は、イオン種はヘリウム(He)、注入量1
×1016atoms/cm2、注入エネルギー40ke
Vである。
[Example] Specific resistance 10Ωcm, oxygen concentration 12-15 × 1
0 17 atoms / cc (ASTMF-121, 197
9) A silicon semiconductor substrate (1) having a specific resistance of 10 Ωcm and an oxygen concentration of 12 to 15
An epitaxial silicon semiconductor substrate (2) provided with an epitaxial layer of × 10 17 / atoms / cc, and an epitaxial silicon semiconductor substrate (3) according to the manufacturing method of the present invention having specifications equivalent to those of the epitaxial silicon semiconductor substrate (2). Produced. The conditions of the ion implantation are as follows: the ion species is helium (He);
× 10 16 atoms / cm 2 , implantation energy 40 ke
V.

【0023】上記のシリコン半導体基板を用いて、Mo
汚染後にMo濃度の測定を行った。Moの表面汚染はス
ピンコート法により行い、汚染量は1×1012atom
s/cm2である。また、Moの拡散熱処理は1000
℃×1時間、窒素雰囲気中で行った。Mo濃度はDLT
S(Deep Level Transient Sp
ectroscopy)法により測定した。
Using the above silicon semiconductor substrate, Mo
After the contamination, the Mo concentration was measured. The surface contamination of Mo is performed by a spin coating method, and the contamination amount is 1 × 10 12 atoms.
s / cm 2 . Mo diffusion heat treatment is 1000
C. for 1 hour in a nitrogen atmosphere. Mo concentration is DLT
S (Deep Level Transient Sp)
(Ectroscopy) method.

【0024】図3に3種類のシリコン半導体基板を用い
たMo濃度の比較を示す。(1)〜(3)の各々のサン
プル水準は、(1)シリコン半導体基板:比抵抗10Ω
・cm、酸素濃度12〜15×1017atoms/c
c、(2)エピタキシャルシリコン半導体基板:シリコ
ン半導体基板の比抵抗15Ω・cm、エピタキシャル層
の比抵抗10Ω・cmで酸素濃度はそれぞれ(1)と同
じである。(3)Heイオン注入を施したシリコン半導
体基板にエピタキシャル層を形成したエピタキシャルシ
リコン半導体基板:シリコン半導体基板、エピタキシャ
ル層の各々の比抵抗、酸素濃度は(2)と同じである。
FIG. 3 shows a comparison of Mo concentration using three types of silicon semiconductor substrates. The sample level of each of (1) to (3) is (1) silicon semiconductor substrate: specific resistance 10Ω
・ Cm, oxygen concentration 12-15 × 10 17 atoms / c
c, (2) Epitaxial silicon semiconductor substrate: The specific resistance of the silicon semiconductor substrate is 15 Ω · cm, the specific resistance of the epitaxial layer is 10 Ω · cm, and the oxygen concentration is the same as that of (1). (3) Epitaxial silicon semiconductor substrate in which an epitaxial layer is formed on a silicon semiconductor substrate on which He ion implantation has been performed: The specific resistance and oxygen concentration of the silicon semiconductor substrate and the epitaxial layer are the same as in (2).

【0025】図3よりMoはシリコン半導体基板にイオ
ン注入を施したエピタキシャルシリコン半導体基板での
み濃度の低下がみられた。これはイオン注入したことに
より表面近傍にゲッタリング源が形成されMoがゲッタ
リングされたことを示している。ここではMoの結果の
みを示したが、Fe、Cuについてもイオン注入を施し
たエピタキシャルシリコン半導体基板で最も濃度の低下
がみられた。
FIG. 3 shows that the concentration of Mo decreased only in the epitaxial silicon semiconductor substrate obtained by implanting ions into the silicon semiconductor substrate. This indicates that the gettering source was formed near the surface by the ion implantation, and Mo was gettered. Here, only the result of Mo is shown, but the concentration of Fe and Cu also decreased most in the epitaxial silicon semiconductor substrate into which the ion implantation was performed.

【0026】[0026]

【発明の効果】この発明は、シリコン半導体基板を鏡面
研磨後、基板表面よりイオン注入を行い基板表面近傍に
転位・歪み層を形成し、その後基板表面にシリコン層を
エピタキシャル成長、成膜することにより、デバイスプ
ロセスで使用される表面より数μm程度の領域において
は何ら悪影響がなく、シリコン中での拡散係数の大きい
重金属元素、小さい重金属元素にかかわらずゲッタリン
グが可能である。
According to the present invention, after a silicon semiconductor substrate is mirror-polished, ions are implanted from the substrate surface to form dislocation / strain layers near the substrate surface, and then a silicon layer is epitaxially grown and formed on the substrate surface. There is no adverse effect in the region about several μm from the surface used in the device process, and gettering is possible regardless of the heavy metal element having a large diffusion coefficient in silicon and the heavy metal element having a small diffusion coefficient.

【図面の簡単な説明】[Brief description of the drawings]

【図1】A,B,Cはこの発明によるエピタキシャルシ
リコン半導体基板の製造方法を示す基板の断面説明図で
ある。
FIGS. 1A, 1B, and 1C are cross-sectional views of a substrate showing a method for manufacturing an epitaxial silicon semiconductor substrate according to the present invention.

【図2】表面Mo汚染濃度と再結合ライフタイムとの関
係を示すグラフである。
FIG. 2 is a graph showing the relationship between surface Mo contamination concentration and recombination lifetime.

【図3】実施例におけるシリコン半導体基板違いと表面
Mo汚染濃度との関係を示すグラフである。
FIG. 3 is a graph showing the relationship between the difference in silicon semiconductor substrate and the concentration of surface Mo contamination in Examples.

【符号の説明】[Explanation of symbols]

1 シリコン半導体基板 2 転位・歪み層 3 エピタキシャル層 Reference Signs List 1 silicon semiconductor substrate 2 dislocation / strain layer 3 epitaxial layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板表面近傍にイオン注入による転位・
歪み層を有し、基板表面上に成膜したエピタキシャルシ
リコン層を有するエピタキシャルシリコン半導体基板。
Claims: 1. Dislocation by ion implantation near the surface of a substrate
An epitaxial silicon semiconductor substrate having a strained layer and having an epitaxial silicon layer formed on a substrate surface.
【請求項2】 シリコン半導体基板を鏡面研磨後、基板
表面よりイオン注入を行い基板表面近傍に転位・歪み層
を形成し、その後基板表面にシリコン層をエピタキシャ
ル成長、成膜するエピタキシャルシリコン半導体基板の
製造方法。
2. Manufacturing an epitaxial silicon semiconductor substrate in which a silicon semiconductor substrate is mirror-polished, ion implantation is performed from the substrate surface to form a dislocation / strain layer near the substrate surface, and then a silicon layer is epitaxially grown and formed on the substrate surface. Method.
JP24765797A 1997-08-27 1997-08-27 Epitaxial silicon semiconductor substrate and its manufacture Pending JPH1174276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24765797A JPH1174276A (en) 1997-08-27 1997-08-27 Epitaxial silicon semiconductor substrate and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24765797A JPH1174276A (en) 1997-08-27 1997-08-27 Epitaxial silicon semiconductor substrate and its manufacture

Publications (1)

Publication Number Publication Date
JPH1174276A true JPH1174276A (en) 1999-03-16

Family

ID=17166742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24765797A Pending JPH1174276A (en) 1997-08-27 1997-08-27 Epitaxial silicon semiconductor substrate and its manufacture

Country Status (1)

Country Link
JP (1) JPH1174276A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004165225A (en) * 2002-11-08 2004-06-10 Sony Corp Manufacturing method of semiconductor substrate, manufacturing method of solid state imaging device, and screening method for solid state imaging devices
JP2007281119A (en) * 2006-04-05 2007-10-25 Sumco Corp Wafer for evaluating heat treatment, method of evaluating heat treatment, and method of manufacturing semiconductor wafer
JP2009206385A (en) * 2008-02-29 2009-09-10 Shin Etsu Handotai Co Ltd Silicon wafer with strained silicon layer formed, and method of manufacturing the same
JP2009252759A (en) * 2008-04-01 2009-10-29 Shin Etsu Handotai Co Ltd Silicon single crystal wafer for semiconductor device and manufacturing method thereof
JP2014099478A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination of epitaxial silicon wafer and method for evaluating contamination in furnace of epitaxial growth device
CN104823269A (en) * 2012-11-13 2015-08-05 胜高股份有限公司 Production method for semiconductor epitaxial wafer, semiconductor epitaxial wafer, and production method for solid-state imaging element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004165225A (en) * 2002-11-08 2004-06-10 Sony Corp Manufacturing method of semiconductor substrate, manufacturing method of solid state imaging device, and screening method for solid state imaging devices
JP2007281119A (en) * 2006-04-05 2007-10-25 Sumco Corp Wafer for evaluating heat treatment, method of evaluating heat treatment, and method of manufacturing semiconductor wafer
JP2009206385A (en) * 2008-02-29 2009-09-10 Shin Etsu Handotai Co Ltd Silicon wafer with strained silicon layer formed, and method of manufacturing the same
JP2009252759A (en) * 2008-04-01 2009-10-29 Shin Etsu Handotai Co Ltd Silicon single crystal wafer for semiconductor device and manufacturing method thereof
JP2014099478A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for evaluating contamination of epitaxial silicon wafer and method for evaluating contamination in furnace of epitaxial growth device
CN104823269A (en) * 2012-11-13 2015-08-05 胜高股份有限公司 Production method for semiconductor epitaxial wafer, semiconductor epitaxial wafer, and production method for solid-state imaging element

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