JP3480479B2 - Method for manufacturing SOI substrate - Google Patents

Method for manufacturing SOI substrate

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Publication number
JP3480479B2
JP3480479B2 JP06573196A JP6573196A JP3480479B2 JP 3480479 B2 JP3480479 B2 JP 3480479B2 JP 06573196 A JP06573196 A JP 06573196A JP 6573196 A JP6573196 A JP 6573196A JP 3480479 B2 JP3480479 B2 JP 3480479B2
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temperature
substrate
heating rate
silicon oxide
rate
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JPH09260622A (en
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充 須藤
勝 高松
哲弥 中井
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三菱住友シリコン株式会社
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Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は絶縁層上にSi層を
形成したSOI(Silicon-On-Insulator)基板の製造方
法に関する。更に詳しくはSIMOX(Separation by
Implanted Oxygen)技術によるSOI基板の製造方法に
関するものである。 【0002】 【従来の技術】SOI基板は将来のULSI基板として
注目されている。このSOI基板の製造方法には、シリ
コン基板同士を絶縁膜を介して貼り合わせる貼り合わせ
法、絶縁性基板又は絶縁性薄膜を表面に有する基板の上
にシリコン薄膜を堆積させる方法、SIMOX法などが
ある。このSIMOX法は、シリコン基板の内部に絶縁
層を埋込む法の1つであって、具体的にはシリコン基板
内部に高濃度の酸素イオンを注入した後、高温でアニー
ル処理してこのシリコン基板表面から所定の深さの領域
に埋込みシリコン酸化層を形成し、その表面側のSi層
を活性領域とする方法である。このSIMOX法は、上
記貼り合わせ方法のように表面のSi層を研削研磨する
ことなく、均一な厚さの活性なSi層が得られる有力な
方法である。 【0003】近年、この酸素イオンの注入量を低減し、
イオン注入装置の処理時間を短縮してSOI基板の製造
コストを低下させる、低ドーズ技術が実用化し始めてい
る。この低ドーズ技術では、例えば加速エネルギ180
keV、注入量4×1017/cm2で酸素イオン注入し
た後、1350℃で熱処理している。この低ドーズSI
MOX法により、SOI基板中の埋込みシリコン酸化層
を連続化し、かつこの酸化層中に未酸化の島状のSi領
域(Si島)を作らせないためには、酸素イオン注入量
の厳格な制御が極めて重要である。 【0004】 【発明が解決しようとする課題】しかし、従来の低ドー
ズSIMOX法で十分に制御した条件で酸素イオン注入
しても、埋込みシリコン酸化層のピンホール密度が30
個/cm2以上であることが報告されている(M.Imai et
al.,"The Status and Future of Low-Dose SIMOX Tech
nology",Extended Abstracts of the 1995 Internation
al Conference on Solid State Devices and Material
s, Osaka, 1995, pp.557-559)。このピンホール密度が
大きいとデバイス間の分離を十分に行うことができな
い。ピンホール密度を低減するために、特開平7−26
3538号公報に示されるITOX(Internal Thermal
Oxidation)技術が提案されている。この技術はSIM
OX法でアニール処理した直後に更に高温の酸素雰囲気
中でアニール処理するもので、埋込みシリコン酸化層の
層厚が増加し、ピンホールがある場合にはこれを埋める
技術である。しかしながら、このITOX技術によって
もピンホール密度は5個/cm2程度存在すると報告さ
れている(上掲のM.Imai et al.の文献)。 【0005】本発明の目的は、基板表面から所定の深さ
の領域にピンホール密度が極めて小さい高品質の埋込み
シリコン酸化層を形成するSOI基板の製造方法を提供
することにある。本発明の別の目的は、Si層と埋込み
シリコン酸化層との界面の平坦度を良好にするSOI基
板の製造方法を提供することにある。【0006】 【課題を解決するための手段】請求項1に係る発明は、
図1及び図2に示すように、シリコン基板11内部に酸
素イオンを注入した後、最終所定温度T0まで昇温して
この最終所定温度T0を所定時間t保持するアニール処
理を行うことによりシリコン基板11表面から所定の深
さの領域に埋込みシリコン酸化層12を形成し、この基
板11表面に活性なSi層11aを形成するSOI基板
の製造方法において、アニール処理時の昇温速度が少な
くとも2段階v1,v2であって、上記最終所定温度T0
に達するまで昇温速度を順次減速し、最初の昇温速度(v
1 )が10〜3℃/分であって、この昇温速度(v 1 )で12
50℃以上1350℃未満の範囲内の第1所定温度(T 1 )
まで昇温し、最終の昇温速度(v 2 )が7〜0.1℃/分で
あって、この昇温速度(v 2 )で1350℃以上シリコン融
点温度未満の最終所定温度(T 0 )まで昇温することを特徴
とするSOI基板の製造方法である。 【0007】埋込みシリコン酸化層は、温度が上がるに
つれて小さなシリコン酸化物析出物が溶解しより大きな
析出物に吸収されるという、オストワルド成長(Ostwal
d ripening)で形成される。低ドーズSIMOX法によ
れば、シリコン基板におけるシリコン酸化物の析出は、
アニール処理の初期では酸素濃度分布に従ってシリコン
と酸素が反応してシリコン酸化物の析出物を形成し、あ
る程度オストワルド成長が進むと、図2に示すように基
板の深さ方向に酸素注入に伴うダメージピーク位置Aと
酸素注入ピーク位置Bの主として2箇所で起こる。そし
て温度の上昇とともにダメージピーク位置Aの析出物が
酸素注入ピーク位置Bの析出物に取り込まれ、最終的に
は1つのシリコン酸化層となる。図2の基板11の右側
には、ダメージ分布線図及び酸素濃度分布線図を示す。
従来のアニール処理は単一の昇温速度で昇温し、所定温
度に達したところで所定時間保持される。昇温速度が比
較的速い場合、例えば5℃/分以上の場合には所定温
度、例えば1300℃以上に達すると、この昇温速度に
オストワルド成長が追いついていけず、埋込みシリコン
酸化層以外にも析出物は残存するようになり、シリコン
酸化物が完全に取り込まれていない分だけピンホールも
存在する。その後の長時間保持のアニール処理で析出物
を埋込みシリコン酸化層に取り込んでいる。この析出物
はシリコンの酸化に伴って放出された格子間シリコンに
起因した欠陥を伝って埋込みシリコン酸化層と合体す
る。そのためピンホール上に十分な欠陥が形成されてい
ないと、ピンホールは埋まらない。一方、昇温速度が比
較的遅い場合、例えば1℃/分以下の場合には、形成さ
れた析出物がオストワルド成長時に安定なものとなり、
長時間保持のアニール処理を行っても溶解させることが
できず、最終的には埋込みシリコン酸化層以外に析出物
が存在してしまうという不具合を生じる。 【0008】 【0009】この発明では、最初の昇温速度v1を10
〜3℃/分にして、減速した最終の昇温速度v2を7〜
0.1℃/分にする。最初の昇温速度v1で1250℃
以上1350℃未満の範囲内の第1所定温度T1まで昇
温し、最終の昇温速度v2で1350℃以上シリコン融
点温度未満の最終所定温度T0まで昇温する。その後、
最終所定温度T0での長時間保持で析出物を埋込みシリ
コン酸化層に十分に取り込み、シリコンと埋込みシリコ
ン酸化層との界面を平坦にする。最終所定温度が135
0℃未満では析出物の十分な取り込みが行われない。最
初の昇温速度v1が3℃/分未満では析出物が安定なも
のとなりやすく、また10℃/分を越えるとシリコン基
板自体にスリップと呼ばれる結晶欠陥などが入りやすく
なるからである。第1所定温度T1が上記範囲外では、
その後のアニール処理によっても酸素析出物が残存しや
すい。また最終の昇温速度v2が0.1℃/分未満では
アニール処理時間が長くなり過ぎ、また7℃/分を越え
ると取り込むはずの析出物が完全に溶解してしまい、そ
の後の長時間保持のアニール処理によってもピンホール
は埋まりにくくなるからである。 【0010】 【発明の実施の形態】本発明の酸素イオンの注入(dos
e)は低ドーズである。この場合の酸素イオン注入量は
3.0〜5.0×1017/cm2である。また減速して
いく昇温速度の段階は少なくとも2段階であって、3段
階でも4段階でもよい。本発明の最終所定温度T0での
保持時間tは少なくとも1時間であることが好ましい。
この最少の1時間は析出物を埋込みシリコン酸化層に取
り込むために必要だからである。保持時間tは最終所定
温度T0に依存し、高温となるほど短時間で済む。好ま
しくは1〜6時間である。 【0011】 【実施例】次に、本発明の実施例を比較例とともに図面
に基づいて詳しく説明する。 <実施例1>厚さ625μmのシリコン基板の所定の領
域(例えば、基板表面から約0.4μmの領域)に次の
条件で酸素イオン(O+)を注入した。 加速電圧: 180 KeV ビーム電流: 40〜50 mA ドーズ量: 4×1017/cm2 基板加熱温度:600℃ イオン注入後に、シリコン基板をアルゴンと酸素の混合
ガス雰囲気中で800℃に保持された熱処理炉に入れ、
最初に昇温速度5℃/分で1300℃まで昇温した。こ
の1300℃の時点における基板断面の電子顕微鏡写真
を図3に示す。次いで昇温速度を1℃/分に変え139
0℃まで昇温した。この昇温過程の基板断面の電子顕微
鏡写真を図4及び図5に示す。また1390℃での写真
を図6に示す。更に基板を1390℃で2時間保持して
アニール処理した。このアニール処理後の写真を図7に
示す。実施例1のアニール処理の温度プロファイルを図
1に示す。 【0012】<実施例2>実施例1と同一のシリコン基
板を同一条件で酸素イオン注入した後、基板を実施例1
と同一の酸素を含むArガス雰囲気で800℃に保持さ
れた熱処理炉に入れ、最初に昇温速度5℃/分で130
0℃まで昇温した。次いで昇温速度を0.5℃/分に変
え1390℃まで昇温し、1390℃で2時間保持して
アニール処理した。このアニール処理後の写真を図8に
示す。実施例2のアニール処理の温度プロファイルを図
1に示す。 【0013】<比較例1>実施例1と同一のシリコン基
板を同一条件で酸素イオン注入した後、基板を実施例1
と同一の酸素を含むArガス雰囲気で800℃に保持さ
れた熱処理炉に入れ、昇温速度5℃/分で1390℃ま
で昇温した。この1390℃の時点における基板断面の
電子顕微鏡写真を図9に示す。次いでこの1390℃で
4時間保持してアニール処理した。このアニール処理後
の写真を図10に示す。比較例1のアニール処理の温度
プロファイルを図1に示す。 【0014】<比較例2>実施例1と同一のシリコン基
板を同一条件で酸素イオン注入した後、基板を実施例1
と同一の酸素を含むArガス雰囲気で800℃に保持さ
れた熱処理炉に入れ、昇温速度5℃/分で1100℃ま
で昇温した。次いで昇温速度を1℃/分に変え1390
℃まで昇温した。1390℃に到達した時点での写真を
図11に示す。比較例2のアニール処理の温度プロファ
イルを図1に示す。 【0015】<比較観察> (a) ピンホール密度の測定 一方、実施例1,2及び比較例1,2の各SOI基板の
埋込みシリコン酸化層中のピンホール密度を測定した。
ピンホール密度はSOI基板の両面を電極で挟んで硫酸
銅溶液に浸漬し、通電した時の硫酸銅の析出量により求
めた。その結果を表1に示す。 【0016】 【表1】 【0017】上記(a)のピンホール密度の測定結果と写
真観察から次の点が明らかになった。比較例1の図9に
示すように、1390℃の時点では埋込みシリコン酸化
層の上に析出物が多数存在しており、ピンホールも観察
される。これは昇温速度が早いために、昇温速度にオス
トワルド成長(小さな析出物の溶解)が追いついていけ
なかったためである。析出物が完全に取り込まれていな
い分だけピンホールも存在している。図10に示すよう
に、この後の高温保持で写真に見られる小さな析出物を
取り込むが、初めにピンホールが多い分だけ完全にはピ
ンホールは埋まらない。比較例2では、図11に示すよ
うにSOI基板中に埋込みシリコン酸化層以外に析出物
が存在する。これは昇温速度が遅すぎるために、110
0℃での析出物が安定なものとして存在してしまったた
めである。析出物が完全に取り込まれていない分だけピ
ンホール密度も大きい。 【0018】これらに対して、実施例1の図3、図4、
図5、図6及び図7には、1300℃から1390℃ま
での埋込みシリコン酸化層が形成される過程が示され
る。1300℃から1℃/分という昇温は、図3の13
00℃の時点に見られる析出物が十分に取り込みながら
オストワルド成長できる条件であるため、比較例1と出
発点が同じ析出状態であっても、最終所定温度に到達し
たときには埋込みシリコン酸化層以外には析出物は存在
しない。析出物が完全に埋込みシリコン酸化層に取り込
まれているため、ピンホール密度は低い。また実施例2
では、図8に示すように実施例1と同様に1300℃で
の析出物を十分に取り込むことができる昇温速度である
ために、基板中に埋込みシリコン酸化層以外は析出物は
見られず、ピンホール密度も実施例1と同じ理由で低
い。 【0019】(b) Si層と埋込みシリコン酸化層との界
面の平坦度の測定 実施例1、2及び比較例1,2の各SOI基板表面の活
性なSi層と埋込みシリコン酸化層との界面の表面粗さ
を原子間力顕微鏡(atomic force microscope;AFM)
を用いて測定した。この測定はSOI基板をKOH液で
選択エッチングして単結晶シリコン層(Si層)を除去
することにより埋込みシリコン酸化層との界面を露出し
て行った。その結果を表2に示す。表2において、Ra
は平均粗さ、Rmsは2乗平均粗さ、Rmaxは最大高さを
意味する。 【0020】 【表2】 【0021】表2から明らかなように、高温で2時間保
持した実施例1及び2は、析出物を完全に取り込んでか
ら高温保持を行っているために4時間保持した比較例1
と比べて界面が短時間で平坦になっていることが判っ
た。一方、比較例1は高温保持中に析出物の取り込みを
行っているために、界面が平坦になるのに時間がかか
り、比較例2は高温保持を行っていないため、界面は極
めて粗いことが判明した。【0022】 【発明の効果】以上述べたように、本発明のSOI基板
の製造方法によれば、昇温速度を少なくとも2段階にし
て、最終所定温度に達するまで昇温速度を順次減速し、
最初の昇温速度(v 1 )が10〜3℃/分であって、この昇
温速度(v 1 )で1250℃以上1350℃未満の範囲内の
第1所定温度(T 1 )まで昇温し、最終の昇温速度(v 2 )が7
〜0.1℃/分であって、この昇温速度(v 2 )で1350
℃以上シリコン融点温度未満の最終所定温度(T 0 )まで昇
温することにより、ピンホール密度が極めて小さい高品
質の埋込みシリコン酸化層を形成することができ、また
Si層と埋込みシリコン酸化層との界面の平坦度を短時
間で良好にすることができる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an SOI (Silicon-On-Insulator) substrate having a Si layer formed on an insulating layer. See SIMOX (Separation by
(Implanted Oxygen) technology. 2. Description of the Related Art An SOI substrate is receiving attention as a future ULSI substrate. The SOI substrate manufacturing method includes a bonding method in which silicon substrates are bonded to each other via an insulating film, a method in which a silicon thin film is deposited on an insulating substrate or a substrate having an insulating thin film on its surface, and a SIMOX method. is there. The SIMOX method is one of the methods of embedding an insulating layer inside a silicon substrate. Specifically, after implanting high-concentration oxygen ions into the silicon substrate, the silicon substrate is annealed at a high temperature to perform annealing. In this method, a buried silicon oxide layer is formed in a region at a predetermined depth from the surface, and the Si layer on the surface side is used as an active region. The SIMOX method is a powerful method in which an active Si layer having a uniform thickness can be obtained without grinding and polishing the surface Si layer as in the above bonding method. In recent years, the amount of oxygen ions implanted has been reduced,
A low-dose technology for shortening the processing time of the ion implantation apparatus and reducing the manufacturing cost of the SOI substrate has begun to be put into practical use. In this low dose technology, for example, the acceleration energy 180
After oxygen ions are implanted at a keV of 4 × 10 17 / cm 2 , a heat treatment is performed at 1350 ° C. This low dose SI
In order to make the buried silicon oxide layer in the SOI substrate continuous by the MOX method and not to form an unoxidized island-like Si region (Si island) in this oxide layer, strict control of the oxygen ion implantation amount is required. Is extremely important. However, even if oxygen ions are implanted under conditions sufficiently controlled by the conventional low-dose SIMOX method, the pinhole density of the buried silicon oxide layer becomes 30%.
/ Cm 2 or more (M. Imai et
al., "The Status and Future of Low-Dose SIMOX Tech
nology ", Extended Abstracts of the 1995 International
al Conference on Solid State Devices and Material
s, Osaka, 1995, pp.557-559). If the pinhole density is large, the separation between devices cannot be performed sufficiently. In order to reduce the pinhole density, Japanese Patent Application Laid-Open No. 7-26
No. 3538 discloses an ITOX (Internal Thermal
Oxidation) technology has been proposed. This technology is SIM
Immediately after annealing in the OX method, annealing is further performed in a high-temperature oxygen atmosphere. This is a technique for increasing the thickness of the buried silicon oxide layer and filling any pinholes if any. However, it has been reported that even with this ITOX technique, a pinhole density of about 5 / cm 2 exists (M. Imai et al., Supra). An object of the present invention is to provide a method of manufacturing an SOI substrate in which a high-quality buried silicon oxide layer having a very low pinhole density is formed in a region at a predetermined depth from the substrate surface. Another object of the present invention is to provide a method of manufacturing an SOI substrate that improves the flatness of the interface between a Si layer and a buried silicon oxide layer. [0006] According to an aspect of the invention according to claim 1,
As shown in FIGS. 1 and 2, after implanting oxygen ions in the silicon substrate 11, to a final predetermined temperature T 0 was heated by performing the annealing treatment for holding the final predetermined temperature T 0 predetermined time t In a method for manufacturing an SOI substrate in which a buried silicon oxide layer 12 is formed in a region at a predetermined depth from the surface of a silicon substrate 11 and an active Si layer 11a is formed on the surface of the substrate 11, at least a temperature increase rate during an annealing process is In the two stages v 1 and v 2 , the final predetermined temperature T 0
Until the temperature rises , the initial heating rate (v
1 ) is 10 to 3 ° C./min, and the heating rate (v 1 ) is 12
First predetermined temperature (T 1 ) within the range of 50 ° C. or more and less than 1350 ° C.
And the final heating rate (v 2 ) is 7-0.1 ° C / min.
At this heating rate (v 2 ), silicon
A method for manufacturing an SOI substrate, comprising raising a temperature to a final predetermined temperature (T 0 ) lower than a point temperature . The buried silicon oxide layer has an Ostwald growth in which small silicon oxide precipitates dissolve as temperature increases and are absorbed by larger precipitates.
d ripening). According to the low-dose SIMOX method, the deposition of silicon oxide on a silicon substrate
In the early stage of the annealing process, silicon and oxygen react with each other in accordance with the oxygen concentration distribution to form a precipitate of silicon oxide, and when Ostwald groWth proceeds to some extent, damage caused by oxygen implantation in the depth direction of the substrate as shoWn in FIG. It occurs mainly at two points, a peak position A and an oxygen injection peak position B. Then, as the temperature rises, the precipitate at the damage peak position A is taken into the precipitate at the oxygen injection peak position B, and finally becomes one silicon oxide layer. A damage distribution diagram and an oxygen concentration distribution diagram are shown on the right side of the substrate 11 in FIG.
In the conventional annealing process, the temperature is increased at a single heating rate, and when the temperature reaches a predetermined temperature, the temperature is maintained for a predetermined time. When the temperature rise rate is relatively high, for example, at 5 ° C./min or more, when the temperature reaches a predetermined temperature, for example, 1300 ° C. or more, Ostwald growth cannot keep up with this temperature rise rate, and deposition occurs in addition to the buried silicon oxide layer. The object remains, and pinholes are present as much as the silicon oxide is not completely taken in. The precipitate is incorporated into the buried silicon oxide layer by a subsequent long-time annealing treatment. The precipitates merge with the buried silicon oxide layer through defects caused by interstitial silicon released with the oxidation of silicon. Therefore, unless a sufficient defect is formed on the pinhole, the pinhole will not be filled. On the other hand, when the heating rate is relatively slow, for example, 1 ° C./min or less, the formed precipitate becomes stable during Ostwald ripening,
Even if the annealing treatment is performed for a long period of time, it cannot be dissolved, resulting in a problem that a precipitate finally exists other than the buried silicon oxide layer. According to the present invention, the initial heating rate v 1 is set to 10
33 ° C./min, and the decelerated final heating rate v 2 is 7〜
0.1 ° C / min. 1250 ° C at the first heating rate v1
The temperature is raised to a first predetermined temperature T 1 within the range of less than 1350 ° C., and the temperature is raised to a final predetermined temperature T 0 of 1350 ° C. or more and lower than the silicon melting point at a final temperature raising rate v 2 . afterwards,
The precipitates are sufficiently taken into the buried silicon oxide layer by keeping at the final predetermined temperature T 0 for a long time, and the interface between silicon and the buried silicon oxide layer is flattened. Final predetermined temperature is 135
If the temperature is lower than 0 ° C., sufficient incorporation of the precipitate is not performed. If the initial heating rate v 1 is less than 3 ° C./min, the precipitate tends to be stable, and if it exceeds 10 ° C./min, crystal defects called slip tend to occur in the silicon substrate itself. When the first predetermined temperature T 1 is outside the above range,
Oxygen precipitates are likely to remain even after subsequent annealing. If the final heating rate v 2 is less than 0.1 ° C./min, the annealing treatment time becomes too long. If the final heating rate v 2 exceeds 7 ° C./min, precipitates to be taken in are completely dissolved, and the This is because the pinholes are less likely to be filled by the annealing treatment for holding. DETAILED DESCRIPTION OF THE INVENTION The oxygen ion implantation (dos
e) has a low dose. The oxygen ion implantation amount in this case is 3.0 to 5.0 × 10 17 / cm 2 . In addition, there are at least two stages of the temperature increasing speed at which the temperature is decelerated, and three or four stages may be used. In the present invention, the holding time t at the final predetermined temperature T 0 is preferably at least one hour.
This is because the minimum one hour is necessary for incorporating the precipitate into the buried silicon oxide layer. The holding time t depends on the final predetermined temperature T 0 , and the higher the temperature, the shorter the time. Preferably, it is 1 to 6 hours. Next, embodiments of the present invention will be described in detail with reference to the drawings together with comparative examples. <Example 1> Oxygen ions (O + ) were implanted into a predetermined region (for example, a region approximately 0.4 μm from the substrate surface) of a silicon substrate having a thickness of 625 μm under the following conditions. Acceleration voltage: 180 KeV Beam current: 40-50 mA Dose amount: 4 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. After ion implantation, the silicon substrate was kept at 800 ° C. in a mixed gas atmosphere of argon and oxygen. Put in the heat treatment furnace,
First, the temperature was raised to 1300 ° C. at a rate of 5 ° C./min. FIG. 3 shows an electron micrograph of the cross section of the substrate at 1300 ° C. Then, the heating rate was changed to 1 ° C./min and 139
The temperature was raised to 0 ° C. FIGS. 4 and 5 show electron micrographs of the cross section of the substrate during the heating process. FIG. 6 shows a photograph at 1390 ° C. Further, the substrate was annealed while being held at 1390 ° C. for 2 hours. FIG. 7 shows a photograph after the annealing. FIG. 1 shows a temperature profile of the annealing process of the first embodiment. <Example 2> After the same silicon substrate as in Example 1 was implanted with oxygen ions under the same conditions, the substrate was replaced with Example 1.
And placed in a heat treatment furnace maintained at 800 ° C. in an Ar gas atmosphere containing the same oxygen as above, and first heated at a rate of 5 ° C./min.
The temperature was raised to 0 ° C. Next, the temperature was raised to 1390 ° C. at a rate of 0.5 ° C./min, and the sample was annealed at 1390 ° C. for 2 hours. FIG. 8 shows a photograph after the annealing. FIG. 1 shows a temperature profile of the annealing process in the second embodiment. Comparative Example 1 After the same silicon substrate as in Example 1 was implanted with oxygen ions under the same conditions, the substrate was replaced with Example 1.
Then, it was placed in a heat treatment furnace maintained at 800 ° C. in an Ar gas atmosphere containing the same oxygen and heated to 1390 ° C. at a rate of 5 ° C./min. FIG. 9 shows an electron micrograph of the cross section of the substrate at 1390 ° C. Next, annealing was carried out at 1390 ° C. for 4 hours. FIG. 10 shows a photograph after the annealing. FIG. 1 shows a temperature profile of the annealing process of Comparative Example 1. Comparative Example 2 The same silicon substrate as in Example 1 was implanted with oxygen ions under the same conditions.
Then, the sample was placed in a heat treatment furnace maintained at 800 ° C. in an Ar gas atmosphere containing the same oxygen as above, and the temperature was raised to 1100 ° C. at a rate of 5 ° C./min. Then, the heating rate was changed to 1 ° C./min and 1390
The temperature was raised to ° C. FIG. 11 shows a photograph when the temperature reached 1390 ° C. FIG. 1 shows the temperature profile of the annealing process of Comparative Example 2. <Comparison Observation> (a) Measurement of Pinhole Density Meanwhile, the pinhole density in the buried silicon oxide layer of each of the SOI substrates of Examples 1 and 2 and Comparative Examples 1 and 2 was measured.
The pinhole density was determined by immersing the SOI substrate between the electrodes on both sides of the electrode in a copper sulfate solution and depositing copper sulfate when energized. Table 1 shows the results. [Table 1] The following points became clear from the pinhole density measurement result (a) and the photograph observation. As shown in FIG. 9 of Comparative Example 1, at 1390 ° C., many precipitates exist on the buried silicon oxide layer, and pinholes are also observed. This is because Ostwald growth (dissolution of small precipitates) could not keep up with the heating rate because the heating rate was high. Pinholes also exist to the extent that the precipitate is not completely taken in. As shown in FIG. 10, the small precipitates seen in the photograph are taken in after the high temperature holding, but the pinholes are not completely filled at first due to the large number of pinholes. In Comparative Example 2, as shown in FIG. 11, a precipitate exists in the SOI substrate other than the buried silicon oxide layer. This is because the heating rate is too slow,
This is because the precipitate at 0 ° C. was present as stable. The pinhole density is large because the precipitate is not completely taken in. On the other hand, FIGS.
FIGS. 5, 6 and 7 show a process of forming a buried silicon oxide layer at 1300 ° C. to 1390 ° C. The temperature rise from 1300 ° C. to 1 ° C./min corresponds to 13 in FIG.
Since the conditions at which the precipitates observed at the time of 00 ° C. allow the Ostwald crystallization to grow sufficiently while taking in are sufficient, even when the starting point is the same as that in Comparative Example 1, when the final predetermined temperature is reached, other than the buried silicon oxide layer, Has no precipitate. The pinhole density is low because the precipitate is completely incorporated into the buried silicon oxide layer. Example 2
As shown in FIG. 8, as in Example 1, since the temperature was raised so that the precipitate at 1300 ° C. could be sufficiently taken in, no precipitate was observed except for the buried silicon oxide layer in the substrate. The pinhole density is also low for the same reason as in the first embodiment. (B) Measurement of the flatness of the interface between the Si layer and the buried silicon oxide layer The interface between the active Si layer on the surface of each SOI substrate and the buried silicon oxide layer in Examples 1 and 2 and Comparative Examples 1 and 2 Atomic force microscope (AFM)
It measured using. This measurement was performed by exposing the interface with the buried silicon oxide layer by selectively etching the SOI substrate with a KOH solution to remove the single crystal silicon layer (Si layer). Table 2 shows the results. In Table 2, Ra
Is the average roughness, Rms is the root-mean-square roughness, and Rmax is the maximum height. [Table 2] As apparent from Table 2, Examples 1 and 2 in which the precipitates were kept at a high temperature for 2 hours corresponded to Comparative Examples 1 and 4 in which the precipitates were completely taken in and kept at a high temperature for 4 hours.
It was found that the interface became flat in a short time as compared with. On the other hand, in Comparative Example 1, since the precipitates were taken in during the high-temperature holding, it took time for the interface to become flat, and in Comparative Example 2, the interface was extremely rough because the high-temperature holding was not performed. found. As described above, according to the SOI substrate manufacturing method of the present invention, the heating rate is set to at least two steps, and the heating rate is sequentially reduced until reaching the final predetermined temperature .
The initial heating rate (v 1 ) is 10 to 3 ° C./min.
At a temperature rate (v 1 ) of 1250 ° C or more and less than 1350 ° C
The temperature is raised to the first predetermined temperature (T 1 ), and the final heating rate (v 2 ) is 7
0.10.1 ° C./min , and 1350 at this heating rate (v 2 ).
The temperature rises to the final specified temperature (T 0 ) that is higher than or equal to
By heating, a high-quality buried silicon oxide layer having an extremely low pinhole density can be formed, and the flatness of the interface between the Si layer and the buried silicon oxide layer can be improved in a short time.

【図面の簡単な説明】 【図1】酸素イオン注入後における実施例と比較例のア
ニール処理の温度プロファイルを示す図。 【図2】本発明の酸素イオン注入直後のシリコン基板の
部分断面を示す模式図。 【図3】昇温速度5℃/分で1300℃まで昇温したと
きの実施例1のシリコン基板断面の電子顕微鏡写真図。 【図4】1300℃から昇温速度1℃/分で昇温する過
程の実施例1のシリコン基板断面の電子顕微鏡写真図。 【図5】昇温速度1℃/分で更に昇温したときの実施例
1のシリコン基板断面の電子顕微鏡写真図。 【図6】昇温速度1℃/分で1390℃まで昇温したと
きの実施例1のシリコン基板断面の電子顕微鏡写真図。 【図7】アニール処理後の実施例1のシリコン基板断面
の電子顕微鏡写真図。 【図8】アニール処理後の実施例2のシリコン基板断面
の電子顕微鏡写真図。 【図9】昇温速度5℃/分で1390℃まで昇温したと
きの比較例1のシリコン基板断面の電子顕微鏡写真図。 【図10】アニール処理後の比較例1のシリコン基板断
面の電子顕微鏡写真図。 【図11】昇温速度5℃/分で1100℃まで昇温し、
昇温速度を1℃/分に変え1390℃まで昇温した時点
での比較例2のシリコン基板断面の電子顕微鏡写真図。 【符号の説明】 11 シリコン基板 11a 基板表面のSi層 12 埋込みシリコン酸化層
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a temperature profile of an annealing process of an example and a comparative example after oxygen ion implantation. FIG. 2 is a schematic view showing a partial cross section of a silicon substrate immediately after oxygen ion implantation according to the present invention. FIG. 3 is an electron micrograph of a cross section of the silicon substrate of Example 1 when the temperature is increased to 1300 ° C. at a rate of 5 ° C./min. FIG. 4 is an electron micrograph of a cross section of the silicon substrate of Example 1 in the process of heating from 1300 ° C. at a heating rate of 1 ° C./min. FIG. 5 is an electron micrograph of the cross section of the silicon substrate of Example 1 when the temperature was further increased at a rate of 1 ° C./min. FIG. 6 is an electron micrograph of the cross section of the silicon substrate of Example 1 when the temperature was increased to 1390 ° C. at a rate of 1 ° C./min. FIG. 7 is an electron micrograph of a cross section of the silicon substrate of Example 1 after annealing. FIG. 8 is an electron micrograph of a cross section of the silicon substrate of Example 2 after annealing. FIG. 9 is an electron micrograph of a cross section of the silicon substrate of Comparative Example 1 when the temperature was raised to 1390 ° C. at a rate of 5 ° C./min. FIG. 10 is an electron micrograph of a cross section of the silicon substrate of Comparative Example 1 after annealing. FIG. 11 is a diagram showing a temperature rise to 1100 ° C. at a rate of 5 ° C./min.
The electron microscope photograph figure of the cross section of the silicon substrate of the comparative example 2 at the time of changing the temperature rising rate to 1 ° C./min and increasing the temperature to 1390 ° C. [Description of Signs] 11 Silicon substrate 11a Si layer on substrate surface 12 Embedded silicon oxide layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−144761(JP,A) 特開 昭62−188239(JP,A) J.Stoemenos,et.a l.,”Dislocation fo rmation related wi th high oxygen dos e inplantation on silicon”,J.Appl.Ph ys.,1991年 1月15日,Vol. 69,No.2,pp.793−802 H.Yang,et.al.,”Ef fect of Implantati on Current dendity and anneal time o n the microstructu re of SIMOX”,Nucle ar Instuments and Methods in Physics Research B,1991年,Vo l.56/57,pp.668−671 (58)調査した分野(Int.Cl.7,DB名) H01L 27/12 H01L 21/26 - 21/268 H01L 21/322 - 21/326 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-144761 (JP, A) JP-A-62-188239 (JP, A) Stoemenos, et. a l. , "Dislocation Formatted Related with High Oxygen Dose Implantation on Silicon", J. Am. Appl. Phys. Vol. 69, No. 15, January 15, 1991. 2, pp. 793-802H. Yang, et. al. , "Effect of Implantation on Current Density and Annual Time of the Microstructure of SIMOX", Nuclear Instruments and Methods of Medicine, 1991, Nuclear Resources and Methods of Medicine. 56/57, p. 668−671 (58) Field surveyed (Int.Cl. 7 , DB name) H01L 27/12 H01L 21/26-21/268 H01L 21/322-21/326

Claims (1)

(57)【特許請求の範囲】 【請求項1】 シリコン基板(11)内部に酸素イオンを注
入した後、最終所定温度(T0)まで昇温して前記最終所定
温度(T0)を所定時間(t)保持するアニール処理を行うこ
とにより前記シリコン基板(11)表面から所定の深さの領
域に埋込みシリコン酸化層(12)を形成し、前記基板(11)
表面に活性なSi層(11a)を形成するSOI基板の製造
方法において、 前記アニール処理時の昇温速度が少なくとも2段階(v1,
v2)であって、前記最終所定温度(T0)に達するまで昇温
速度を順次減速し、 最初の昇温速度(v 1 )が10〜3℃/分であって、この昇
温速度(v 1 )で1250℃以上1350℃未満の範囲内の
第1所定温度(T 1 )まで昇温し、最終の昇温速度(v 2 )が7
〜0.1℃/分であって、この昇温速度(v 2 )で1350
℃以上シリコン融点温度未満の最終所定温度(T 0 )まで昇
温する ことを特徴とするSOI基板の製造方法。
(57) After the Claims to 1. A silicon substrate (11) inside the oxygen ion was implanted, a predetermined temperature increase to the final predetermined temperature (T 0) to a final predetermined temperature (T 0) A buried silicon oxide layer (12) is formed in a region at a predetermined depth from the surface of the silicon substrate (11) by performing an annealing process for holding time (t), and the substrate (11)
In the method for manufacturing an SOI substrate in which an active Si layer (11a) is formed on the surface, the rate of temperature increase during the annealing treatment is at least two steps (v 1 ,
v 2) is a, said final predetermined temperature (T 0) sequentially decelerated heating rate to reach, a first heating rate (v 1) is ten to three ° C. / min, the temperature
At a temperature rate (v 1 ) of 1250 ° C or more and less than 1350 ° C
The temperature is raised to the first predetermined temperature (T 1 ), and the final heating rate (v 2 ) is 7
0.10.1 ° C./min , and 1350 at this heating rate (v 2 ).
The temperature rises to the final specified temperature (T 0 ) that is higher than or equal to ° C and lower than the silicon melting point temperature.
Heating the SOI substrate.
JP06573196A 1996-03-22 1996-03-22 Method for manufacturing SOI substrate Expired - Fee Related JP3480479B2 (en)

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Publication number Priority date Publication date Assignee Title
JP3211233B2 (en) * 1998-08-31 2001-09-25 日本電気株式会社 SOI substrate and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
H.Yang,et.al.,"Effect of Implantation Current dendity and anneal time on the microstructure of SIMOX",Nuclear Instuments and Methods in Physics Research B,1991年,Vol.56/57,pp.668−671
J.Stoemenos,et.al.,"Dislocation formation related with high oxygen dose inplantation on silicon",J.Appl.Phys.,1991年 1月15日,Vol.69,No.2,pp.793−802

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