JP3097827B2 - Method for manufacturing SOI substrate - Google Patents

Method for manufacturing SOI substrate

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Publication number
JP3097827B2
JP3097827B2 JP08062534A JP6253496A JP3097827B2 JP 3097827 B2 JP3097827 B2 JP 3097827B2 JP 08062534 A JP08062534 A JP 08062534A JP 6253496 A JP6253496 A JP 6253496A JP 3097827 B2 JP3097827 B2 JP 3097827B2
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JP
Japan
Prior art keywords
substrate
region
ions
silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08062534A
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Japanese (ja)
Other versions
JPH08321594A (en
Inventor
哲弥 中井
隆之 新行内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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Priority to JP08062534A priority Critical patent/JP3097827B2/en
Publication of JPH08321594A publication Critical patent/JPH08321594A/en
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/30Hydrogen technology
    • Y02E60/32Hydrogen storage

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  • Element Separation (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は絶縁層上にシリコン層を
形成するSOI(Silicon-On-Insulator)基板の製造方
法に関する。更に詳しくはSIMOX(Separation by
Implanted Oxygen)技術によるSOI基板の製造方法に
関するものである。
The present invention relates to a method for manufacturing an SOI (Silicon-On-Insulator) substrate in which a silicon layer is formed on an insulating layer. See SIMOX (Separation by
(Implanted Oxygen) technology.

【0002】[0002]

【従来の技術】SOI基板は将来の超高集積回路(UL
SI)基板として注目されてきている。このSOI基板
の製造方法には、シリコン基板同士を絶縁膜を介して貼
り合わせる方法、絶縁性基板又は絶縁性薄膜を表面に有
する基板の上にシリコン薄膜を堆積させる方法、SIM
OX法などがある。このSIMOX法は、シリコン基板
の内部に絶縁層を埋込む法の1つであって、具体的には
シリコン基板内部に高濃度の酸素イオンを注入した後、
高温でアニール処理してこのシリコン基板表面から所定
の深さの領域に埋込みシリコン酸化層を形成し、その表
面側のSi層を活性領域とする方法である。このSIM
OX法ではシリコン基板内部に酸素を一度に過剰にイオ
ン注入することにより、格子位置のシリコン原子を放出
して格子間シリコン原子にするとともに格子位置に空孔
を形成する。引き続いて、高温アニール処理してシリコ
ン基板を体積膨張させることにより、注入した酸素イオ
ンと格子間シリコン原子を再配列させてイオン注入損傷
領域に極めて短時間のうちにシリコン酸化層を析出させ
ている。
2. Description of the Related Art SOI substrates are used in future ultra-high integrated circuits (UL).
SI) It has attracted attention as a substrate. The method of manufacturing the SOI substrate includes a method of bonding silicon substrates together via an insulating film, a method of depositing a silicon thin film on an insulating substrate or a substrate having an insulating thin film on its surface,
OX method and the like. The SIMOX method is one of the methods of embedding an insulating layer inside a silicon substrate. Specifically, after implanting high-concentration oxygen ions into the silicon substrate,
In this method, a buried silicon oxide layer is formed at a predetermined depth from the surface of the silicon substrate by annealing at a high temperature, and the Si layer on the surface side is used as an active region. This SIM
In the OX method, oxygen is excessively ion-implanted into a silicon substrate at a time to release silicon atoms at lattice positions to form interstitial silicon atoms and form vacancies at lattice positions. Subsequently, high-temperature annealing is performed to expand the volume of the silicon substrate, thereby rearranging the implanted oxygen ions and interstitial silicon atoms, thereby depositing a silicon oxide layer in the ion implantation damaged region in a very short time. .

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来のS
IMOX法では過剰な格子間シリコン原子により微小欠
陥を生じ、この微小欠陥は高温アニール処理による再配
列時に基板表面近傍で成長して転位欠陥を形成し易い不
具合があった。また上記方法ではイオン注入する酸素の
原子量が比較的大きく、このために高い加速電圧を要す
ることから、注入した基板表面からの深さ方向に酸素濃
度が広く分布し易く、しかも基板表面が粗くなり、埋込
みシリコン酸化層の境界が急峻でない傾向があった。特
に埋込みシリコン酸化層を基板表面から深く形成しよう
とするとその傾向が顕著であった。換言すれば、酸素イ
オン注入の場合には、SOI基板の表面粗さが大きく、
しかもイオン注入損傷領域が広くなり易く、その分だけ
アニール処理で所定の深さ領域に境界が急峻な埋込みシ
リコン酸化層を形成することが困難であった。更に上記
方法では酸素イオン注入の際に、イオン注入装置からF
e,Ni,Cu,Zn,Crなどの重金属が不純物とし
てシリコン基板の表面近傍に高い濃度で侵入し易い。こ
れらの重金属が基板表面の活性領域のSi層に存在する
とデバイスとなったときの電気特性に大きな影響を及ぼ
す問題点があった。
However, the conventional S
In the IMOX method, a minute defect is generated by excessive interstitial silicon atoms, and the minute defect grows near the substrate surface during rearrangement by high-temperature annealing, and has a problem that a dislocation defect is easily formed. Further, in the above method, the atomic weight of oxygen to be ion-implanted is relatively large, which requires a high accelerating voltage. Therefore, the oxygen concentration is easily distributed widely in the depth direction from the surface of the implanted substrate, and the surface of the substrate becomes rough. However, the boundary between the buried silicon oxide layers tends not to be steep. In particular, when the buried silicon oxide layer is to be formed deep from the substrate surface, the tendency is remarkable. In other words, in the case of oxygen ion implantation, the surface roughness of the SOI substrate is large,
In addition, the ion implantation damage region is likely to be widened, and it is difficult to form a buried silicon oxide layer having a steep boundary in a predetermined depth region by annealing. Further, in the above method, when oxygen ions are implanted, F
Heavy metals such as e, Ni, Cu, Zn, and Cr easily enter the vicinity of the surface of the silicon substrate as impurities at a high concentration. When these heavy metals exist in the Si layer in the active region on the substrate surface, there is a problem that the electrical characteristics of the device are greatly affected.

【0004】本発明の目的は、基板表面の活性領域のS
i層に転位欠陥を形成しにくいSOI基板の製造方法を
提供することにある。本発明の別の目的は、比較的低い
加速電圧により、基板表面粗さを小さくして、かつ所定
の深さ領域に境界が急峻で層厚の小さな埋込みシリコン
酸化層を形成し得るSOI基板の製造方法を提供するこ
とにある。本発明の更に別の目的は、基板中の重金属を
低減し得るSOI基板の製造方法を提供することにあ
る。
[0004] It is an object of the present invention to provide a semiconductor device having an active region on a substrate surface.
An object of the present invention is to provide a method for manufacturing an SOI substrate in which dislocation defects are hardly formed in an i-layer. Another object of the present invention is to provide an SOI substrate capable of forming a buried silicon oxide layer having a steep boundary and a small thickness in a predetermined depth region with a relatively low acceleration voltage to reduce the substrate surface roughness. It is to provide a manufacturing method. Still another object of the present invention is to provide a method for manufacturing an SOI substrate capable of reducing heavy metals in the substrate.

【0005】[0005]

【0006】[0006]

【0007】[0007]

【0008】[0008]

【課題を解決するための手段】請求項に係る発明は、
(a)〜図(e)に示すように、シリコン基板2
1に真空中で少なくともHeイオンHイオン、Arイ
オン又はSiイオンを注入することによりシリコン基板
21内部にイオン注入損傷領域22を形成する工程と、
イオン注入損傷領域22が形成されたシリコン基板21
を800〜1400℃の温度でアニール処理してイオン
注入損傷領域22に注入されたHe原子H原子、Ar
原子又はSi原子をこの領域22より放出して空孔領域
23を形成する工程と、シリコン基板21内部に酸素イ
オンを注入して空孔領域23を中心にSiOx領域24
を形成する工程と、SiOx領域24が形成されたシリ
コン基板21を酸化性雰囲気中で1000℃〜1400
℃の温度でアニール処理してシリコン基板21表面から
所定の深さの領域に埋込みシリコン酸化層26を形成し
てシリコン基板表面に単結晶Si層21aを形成する工
程とを含むSOI基板20の製造方法である。この方法
によれば、基板外へのHe原子H原子、Ar原子又は
Si原子(図中、hを円で囲んで表す)の放出により生
じた空孔領域23に酸素原子(図中、●印で示す)がイ
オン注入により侵入してSiOxを形成するため埋込
みシリコン酸化層安定して形成することができる。
The invention according to claim 1 is
As shown in FIG. 1 (a) ~ FIG 1 (e), a silicon substrate 2
1. At least He ion , H ion , Ar ion in vacuum
Forming an ion implantation damaged region 22 inside the silicon substrate 21 by implanting ON or Si ions ;
Silicon substrate 21 with ion implantation damaged region 22 formed
The 800 to 1400 ° C. temperature annealing to He atoms injected into the ion implantation damage region 22 of, H atom, Ar
Forming a vacancy region 23 by releasing atoms or Si atoms from the region 22; and implanting oxygen ions into the silicon substrate 21 to form a SiOx region 24 around the vacancy region 23.
And forming the silicon substrate 21 on which the SiOx region 24 is formed in an oxidizing atmosphere at 1000 ° C. to 1400 ° C.
Forming an embedded silicon oxide layer 26 in a region at a predetermined depth from the surface of the silicon substrate 21 by annealing at a temperature of ° C. to form a single-crystal Si layer 21a on the surface of the silicon substrate. Is the way. According to this method, He atoms , H atoms , Ar atoms or
(In the figure, it represented circled the h) Si atom (in the figure, indicated by marks ●) air oxygen atom in the hole region 23 caused by release for to form a SiOx invade by ion implantation, a buried silicon it is possible to stably form an oxide layer.

【0009】請求項に係る発明は、請求項に係る発
明であって、アニール処理して埋込シリコン酸化層26
を形成した後にシリコン基板21表面を研磨する工程を
更に含むSOI基板の製造方法である。この方法によれ
ば、基板の表面粗さをより小さくすることができ、マイ
クロラフネスがより小さい単結晶Si層21aが得られ
る。請求項に係る発明は、請求項1又は2に係る発明
であって、注入するイオンがHeイオン又はHイオンで
あるとき、そのイオン注入時のドーズ量が1×1016
cm2〜5×1017/cm2で、加速電圧が40keV〜
200keVであるSOI基板の製造方法である。請求
に係る発明は、請求項1〜3いずれかに係る発明で
あって、埋込シリコン酸化層26を形成するためのアニ
ール処理が酸化性雰囲気中、10〜100気圧下で行わ
れるSOI基板の製造方法である。この方法によれば、
埋込みシリコン酸化層をより一層安定して形成すること
ができる。
The invention according to claim 2 is the invention according to claim 1 , wherein the buried silicon oxide layer 26 is formed by annealing.
This is a method for manufacturing an SOI substrate, further comprising a step of polishing the surface of the silicon substrate 21 after forming the substrate. According to this method, the surface roughness of the substrate can be further reduced, and a single-crystal Si layer 21a having a smaller micro roughness can be obtained. The invention according to claim 3 is the invention according to claim 1 or 2 , wherein when the ions to be implanted are He ions or H ions, the dose at the time of the ion implantation is 1 × 10 16 /.
cm 2 -5 × 10 17 / cm 2 , and the accelerating voltage is 40 keV
This is a method for manufacturing an SOI substrate at 200 keV. The invention according to claim 4 is the invention according to any one of claims 1 to 3 , wherein the annealing for forming the buried silicon oxide layer 26 is performed in an oxidizing atmosphere at 10 to 100 atm. This is a method for manufacturing a substrate. According to this method,
The buried silicon oxide layer can be formed more stably.

【0010】[0010]

【発明の実施の形態】本発明において、注入するイオン
がArイオン又はSiイオンの場合には、Ar又はSi
の原子量はHeと比べて大きいため、埋込みシリコン酸
化層の表面からの深さに応じてそのイオン注入時のドー
ズ量は1×1015/cm2〜1×1017/cm2であり、
このときの加速電圧は150keV〜200keVであ
る。本発明のイオン注入時の基板温度は500℃〜70
0℃が好ましく、600℃が更に好ましい。アニール処
理は、酸化性雰囲気中、1000℃〜1400℃の温度
範囲で1〜8時間行われる。この処理温度は1300℃
〜1400℃が好ましく、1350℃が更に好ましい。
またその時間は4〜8時間が好ましく、6時間程度が更
に好ましい。酸化性雰囲気としては、10〜100%濃
度の酸素雰囲気が挙げられ、100%濃度に近い高濃度
の酸素雰囲気が好ましい。またイオン注入損傷領域に注
入されたHe原子又はH原子をこの損傷領域より放出し
て空孔領域を形成するためのアニール処理の雰囲気は
0.5〜3%O2、残部不活性ガスの混合ガス雰囲気が
好ましい。酸素を僅かに含むのは、基板表面の荒れを防
ぐためである。シリコン基板の表面研磨はシリコンウェ
ーハ用研磨機、レンズ研磨機などにより軽く行われる。
この研磨では基板表面が厚さ50オングストローム〜5
00オングストローム、好ましくは100オングストロ
ーム程度の深さ磨滅させることが望ましい。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, when the ions to be implanted are Ar ions or Si ions, Ar or Si ions are used.
Has a greater atomic weight than He, and the dose at the time of ion implantation is 1 × 10 15 / cm 2 to 1 × 10 17 / cm 2 depending on the depth from the surface of the buried silicon oxide layer.
The acceleration voltage at this time is 150 keV to 200 keV. The substrate temperature during the ion implantation according to the present invention is 500 ° C. to 70 ° C.
0 ° C is preferred, and 600 ° C is more preferred. The annealing treatment is performed in an oxidizing atmosphere at a temperature in the range of 1000C to 1400C for 1 to 8 hours. The processing temperature is 1300 ° C
To 1400 ° C is preferable, and 1350 ° C is more preferable.
The time is preferably 4 to 8 hours, more preferably about 6 hours. Examples of the oxidizing atmosphere include an oxygen atmosphere having a concentration of 10 to 100%, and an oxygen atmosphere having a high concentration close to 100% is preferable. The atmosphere of the annealing treatment for releasing the He atoms or H atoms implanted into the ion-implanted damaged region from the damaged region to form a void region is 0.5 to 3% O 2 , and the remaining inert gas is mixed. A gas atmosphere is preferred. The reason for containing a small amount of oxygen is to prevent the substrate surface from being roughened. The surface of the silicon substrate is lightly polished by a silicon wafer polishing machine, a lens polishing machine or the like.
In this polishing, the substrate surface has a thickness of 50 Å to 5 Å.
It is desirable to wear down to a depth of about 100 Å, preferably about 100 Å.

【0011】特に注入イオンがHeイオン又はHイオン
の場合には、He,Hは原子量が小さいため、従来の酸
素イオン注入と比べて、基板の表面近傍のSi層の転位
欠陥が生じにくくなると同時に酸素イオンよりも低い加
速電圧で所定の深さにイオン注入損傷領域を形成するこ
とができる。この加速電圧が低いことに起因して、イオ
ン注入損傷領域に境界が急峻で層厚の小さな埋込みシリ
コン酸化層を形成し易くなり、結果としてSiO2の析
出制御が容易となる。またイオン注入時にSi層表面の
スパッタリングが減少し、基板の表面粗さが小さくな
る。同時に装置内壁のスパッタリングが大幅に低減さ
れ、基板への重金属の汚染が低減される。
In particular, when the implanted ions are He ions or H ions, since He and H have small atomic weights, dislocation defects in the Si layer near the surface of the substrate are less likely to occur as compared with conventional oxygen ion implantation, and An ion implantation damaged region can be formed at a predetermined depth with an acceleration voltage lower than that of oxygen ions. Due to the low accelerating voltage, a buried silicon oxide layer having a sharp boundary and a small layer thickness is easily formed in the ion implantation damaged region, and as a result, control of deposition of SiO 2 is facilitated. Also, sputtering on the surface of the Si layer during ion implantation is reduced, and the surface roughness of the substrate is reduced. At the same time, the sputtering of the inner wall of the apparatus is greatly reduced, and the contamination of the substrate with heavy metals is reduced.

【0012】[0012]

【実施例】次に、本発明の実施例を比較例とともに図面
に基づいて詳しく説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings together with comparative examples.

【0013】[0013]

【0014】[0014]

【0015】[0015]

【0016】[0016]

【0017】[0017]

【0018】[0018]

【0019】[0019]

【0020】<比較例1>厚さ625μmのシリコン基
板の所定の領域(例えば、基板表面から約0.4μmの
領域)に次の条件で酸素イオン(O+)を注入した。 加速電圧: 120 keV ドーズ量: 0.4×1018/cm2 基板加熱温度:600℃ シリコン基板11に酸素イオン注入した後、Ar97%
でO23%の混合ガス雰囲気中で1325℃、6時間シ
リコン基板をアニール処理してSOI基板を得た。
<Comparative Example 1> Oxygen ions (O + ) were implanted into a predetermined region (for example, a region approximately 0.4 μm from the substrate surface) of a 625 μm-thick silicon substrate under the following conditions. Accelerating voltage: 120 keV Dose amount: 0.4 × 10 18 / cm 2 Substrate heating temperature: 600 ° C. After oxygen ions are implanted into the silicon substrate 11, Ar 97%
The silicon substrate was annealed at 1325 ° C. for 6 hours in a mixed gas atmosphere of O 2 3% to obtain an SOI substrate.

【0021】<実施例> 図(a)及び(b)に示すように、厚さ625μmの
シリコン基板21の所定の領域に次の条件でHeイオン
(He+)を注入した。 加速電圧: 40 keV ドーズ量: 1×1017/cm2 基板加熱温度:600℃ このイオン注入によりシリコン基板21の表面から約
0.3μmのイオン注入損傷領域22が形成された。イ
オン注入後、図(c)及び(d)に示すようにシリコ
ン基板21をAr99%でO21%の混合ガス雰囲気中
で1325℃、2時間アニール処理を施して、イオン注
入損傷領域22に注入されたHe原子をこの損傷領域2
2より放出して空孔領域23を形成した。
[0021] <Example 1> As shown in FIG. 1 (a) and (b), was injected He ions (He +) under the following conditions in a predetermined region of the silicon substrate 21 with a thickness of 625 .mu.m. Acceleration voltage: 40 keV Dose: 1 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. By this ion implantation, an ion implantation damaged region 22 of about 0.3 μm was formed from the surface of the silicon substrate 21. After the ion implantation, FIG. 1 (c) and 1325 ° C. in O 2 1% in the mixed gas atmosphere of the silicon substrate 21 as shown in (d) in Ar99%, subjected to 2 hours annealing, ion implantation damage region 22 He atoms implanted into the damaged region 2
2 to form a hole region 23.

【0022】引き続き、次の条件でシリコン基板21内
部に酸素イオン(O+)を注入した。 加速電圧: 150 keV ドーズ量: 4×1017/cm2 基板加熱温度:600℃ シリコン基板21に酸素イオン注入した後、Ar99%
でO21%の混合ガス雰囲気中で1360℃、4時間シ
リコン基板をアニール処理を施してSOI基板を得た。
Subsequently, oxygen ions (O + ) were implanted into the silicon substrate 21 under the following conditions. Accelerating voltage: 150 keV Dose amount: 4 × 10 17 / cm 2 Substrate heating temperature: 600 ° C. After oxygen ions are implanted into the silicon substrate 21, Ar 99%
The silicon substrate was annealed at 1360 ° C. for 4 hours in a mixed gas atmosphere of 1% O 2 to obtain an SOI substrate.

【0023】<実施例> イオン注入損傷領域22を形成したシリコン基板21を
Ar99%でO21%の混合ガス雰囲気中で1000
℃、2時間アニール処理を施した以外は、シリコン基板
を実施例と同様に処理してSOI基板を得た。
Example 2 A silicon substrate 21 having an ion-implanted damaged region 22 formed thereon was prepared in a mixed gas atmosphere of 99% Ar and 1% O 2 in an atmosphere of 1000%.
A silicon substrate was treated in the same manner as in Example 1 except that annealing was performed at 2 ° C. for 2 hours to obtain an SOI substrate.

【0024】<評価> (a) 欠陥の密度 実施例1実施例2及び比較例1の各SOI基板の基板
表面のSi層中の転位欠陥密度を測定した。この転位欠
陥密度はSOI基板を酸化クロムを含む溶液により基板
表面をエッチングし、エッチングで拡大した転位欠陥を
電子顕微鏡で観察することにより求めた。その結果を表
1に示す。
<Evaluation> (a) Defect Density The dislocation defect density in the Si layer on the substrate surface of each of the SOI substrates of Example 1 , Example 2 and Comparative Example 1 was measured. The dislocation defect density was determined by etching the SOI substrate surface with a solution containing chromium oxide and observing the dislocation defects enlarged by etching with an electron microscope. Table 1 shows the results.

【0025】[0025]

【表1】 [Table 1]

【0026】表1から明らかなように、酸素イオン注入
後にArとO2の混合ガス雰囲気中で高温アニール処理
した比較例1の転位欠陥密度と比べて、Siと反応しな
Heイオンを注入した後にArとO 2 の混合ガス雰囲
気中で高温アニール処理した実施例1及び実施例の転
位欠陥密度は、いずれも小さかった
As is clear from Table 1, after implanting He ions which do not react with Si compared with the dislocation defect density of Comparative Example 1 which was subjected to high-temperature annealing in a mixed gas atmosphere of Ar and O 2 after oxygen ion implantation. dislocation defect density in example 1 and example 2 was high-temperature annealing in a mixed gas Kiri囲<br/> aerial of Ar and O 2 are both small.

【0027】(b) SOI基板の表面粗さ 実施例及び比較例1の各SOI基板表面の2μm×2
μmの領域における表面粗さを原子間力顕微鏡を用いて
測定した。その結果を表2に示す。表2において、Ra
は表面粗さのうち平均粗さ、Rmaxは最大高さ、Rzは十
点平均粗さを意味する。
(B) Surface roughness of SOI substrate 2 μm × 2 of the surface of each SOI substrate of Example 1 and Comparative Example 1
The surface roughness in the region of μm was measured using an atomic force microscope. Table 2 shows the results. In Table 2, Ra
Is the average roughness of the surface roughness, Rmax is the maximum height, and Rz is the ten-point average roughness.

【0028】[0028]

【表2】 [Table 2]

【0029】表2から明らかなように、比較例1のSO
I基板の表面粗さは著しく大きかったのに対して、実施
例1のSOI基板の表面粗さは小さくなり、初期のシリ
コンウェーハ程度であった。
As is clear from Table 2, the SO of Comparative Example 1
Whereas the surface roughness of the I substrate was significantly greater, performed
The surface roughness of the SOI substrate of Example 1 was small, and was about the same as the initial silicon wafer.

【0030】[0030]

【0031】[0031]

【0032】[0032]

【0033】(c) 埋込みシリコン酸化層の境界実施例1、実施例2 及び比較例1の各SOI基板の断面
を透過電子顕微鏡で観察し、埋込みシリコン酸化層の境
界の急峻性を観察した。その結果、比較例1の埋込みシ
リコン酸化層の境界がそれ程急峻でないのに対して、実
施例1及び2の埋込みシリコン酸化層の境界は急峻であ
った
(C) Boundary of Embedded Silicon Oxide Layer The cross section of each SOI substrate of Example 1, Example 2, and Comparative Example 1 was observed with a transmission electron microscope, and the steepness of the boundary of the embedded silicon oxide layer was observed. As a result, the boundary between the buried silicon oxide layers in Comparative Example 1 was not so steep, whereas the boundary between the buried silicon oxide layers in Examples 1 and 2 was steep .

【0034】[0034]

【発明の効果】以上述べたように、本発明のSOI基板
の製造方法によれば、シリコン基板に真空中でシリコン
と反応しないHeイオン等を注入して基板内部にイオン
注入損傷領域を形成した後、アニール処理をして空孔領
域を形成し、更に酸素イオンを注入し、この基板を酸化
性雰囲気中で高温でアニール処理することにより、酸素
原子が基板内部に拡散律速により拡散し、イオン注入に
より形成された空孔の存在により優先的にイオン注入損
傷領域に埋込みシリコン酸化層を形成することができ
る。従来の酸素イオン注入が極めて短時間に埋込みシリ
コン酸化層を形成して格子間シリコン原子を急激に生じ
ていたのに対して、この酸化は拡散律速で進行するた
め、格子間シリコン原子の急激な発生はなく、転位欠陥
を抑制することができる。特に注入イオンがHeイオン
又はHイオンのような原子量が小さい元素のイオンであ
る場合には、より一層基板の表面近傍のSi層の転位欠
陥が生じにくくなるとともに、酸素イオンに比べて低い
加速電圧で所定の深さにイオン注入損傷領域を形成でき
る。換言すれば、同じ加速電圧でも酸素イオン注入と比
べて本発明のイオン注入ではより深い領域に埋込みシリ
コン酸化層を形成することができる。この低い加速電圧
は境界が急峻で層厚の小さな埋込みシリコン酸化層の形
成を容易にし、SiO2の析出制御を容易にする。また
イオン注入時にSi層表面のスパッタリングが減少し、
基板の表面粗さが小さくなる。同時に装置内壁のスパッ
タリングが大幅に低減され、基板への重金属の汚染が低
減される。
As described above, according to the method for manufacturing an SOI substrate of the present invention, a He ion or the like which does not react with silicon is implanted into a silicon substrate in a vacuum to form an ion-implanted damaged region inside the substrate. After that , annealing treatment
A region is formed, oxygen ions are further implanted, and the substrate is oxidized.
Annealing at a high temperature in a neutral atmosphere diffuses oxygen atoms into the substrate by diffusion control, and preferentially forms a buried silicon oxide layer in the ion-implanted damaged region due to the presence of vacancies formed by ion implantation. be able to. Whereas conventional oxygen ion implantation forms a buried silicon oxide layer in a very short time and rapidly generates interstitial silicon atoms, this oxidation proceeds with diffusion control, so the rapid There is no occurrence, and dislocation defects can be suppressed. In particular, when the implanted ions are ions of an element having a small atomic weight such as He ions or H ions, dislocation defects in the Si layer near the surface of the substrate are more unlikely to occur, and the acceleration voltage is lower than that of oxygen ions. Thus, an ion implantation damaged region can be formed at a predetermined depth. In other words, even with the same acceleration voltage, the buried silicon oxide layer can be formed in a deeper region by the ion implantation of the present invention as compared with the oxygen ion implantation. This low accelerating voltage facilitates formation of a buried silicon oxide layer having a sharp boundary and a small thickness, and facilitates control of SiO 2 deposition. Also, sputtering on the surface of the Si layer during ion implantation is reduced,
The surface roughness of the substrate is reduced. At the same time, the sputtering of the inner wall of the apparatus is greatly reduced, and the contamination of the substrate with heavy metals is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例のSOI基板の製造方法を模式
的に示す図。
FIG. 1 is a view schematically showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.

【符号の説明】20 SOI基板21 シリコン基板21a 基板表面のSi層22 イオン注入損傷領域23 空孔領域 24 SiOx領域25 酸素原子26 埋込みシリコン酸化層[Description of Signs] 20 SOI substrate 21 Silicon substrate 21a Si layer on substrate surface 22 Ion implantation damaged region 23 Vacancy region 24 SiOx region 25 Oxygen atom 26 Embedded silicon oxide layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平8−191140(JP,A) 特開 平8−111453(JP,A) 特開 平1−108764(JP,A) 特開 昭48−21979(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 27/12 H01L 21/265 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-8-191140 (JP, A) JP-A-8-111453 (JP, A) JP-A-1-108764 (JP, A) JP-A 48-81 21979 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 27/12 H01L 21/265

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 シリコン基板(21)に真空中で少なくとも
HeイオンHイオン、Arイオン又はSiイオンを注
入することにより前記シリコン基板(21)内部にイオン注
入損傷領域(22)を形成する工程と、 前記イオン注入損傷領域(22)が形成されたシリコン基板
(21)を800〜1400℃の温度でアニール処理して前
記領域(22)に注入されたHe原子H原子、Ar原子又
はSi原子を前記領域(22)より放出して空孔領域(23)を
形成する工程と、 前記シリコン基板(21)内部に酸素イオンを注入して前記
空孔領域(23)を中心にSiOx領域(24)を形成する工程
と、 前記SiOx領域(24)が形成されたシリコン基板(21)を
酸化性雰囲気中で1000℃〜1400℃の温度でアニ
ール処理して前記シリコン基板(21)表面から所定の深さ
の領域に埋込みシリコン酸化層(26)を形成して前記基板
表面に単結晶Si層(21a)を形成する工程とを含むこと
を特徴とするSOI基板の製造方法。
1. A step of forming an ion-implanted damaged region (22) inside a silicon substrate (21) by implanting at least He ions , H ions , Ar ions or Si ions in a silicon substrate (21) in a vacuum. A silicon substrate on which the ion implantation damaged region (22) is formed
(21) is annealed at a temperature of 800 to 1400 ° C., and He atoms , H atoms , Ar atoms or
Forming a vacancy region (23) by releasing Si atoms from the region (22); and implanting oxygen ions into the silicon substrate (21) to form SiOx around the vacancy region (23). Forming a region (24); annealing the silicon substrate (21) on which the SiOx region (24) is formed at a temperature of 1000 ° C. to 1400 ° C. in an oxidizing atmosphere; Forming a buried silicon oxide layer (26) in a region having a predetermined depth from the substrate and forming a single-crystal Si layer (21a) on the surface of the substrate.
【請求項2】 アニール処理して埋込シリコン酸化層(2
6)を形成した後にシリコン基板(21)表面を研磨する工程
を更に含む請求項記載のSOI基板の製造方法。
2. A buried silicon oxide layer (2)
Method of manufacturing a SOI substrate according to claim 1, further comprising a step of polishing the silicon substrate (21) surface after forming the 6).
【請求項3】 注入するイオンがHeイオン又はHイオ
ンであるとき、そのイオン注入時のドーズ量が1×10
16/cm2〜5×1017/cm2で、加速電圧が40ke
V〜200keVである請求項1又は2記載のSOI基
板の製造方法。
3. When the ions to be implanted are He ions or H ions, the dose at the time of the ion implantation is 1 × 10 5.
16 / cm 2 -5 × 10 17 / cm 2 and acceleration voltage of 40 ke
The method for manufacturing an SOI substrate according to claim 1 or 2 wherein the V~200keV.
【請求項4】 埋込シリコン酸化層(26)を形成するため
のアニール処理が酸化性雰囲気中、10〜100気圧下
で行われる請求項1ないし3いずれか記載のSOI基板
の製造方法。
4. A buried silicon oxide layer during the annealing treatment for forming (26) an oxidizing atmosphere, claims 1 to 3 SOI substrate manufacturing method according to any one carried out under 10 to 100 atm.
JP08062534A 1995-03-20 1996-03-19 Method for manufacturing SOI substrate Expired - Fee Related JP3097827B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08062534A JP3097827B2 (en) 1995-03-20 1996-03-19 Method for manufacturing SOI substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-60219 1995-03-20
JP6021995 1995-03-20
JP08062534A JP3097827B2 (en) 1995-03-20 1996-03-19 Method for manufacturing SOI substrate

Publications (2)

Publication Number Publication Date
JPH08321594A JPH08321594A (en) 1996-12-03
JP3097827B2 true JP3097827B2 (en) 2000-10-10

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ID=26401289

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200478682Y1 (en) * 2014-11-05 2015-11-13 유재정 Multipurpose drying unit

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
KR100565438B1 (en) 1998-02-02 2006-03-30 신닛뽄세이테쯔 카부시키카이샤 Soi substrate and method for manufacturing the same
FR2784796B1 (en) * 1998-10-15 2001-11-23 Commissariat Energie Atomique PROCESS FOR PRODUCING A LAYER OF MATERIAL BURIED IN ANOTHER MATERIAL
JP4531339B2 (en) * 2003-01-28 2010-08-25 富士通セミコンダクター株式会社 Manufacturing method of semiconductor substrate
JP4655797B2 (en) * 2005-07-19 2011-03-23 信越半導体株式会社 Manufacturing method of directly bonded wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200478682Y1 (en) * 2014-11-05 2015-11-13 유재정 Multipurpose drying unit

Also Published As

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