JPH0832084A - Insulated-gate transistor - Google Patents

Abstract

PURPOSE:To discharge effectively heat in a single crystal semiconductor layer to the outside by a method wherein the insulating layer of a semiconductor substrate is substituted with a semiconductor layer, wherein impurities having a first conductivity type are introduced in a high concentration compared with that of the impurities in a channel region and which has the first conductivity type. CONSTITUTION:P-type impurities are introduced in a single crystal semiconductor substrate main body 2 of a semiconductor substrate 1 in a high concentration compared with that of the P-type impurities in a channel region 8 and the main body 2 has a P-type. Moreover, an insulating layer 3 of the substrate 1 is substituted with a P-type semiconductor layer 21, which is continually connected with the main body 2 only at its region continually connected with the region 8 excluding its regions which are continually connected with a drain region 7 and an offset region 6, and is continually connected only with the region 8, and at the same time, in which the P-type impurities are introduced in a high concentration compared with that of the P-type impurities in th region 8. Thereby, heat, which is generated in a single crystal semiconductor layer 4, can be effectively discharged to the outside via the main body 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect type and bipolar type insulated gate transistors.

[0002]

2. Description of the Related Art Heretofore, a field effect type insulated gate transistor which has been described below with reference to FIGS. 9 and 10 has been proposed.

That is, for example, a single crystal half made of silicon
On the conductor substrate body 2, for example, SiO ₂ Insulating layer 3 consisting of
Impurity that gives, for example, p-type as the first conductivity type through
Single crystal having p-type, in which substances are introduced at a relatively low concentration
The semiconductor substrate 1 on which the crystalline semiconductor layer 4 is formed is used.
Then, a single crystal is formed in the single crystal semiconductor layer 4 of the semiconductor substrate 1.
From the side opposite to the crystal semiconductor substrate body 2 side
The impurity that gives the n-type as the second conductivity type opposite to
Source region having n-type introduced at a relatively high concentration
5 and n-type impurities are introduced at a relatively low concentration.
Offset region 6 having n-type and source region
Not connected to area 5 but connected to offset area 6
In addition, the impurities that give the n-type are introduced at a relatively high concentration.
And the drain region 7 having the n-type are both insulated.
To the depth reaching layer 3, and the source region 5 and offset
Connected to region 6 but connected to drain region 7
Formed so as not to form the channel region 8
There is.

In addition, the single crystal semiconductor layer 4 of the semiconductor substrate 1 has a p-type in which an impurity imparting p-type is introduced at a relatively high concentration from the side opposite to the single-crystal semiconductor substrate body 2 side. The back gate voltage applying region 9 (FIG. 10) is juxtaposed and connected to the source region 5, and one end thereof is connected to the source region 5.
At the same time, the offset region 8 is formed to a depth reaching the insulating layer 3 so as to face the source region 5 side and the end.

Furthermore, on the semiconductor substrate 1, the gate electrode 10 is formed on the single crystal semiconductor layer 4, and the gate insulating film 11 is formed.
It is formed so as to face the channel region 8 via.

Further, on the semiconductor substrate 1, the source electrode 12 which is ohmicly connected to the source region 5 is formed on the back gate voltage applying region 9 so as to be ohmicly connected and extended. , The drain electrode 13 ohmicly connected to the drain region 7
Are formed. In addition, in FIG. 9 and FIG.
Reference numeral 4 is an interlayer insulating layer formed on the semiconductor substrate 11.

The above is the structure of the conventionally proposed field effect type insulated gate transistor.

According to the conventional field effect type insulated gate transistor having such a structure, the source electrode 12
A load (not shown) is connected between the drain electrode 13 and the drain electrode 13, and thus between the source region 5 and the drain region 7, via a power source (not shown) having the positive electrode side as the drain electrode 13 side, and the source If a control voltage source (not shown) is connected between the electrode 12 and the gate electrode 10, and thus between the source region 5 and the drain region 10, the gate of the channel region 8 is changed according to the value of the control voltage from the control voltage source. It is possible to control the formation of the n-channel extending between the source region 5 and the offset region 6 on the side of the insulating film 11, and thus, the source electrode 12, that is, the source region 5, and the drain electrode 13, that is, the drain region 7 are controlled. It is possible to control the ON state between the control voltage source and the control circuit, and thus to control the supply of current to the load according to the value of the control voltage from the control voltage source. Cormorants function as field effect insulated gate transistor is obtained.

Further, in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10 which can obtain such a function, a p type single transistor is formed on the single crystal semiconductor substrate body 2 through the insulating layer 3. Since the semiconductor substrate 1 on which the crystalline semiconductor layer 3 is formed is used, the semiconductor substrate 1 causes the leakage current between the source region 5, the offset region 6 and the drain region 7 on the single crystal semiconductor substrate body 2. If the semiconductor substrate is replaced with a semiconductor substrate on which the single crystal semiconductor layer 3 is formed without interposing the insulating layer 3, or the semiconductor substrate 1 is a p-type semiconductor substrate 1 whose main surface side is used as the p-type single crystal semiconductor layer 3. It can be made sufficiently smaller than the case where the single crystal semiconductor substrate is replaced.

Further, in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10, the offset region 6 having a relatively low n-type impurity concentration is disposed between the channel region 8 and the drain region 7. Since the breakdown voltage between the source electrode 12 and the drain electrode 13, that is, between the source region 5 and the drain region 7 is such that the offset region 6 and the drain region 7 are replaced with the same drain region as the drain region 7, Therefore, the offset region 6 and the drain region 7 are replaced by the same drain region as the drain region 7, so that the voltage of the power source connected through the load between the source electrode 12 and the drain electrode 13 is limited. It can be relaxed compared to the case where it is.

Further, in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10, since the back gate voltage applying region 9 is provided, the back gate having the same potential as the source region 5 is formed in the channel region 8. A voltage can be applied via the source electrode 12, and thus the function as the above-mentioned field effect type insulated gate transistor can be stably obtained.

Further, conventionally, a bipolar type insulated gate transistor described below with reference to FIGS. 11 and 12 has been proposed. Note that in FIG. 11 and FIG.
The same parts as those in FIG. 10 are designated by the same reference numerals.

That is, similar to the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10,
For example, an impurity imparting, for example, p-type as the first conductivity type is introduced at a relatively low concentration onto the single crystal semiconductor substrate body 2 made of, for example, silicon through the insulating layer 3 made of, for example, SiO ₂ . 1. A semiconductor substrate 1 on which a single crystal semiconductor layer 4 having a p-type as a conductivity type of 1 is formed is used, and in the single crystal semiconductor layer 4 of the semiconductor substrate 1, the single crystal semiconductor substrate main body 2 side is An n-type source region 5 in which an impurity imparting n-type as a second conductivity type opposite to the first conductivity type is introduced at a relatively high concentration from the opposite side.
And an n-type offset region 6 into which an impurity imparting n-type is introduced at a relatively low concentration, and is not connected to the source region 5 but is connected to the offset region 6.
In addition, the p-type drain region 27 in which the impurity imparting p-type is introduced at a relatively high concentration is the source region 5
The drain region 27 has a depth not reaching the insulating layer 3, the offset region 6 has a depth reaching the insulating layer 3, and the drain region 7 is connected to the source region 5 and the offset region 6. Are formed so as to form the channel region 8 which is not connected.

Further, the single crystal semiconductor layer 4 of the semiconductor substrate 1 has a p-type in which impurities imparting p-type are introduced at a relatively high concentration from the side opposite to the single-crystal semiconductor substrate body 2 side. The back gate voltage applying region 9 is the source region 5
Is formed at a depth that does not reach the insulating layer 3 so as to be connected on the side opposite to the channel region 8 side.

Further, on the single crystal semiconductor layer 4 on the semiconductor substrate 1, the gate electrode 10 is the same as in the case of the conventional insulated gate transistor shown in FIGS. 9 and 10.
The gate insulating film 11 is formed so as to face the channel region 8.

On the semiconductor substrate 1, the source electrode 12 is formed on the source region 5 in ohmic contact therewith, and is formed in the back gate voltage applying region 9 in ohmic connection therewith. At the same time, a drain electrode 13 that is ohmic-connected to the drain region 7 is formed. 9 and 10, reference numeral 14 denotes an interlayer insulating layer formed on the semiconductor substrate 11.

The above is the configuration of the bipolar type insulated gate transistor which has been conventionally proposed.

According to the conventional insulated gate type transistor having such a structure, the source electrode 12 and the drain electrode 13, and thus the source region 5 are formed as in the conventional insulated gate type transistor shown in FIGS. 9 and 10. A load (not shown) is connected between the drain electrode 27 and the drain region 27 via a power source (not shown) having the positive electrode side as the drain electrode 13 side, and also between the source electrode 12 and the gate electrode 10, thus the source region. If a control voltage source (not shown) is connected between the gate electrode 10 and the gate electrode 10, the source region 5 and the offset region 6 on the gate insulating film 11 side of the channel region 8 depending on the value of the control voltage from the control voltage source. It is possible to control the formation of n-channels extending in between, and thus the source electrode 12, and thus the source region 5, and the drain electrode 1.
3 and thus the drain region 4 can be controlled to be turned on and in this case the drain region 2
7 has a p-type, unlike the drain region 7 in the case of the field effect type insulated gate transistor shown in FIG. 9 and FIG.
Holes can be injected into the channel region 8 side through, so that the current is supplied to the load according to the value of the control voltage from the control voltage source, and the current at the time of supplying the current is set as shown in FIGS. 9 and 10. It is possible to obtain a function as a bipolar insulated gate transistor that can be controlled in such a manner that the value can be made larger than that of the conventional field effect insulated gate transistor shown in FIG.

Further, in the case of the conventional field effect type insulated gate transistor shown in FIGS. 11 and 12 which can obtain such a function, the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10 is also used. As in the case of, the semiconductor substrate 1 in which the p-type single crystal semiconductor layer 3 is formed on the single crystal semiconductor substrate body 2 with the insulating layer 3 interposed therebetween is used, so that the source region 5, the offset region 6, and It is assumed that the current leakage between the drain region 7 and the semiconductor substrate 1 is replaced by the semiconductor substrate in which the single crystal semiconductor layer 3 is formed on the single crystal semiconductor substrate body 2 without the insulating layer 3 interposed therebetween. In this case, or when the semiconductor substrate 1 is replaced with a p-type single crystal semiconductor substrate used as the p-type single crystal semiconductor layer 3 on the main surface side, it can be made sufficiently small.

Further, in the case of the conventional bipolar type insulated gate transistor shown in FIGS. 11 and 12, the channel region 8 is formed in the same manner as the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10. Since the offset region 6 having a relatively low n-type impurity concentration is arranged between the drain region 27 and the drain region 27, the breakdown voltage between the source electrode 12 and the drain electrode 13, and thus between the source region 5 and the drain region 27 is It is higher than the case where the offset region 6 and the drain region 27 are replaced with the same drain region as the drain region 27, and therefore,
The offset region 6 and the drain region 27 are replaced with the same drain region as the drain region 27 to limit the voltage of the power supply connected between the source electrode 12 and the drain electrode 13, and thus between the source region 5 and the drain region 27 through a load. It can be relaxed compared to the case where it is.

Also, in the case of the conventional bipolar type insulated gate type transistor shown in FIGS. 11 and 12, the back gate is formed similarly to the case of the conventional field effect type insulated gate type transistor shown in FIGS. 9 and 10. Voltage application area 9
Therefore, a back gate voltage having the same potential as that of the source region 5 can be applied to the channel region 8 via the source electrode 12, and thus the above-described function as a bipolar insulated gate transistor can be stably obtained. be able to.

[0022]

In the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10,
It is unavoidable that heat is generated in the single crystal semiconductor layer 4 when the above-mentioned function as the field effect type insulated gate transistor is obtained, and the heat is passed through the insulating layer 3 and then the single crystal. Although it can be released to the outside through the semiconductor substrate body 2, the thermal conductivity of the insulating layer 3 is lower than that of the single crystal semiconductor substrate body 2. Therefore, the heat generated in the single crystal semiconductor layer 4 cannot be effectively radiated to the outside through the single crystal semiconductor substrate body 2, and
It has a drawback that the above-mentioned function as the field effect type insulated gate transistor cannot be stably obtained for a long period of time.

The conventional field effect type insulated gate transistor shown in FIGS. 9 and 10 has a back gate voltage applying region 9 for applying a back gate voltage to the channel region 8, and The end of the back gate voltage applying region 9 on the side of the gate electrode 10 is arranged so as to face the end of the offset region 6 on the side of the gate electrode 10 in parallel with the end of the source region 5 on the side of the gate electrode 10. Therefore, as compared with the case where the source region 5 and the back gate voltage applying region 9 are replaced with the same source region as the source region 5, the effective gate width is smaller than that of the gate electrode 10 of the back gate voltage applying region 9. Narrow as much as the width of the side edge. Therefore, when the ON state is obtained between the source region 5 and the drain region 13 as described above, the resistance at the ON time is the same as the source region 5 and the back gate voltage applying region 9 are the same as the source region 5. It has a drawback that it is higher than the case where it is replaced with a region, and therefore has a certain limit for obtaining the function as the above-mentioned field effect type insulated gate transistor at high speed.

Further, in the case of the conventional field effect type insulated gate type transistor shown in FIGS. 9 and 10, the effective gate width as the field effect type insulated gate type transistor described above is applied to the source region 5 and the back gate voltage. The width of the end of the source region 5 on the side of the gate electrode 10 is set so as to be the same as when the source region 5 is replaced with a source region similar to the source region 5. Assuming that the region 9 is replaced with a source region similar to the source region 5, the width of the end of the source region 5 on the gate electrode 10 side and the side of the back gate voltage applying region 9 on the gate electrode 10 side. The width of the edge of the back gate voltage applying region 9 on the side of the gate electrode 10 is wider than the effective gate width in this case. The gate capacitance of the gate transistor is increased, thus, had the disadvantage, has a certain limit to obtain a function as an insulating gate type transistor of the field effect described above at high speed. This means that the width of the end of the source region 5 on the gate electrode 10 side is
The end of the offset region 8 on the side of the gate electrode 10 is prepared in the same manner as when the source region 5 and the back gate voltage applying region 9 are replaced with the same source region as the source region 5. Since it is possible to make the width of the sum of the width of the end of the source region 5 on the gate electrode 10 side and the width of the end of the back gate voltage applying region 9 on the gate electrode 10 side in this case, This is all the more so.

In the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10, the source region 5 is used.
A parasitic bipolar transistor having the source region 5 as an emitter, the channel region 8 as a base, and the offset region 6 as a collector is constituted by the channel region 8 and the offset region 6, and the base resistance of the parasitic bipolar transistor serves as the base. Channel region 8 is p
It is relatively high because the impurities that give the mold are introduced only at a relatively low concentration and it is composed of a part of the single crystal semiconductor layer 4 having a small thickness. Therefore, the parasitic bipolar transistor is in the ON state. When the parasitic bipolar transistor is turned on, the function as the field effect type insulated gate transistor cannot be obtained.

Further, in the case of the conventional bipolar type insulated gate type transistor shown in FIGS. 11 and 12, when the above-mentioned function as the bipolar type insulated gate type transistor is obtained, the conventional bipolar type insulated gate type transistor shown in FIGS. As in the case of the field effect type insulated gate transistor, it is inevitable that heat is generated in the single crystal semiconductor layer 4, and the heat is transmitted through the insulating layer 3 and then the single crystal semiconductor substrate main body 2
Although it can be released to the outside through the insulating layer 3, the thermal conductivity of the insulating layer 3 is lower than that of the single crystal semiconductor substrate body 2.
Therefore, the heat generated in the single crystal semiconductor layer 4 cannot be effectively radiated to the outside via the single crystal semiconductor substrate body 2, and therefore, the bipolar insulated gate transistor described above is used. It has a drawback that the function cannot be stably obtained for a long period of time.

In the case of the conventional bipolar type insulated gate transistor shown in FIGS. 11 and 12, the source region 5 is formed as in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10. And channel area 8
The offset region 6 constitutes a parasitic bipolar transistor having the source region 5 as an emitter, the channel region 8 as a base, and the offset region 6 as a collector, and the parasitic bipolar transistor has a base resistance of
Since the channel region 8 serving as a base is introduced with impurities imparting p-type only at a relatively low concentration and is composed of a part of the single crystal semiconductor layer 4 having a small thickness, it is relatively high, When the function as the bipolar type insulated gate transistor described above is obtained, as described above, the drain region 27 is passed through the offset region 6 as the collector and the channel region 8 as the base.
Since the holes are injected into the side, the parasitic bipolar transistor has a higher possibility of being turned on than that of the conventional insulated gate transistor shown in FIGS. 9 and 10. When turned on, the function as the bipolar type insulated gate transistor described above cannot be obtained.

Therefore, the present invention does not have the above-mentioned drawbacks.
We propose new field-effect and bipolar insulated gate transistors.

The field effect type insulated gate transistor according to the present invention is similar to the case of the conventional insulated gate transistor described above with reference to FIGS. 9 and 10.
(A) A single crystal semiconductor layer having a first conductivity type in which an impurity imparting the first conductivity type is introduced at a relatively low concentration through an insulating layer is formed on a single crystal semiconductor substrate body. And (b) a second conductivity type opposite to the first conductivity type from a side opposite to the single crystal semiconductor substrate body side in the single crystal semiconductor layer of the semiconductor substrate. Second, which introduces a relatively high concentration of impurities that give
Source region having a second conductivity type, an offset region having a second conductivity type in which an impurity imparting a second conductivity type is introduced at a relatively low concentration, and the source region having no conductivity type. A drain region having a second conductivity type, which is connected to the offset region and into which impurities imparting the second conductivity type are introduced at a relatively high concentration, is connected to the source region and the offset region. However, the gate electrode is formed so as to form a channel region that is not connected to the drain region, and (c) the gate electrode is formed on the single crystal semiconductor layer on the semiconductor substrate via the gate insulating film. It is formed so as to face the channel region.

However, the field effect type insulated gate transistor according to the present invention is the same as the field effect type insulated gate transistor having the above structure.
(D) The single crystal semiconductor substrate body of the semiconductor substrate is the first
An impurity imparting the conductivity type is introduced at a higher concentration than the channel region, and has the first conductivity type.
(E) The insulating layer of the semiconductor substrate is connected to the main body of the single crystal semiconductor substrate and at least connected to the channel region at least in the region connected to the channel region, and has the first conductivity type. It is replaced by a semiconductor layer having the first conductivity type, in which the impurity to be introduced is introduced at a higher concentration than the channel region.

Further, the bipolar insulated gate transistor according to the present invention is (a) as in the case of the conventional insulated gate transistor described in FIGS. 11 and 12.
An impurity imparting the first conductivity type is introduced at a relatively low concentration over the single crystal semiconductor substrate body through an insulating layer.
A semiconductor substrate on which a single crystal semiconductor layer having a first conductivity type is formed is used, and (b) in the single crystal semiconductor layer of the semiconductor substrate, from the side opposite to the single crystal semiconductor substrate body side. , Comparing a source region having a second conductivity type with an impurity giving a second conductivity type opposite to the first conductivity type introduced at a relatively high concentration, and an impurity giving a second conductivity type. An offset region having a second conductivity type, which is introduced at a relatively low concentration, is connected to the source region but is not connected to the source region, and the first region
And a drain region having a first conductivity type in which an impurity imparting a conductivity type is introduced at a relatively high concentration is connected to the source region and the offset region but is connected to the drain region. And (c) a gate electrode on the single crystal semiconductor layer on the semiconductor substrate so as to face the channel region via a gate insulating film. It is formed.

However, the bipolar insulated gate transistor according to the present invention is the same as the bipolar insulated gate transistor having the above structure.
(D) The single crystal semiconductor substrate body of the semiconductor substrate is the first
An impurity imparting the conductivity type is introduced at a higher concentration than the channel region, and has the first conductivity type.
(E) The insulating layer of the semiconductor substrate is connected to the main body of the single crystal semiconductor substrate and at least connected to the channel region at least in the region connected to the channel region, and has the first conductivity type. It is replaced by a semiconductor layer having the first conductivity type, in which the impurity to be introduced is introduced at a higher concentration than the channel region.

[0032]

According to the field effect type insulated gate transistor of the present invention, the single crystal semiconductor substrate body of the semiconductor substrate introduces the impurity imparting the first conductivity type at a higher concentration than the channel region. Has a first conductivity type,
In addition, at least in the region where the insulating layer of the semiconductor substrate is in contact with the channel region, the insulating layer is in contact with the single crystal semiconductor substrate body and at least with the channel region, and impurities that give the first conductivity type are added to the channel region. Except that the semiconductor layer having the first conductivity type is replaced with a semiconductor layer having a first conductivity type,
Since it has the same structure as the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10, it is the same as the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10. In addition, a load (not shown) is connected between the source region and the drain region through a power supply (not shown), and a control voltage source (not shown) is connected between the source region and the gate electrode. For example, it is possible to control the formation of the n channel extending between the source region and the offset region on the gate insulating film side of the channel region according to the value of the control voltage from the control voltage source.
It is possible to control turning on between the source region and the drain region, and thus it is possible to control the supply of current to the load according to the value of the control voltage from the control voltage source. The function as a field effect type insulated gate transistor can be obtained.

Further, in the case of the field effect type insulated gate transistor according to the present invention which can obtain such a function, as in the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10, Since the semiconductor substrate in which the single crystal semiconductor layer having the first conductivity type is formed over the single crystal semiconductor substrate body with the insulating layer interposed therebetween, leakage between the source region and the offset region and the drain region is caused. When the electric current is replaced with the semiconductor substrate in which the single crystal semiconductor layer is formed without interposing the insulating layer on the single crystal semiconductor substrate body, or when the semiconductor substrate is the first surface on the main surface side. It can be made sufficiently smaller than the case where the single crystal semiconductor substrate having the first conductivity type used as the single crystal semiconductor layer having the conductivity type is substituted.

Further, in the case of the field effect type insulated gate type transistor according to the present invention, as in the case of the conventional field effect type insulated gate type transistor described above with reference to FIGS. 9 and 10, between the channel region and the drain region. Since the offset region having the impurity concentration giving the relatively low second conductivity type is arranged, the offset voltage between the source region and the drain region is the same as that of the drain region. Therefore, the offset region and the drain region are replaced with the same drain region as the drain region, so that the voltage limit of the power supply connected through the load between the source region and the drain region is higher than that of the drain region. Compared with the case where it is done, it can be alleviated.

Further, according to the field effect type insulated gate transistor according to the present invention, as in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10, the field effect type insulated gate transistor described above is used. It is unavoidable that heat is generated in the single crystal semiconductor layer when the function as the gate type transistor is obtained, and the heat is generated through the insulating layer 3 and then through the single crystal semiconductor substrate body. The semiconductor layer has a semiconductor layer replacing a part of the insulating layer, and the semiconductor layer can be discharged to the outside.
Along with the main body of the single crystal semiconductor substrate, since it has a higher thermal conductivity than the insulating layer, the heat generated in the single crystal semiconductor layer is
Through the semiconductor layer partially replacing the insulating layer and the single crystal semiconductor substrate body, it can be effectively released to the outside,
Therefore, the function as the above-described field effect type insulated gate transistor can be stably obtained for a long period of time.

According to the field effect type insulated gate transistor of the present invention, the single crystal semiconductor substrate body of the semiconductor substrate has the first conductivity type, and the insulating layer is partially replaced. Since the semiconductor layer having the conductivity type of 1 is included, a back gate voltage can be applied to the channel region through the semiconductor layer partially replacing the main body of the single crystal semiconductor substrate and the semiconductor layer. The function as an effect-type insulated gate transistor can be stably obtained.

For this reason, the end on the gate electrode side faces the end on the gate electrode side of the offset region as in the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10. It is possible to omit the back gate voltage applying region which is disposed as a result, and to have the drawbacks regarding the effective gate width and the gate capacitance described in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10. Therefore, the function of the above-described field effect type insulated gate transistor can be obtained at a higher speed than that of the conventional field effect type insulated gate transistor described with reference to FIGS. 9 and 10.

Further, according to the field effect type insulated gate transistor of the present invention, the source region, the channel region and the offset are offset from each other as in the case of the conventional field effect type insulated gate transistor shown in FIGS. 9 and 10. With regions, the source region is the emitter, the channel region is the base,
A parasitic bipolar transistor having an offset region as a collector is constructed. In this case, a channel region has a part of an insulating film formed on a single crystal semiconductor substrate body having the same first conductivity type as the first conductivity type. Since the base resistance of the parasitic bipolar transistor is connected through the replacing semiconductor layer, the channel region as the base introduces the impurity giving the first conductivity type in a relatively low concentration. Even if it is composed of a part of the semiconductor layer, it is lower than the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10, and therefore the parasitic bipolar transistor may be turned on. Therefore, it is possible to effectively avoid the possibility that the function as the field effect type insulated gate transistor cannot be obtained. .

Further, according to the bipolar type insulated gate transistor of the present invention, the single crystal semiconductor substrate body of the semiconductor substrate introduces the impurity imparting the first conductivity type at a higher concentration than the channel region. A first conductivity type, and at least in a region where the insulating layer of the semiconductor substrate is in contact with the channel region, the insulating layer is connected to the single crystal semiconductor substrate body and at least to the channel region, and 11 and 12 except that the impurity imparting the first conductivity type is introduced at a higher concentration than the channel region and is replaced by the semiconductor layer having the first conductivity type. Since the structure is similar to that of the conventional field effect type insulated gate transistor, detailed description thereof will be omitted, but the conventional field effect type transistor shown in FIGS. Together with the features described in the insulated gate transistor, having the characteristics described for insulated gate transistor of the field-effect according to the present invention.

[0040]

[Embodiment 1] Next, a first embodiment of a field effect type insulated gate transistor according to the present invention will be described with reference to FIGS.

1 and 2, parts corresponding to those in FIGS. 9 and 10 are designated by the same reference numerals, and detailed description thereof will be omitted.

The field effect type insulated gate type transistor according to the present invention shown in FIGS. 1 and 2 is the same as the conventional field effect type insulated gate type transistor shown in FIG. 9 and FIG. Substrate body 2 is p
-Type impurities are introduced at a higher concentration than the channel region 8 and have p-type, and the insulating layer 3 of the semiconductor substrate 1 is also included.
Is connected to the single crystal semiconductor substrate body 2 and is connected only to the channel region 8 only in the region connected to the channel region 8 except for the region connected to the drain region 7 and the offset region 6. At the same time, p-type impurities are introduced at a higher concentration than the channel region 8.
The p-type semiconductor layer 21 replaces the source region 5 and the back gate voltage applying region 9 with the same source region as the source region 5 (this is referred to as the source region 5), and the single crystal semiconductor substrate Insulating layer 3 on body 2
On the side opposite to the side, the back gate voltage applying voltage 2
It has the same structure as the case of the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10, except that 2 is ohmic. In this case, the semiconductor layer 21 can be made of a single crystal semiconductor or a polycrystalline semiconductor.

The above is the first embodiment of the field effect type insulated gate transistor according to the present invention.

According to the embodiment of the field effect type insulated gate transistor of the present invention having the above structure,
Except for the matters described above, it has the same configuration as the conventional field effect type insulated gate transistor described above with reference to FIGS. 9 and 10, and thus detailed description thereof will be omitted.
In addition to having the advantages described in the conventional field effect type insulated gate transistor shown in (3), it has the excellent features described in the section of action and effect.

[0045]

Second Embodiment Next, a second embodiment of the field effect type insulated gate transistor according to the present invention will be described with reference to FIGS. 3 and 4.

3 and 4, parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The field effect type insulated gate transistor according to the present invention shown in FIGS. 3 and 4 is the same as the field effect type insulated gate transistor according to the present invention shown in FIGS. But the channel area 8
Instead of being replaced by the semiconductor layer 21 only in the region connected to the source region 5, the region connected to the source region 5 also extends continuously from below the channel region 8 to the source region 5. It has the same structure as the field effect type insulated gate transistor according to the present invention shown in FIGS. 1 and 2, except that the semiconductor layer 21 is replaced.

The above is the configuration of the second embodiment of the field effect type insulated gate transistor according to the present invention.

According to the field effect type insulated gate transistor according to the present invention having such a structure, the field effect type insulated gate transistor according to the present invention shown in FIGS. Although the detailed description is omitted because it has the same structure, the same action and effect as the field effect type insulated gate transistor according to the present invention shown in FIGS. 1 and 2 are obtained, and the field effect type insulated gate type transistor is obtained. The function as a transistor can be stably obtained with the channel region 8 and the source region 5 at the same potential.

[0050]

Third Embodiment Next, a first embodiment of the bipolar type insulated gate transistor according to the present invention will be described with reference to FIGS.

5 and 6, parts corresponding to those in FIGS. 11 and 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

The bipolar type insulated gate transistor according to the present invention shown in FIGS. 5 and 6 is shown in FIGS.
In the conventional bipolar insulated gate transistor described above, the single crystal semiconductor substrate body 2 of the semiconductor substrate 1 introduces an impurity imparting p-type at a higher concentration than that of the channel region 8 and thus has p-type conductivity. In addition, the insulating layer 8 of the semiconductor substrate 1 is connected to the single crystal semiconductor substrate body 2 and is connected to the channel region 8 only in the region connected to the channel region 8 except the region connected to the offset region 6. P-type impurity which is connected to the channel region 8 and has a higher concentration than the channel region 8.
Is replaced by a semiconductor layer 21 having a mold,
11 and 12, except that the back gate voltage applying electrode 22 is ohmic-attached to the single crystal semiconductor substrate body 2 on the side opposite to the insulating layer 3 side. It has the same structure as that of the insulated gate transistor.

According to the embodiment of the bipolar type insulated gate transistor according to the present invention having such a structure, except for the matters mentioned above, the conventional field effect type insulated gate type transistor described above with reference to FIGS. Since the transistor has the same configuration as the transistor, detailed description thereof will be omitted. However, the conventional bipolar insulated gate transistor shown in FIGS. 11 and 12 has the above-mentioned advantages, and has the features described in the section of action and effect. Have.

[0054]

Fourth Embodiment Next, a second embodiment of the bipolar type insulated gate transistor according to the present invention will be described with reference to FIGS. 7 and 8.

7 and 8, parts corresponding to those in FIGS. 5 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

The field effect type insulated gate type transistor according to the present invention shown in FIGS. 7 and 8 is the same as the bipolar type insulated gate type transistor according to the present invention shown in FIGS. , The region other than the channel region 8 of the single crystal semiconductor layer 4 is replaced by the semiconductor layer 21 only in the region connected to the channel region 8 and from the bottom of the channel region 8 to the region other than the channel region 8 The structure is similar to that of the bipolar insulated gate transistor according to the present invention shown in FIGS. 4 and 5, except that the semiconductor layer 21 is connected to the region of FIG.

The above is the configuration of the second embodiment of the field effect type insulated gate transistor according to the present invention.

According to the field effect type insulated gate transistor according to the present invention having such a structure, the field effect type insulated gate transistor according to the present invention shown in FIGS. 7 and 8 is provided except for the matters described above. Since it has the same configuration, detailed description thereof will be omitted, but it will be apparent that the same action and effect as the field effect type insulated gate transistor according to the present invention shown in FIGS. 4 and 5 can be obtained.

In the above description, only two embodiments are described for each of the field effect type insulated gate transistor and the bipolar type insulated gate transistor according to the present invention. For example, FIGS. And the field effect type insulated gate transistor according to the present invention shown in FIGS. 3 and 4, the same as the back gate voltage applying region 9 of the bipolar type insulated gate transistor according to the present invention shown in FIGS. A back gate voltage applying region may be provided in the same manner, and in the field effect type insulated gate transistor according to the present invention shown in FIGS. 3 and 4, 5, 6 and 7, The gate voltage applying electrode 22 can be omitted,
In the bipolar insulated gate transistor according to the present invention shown in FIGS. 5 and 6, the back gate voltage applying region 9 has a depth reaching the insulating film 3,
In the bipolar type according to the present invention shown in FIGS. 7 and 8, the back gate voltage applying region 9 has a depth reaching the semiconductor layer 21, and the book shown in FIGS. 5 and 6 and FIGS. In the bipolar insulated gate transistor according to the present invention, the back gate voltage applying region 9 may be omitted, and the field effect insulated gate transistor according to the present invention and the bipolar insulated transistor described above may be used. In the gate type transistor, the p-type may be read as an n-type and the n-type may be read as a p-type, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of a field effect type insulated gate transistor according to the present invention.

FIG. 2 is a schematic plan view showing a first embodiment of the field effect type insulated gate transistor according to the present invention shown in FIG.

FIG. 3 is a schematic cross-sectional view showing a second embodiment of the field effect type insulated gate transistor according to the present invention.

FIG. 4 is a schematic plan view showing a second embodiment of the field effect type insulated gate transistor according to the present invention shown in FIG.

FIG. 5 is a schematic sectional view showing a first embodiment of a bipolar insulated gate transistor according to the present invention.

FIG. 6 is a schematic plan view showing a first embodiment of the bipolar insulated gate transistor according to the present invention shown in FIG.

FIG. 7 is a schematic cross-sectional view showing a second embodiment of a bipolar insulated gate transistor according to the present invention.

FIG. 8 is a schematic plan view showing a second embodiment of the bipolar insulated gate transistor according to the present invention shown in FIG.

FIG. 9 is a schematic cross-sectional view showing a conventional field effect insulated gate transistor.

10 is a schematic plan view showing the conventional field effect insulated gate transistor shown in FIG.

FIG. 11 is a schematic cross-sectional view showing a conventional bipolar insulated gate transistor.

FIG. 12 is a schematic plan view showing the conventional bipolar insulated gate transistor shown in FIG.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Single Crystal Semiconductor Substrate Body 3 Insulating Layer 4 Single Crystal Semiconductor Layer 5 Source Region 6 Offset Region 7 Drain Region 8 Channel Region 9 Back Gate Voltage Applying Region 10 Gate Electrode 11 Gate Insulating Film 12 Source Electrode 13 Drain Electrode 14 Interlayer insulating layer 21 Semiconductor layer 22 Back gate voltage applying voltage 27 Drain region

Claims (2)

[Claims] 1. A single crystal semiconductor layer having a first conductivity type, in which an impurity imparting the first conductivity type is introduced at a relatively low concentration through an insulating layer on a single crystal semiconductor substrate body. An impurity that gives a second conductivity type opposite to the first conductivity type from a side opposite to the single crystal semiconductor substrate body side in the single crystal semiconductor layer of the semiconductor substrate using the formed semiconductor substrate. Source region having a second conductivity type in which is introduced at a relatively high concentration, and an offset region having a second conductivity type in which an impurity imparting the second conductivity type is introduced at a relatively low concentration. And a drain region having a second conductivity type, which is not connected to the source region but is connected to the offset region and into which impurities imparting the second conductivity type are introduced at a relatively high concentration. Is the source area and the offset area Is formed so as to form a channel region which is connected to the drain region but not to the drain region, and the gate electrode is formed on the single crystal semiconductor layer on the semiconductor substrate through the gate insulating film. In the field-effect type insulated gate transistor formed so as to face the channel region, the single crystal semiconductor substrate body of the semiconductor substrate has a higher impurity that imparts the first conductivity type than the channel region. Is introduced at a concentration, has the first conductivity type, and the insulating layer of the semiconductor substrate is connected to at least the channel region and is connected to the single crystal semiconductor substrate body and is at least the channel. Having the first conductivity type, the impurity which is connected to the region and gives the first conductivity type is introduced at a higher concentration than the channel region. A field effect type insulated gate transistor, characterized in that it is replaced by a semiconductor layer. 2. A single crystal semiconductor layer having a first conductivity type, in which an impurity imparting the first conductivity type is introduced at a relatively low concentration through an insulating layer on a single crystal semiconductor substrate body. An impurity that gives a second conductivity type opposite to the first conductivity type from a side opposite to the single crystal semiconductor substrate body side in the single crystal semiconductor layer of the semiconductor substrate using the formed semiconductor substrate. Source region having a second conductivity type in which is introduced at a relatively high concentration, and an offset region having a second conductivity type in which an impurity imparting the second conductivity type is introduced at a relatively low concentration. And a drain region having a first conductivity type, which is not connected to the source region but is connected to the offset region and into which an impurity imparting the first conductivity type is introduced at a relatively high concentration. Is the source area and the offset area Is formed so as to form a channel region which is connected to the drain region but not to the drain region, and the gate electrode is formed on the single crystal semiconductor layer on the semiconductor substrate through the gate insulating film. In the bipolar insulated gate transistor formed so as to face the channel region, the single crystal semiconductor substrate body of the semiconductor substrate has a higher concentration of impurities giving the first conductivity type than the channel region. And having the first conductivity type, the insulating layer of the semiconductor substrate is connected to the single crystal semiconductor substrate body and at least the channel region in at least a region where the insulating layer is connected to the channel region. The first conductivity type, which is connected to the first conductivity type and has a higher concentration of impurities that give the first conductivity type introduced into the channel region. A bipolar insulated gate transistor characterized by being replaced by a semiconductor layer having.