JPH0832009A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve efficiency of failure analysis of a semiconductor device wherein many outer leads are arranged along one side of a sealed body. CONSTITUTION:In a semiconductor device wherein many outer leads 3 are arranged along one side of a sealed body 1, scales for counting the number of outer leads 3 are constituted for every specified number of leads. The scales consist of colored outer leads 3A, outer leads formed wider than other outer leads 3, and marks formed on a single surface of the sealed body 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a large number of outer leads are arranged along one side of a sealing body.

[0002]

2. Description of the Related Art As a semiconductor device for sealing a semiconductor pellet on which a circuit system is mounted with a sealing body, for example, QFP
There is a semiconductor device that employs a (Quad Flat Package) structure. A semiconductor device adopting this QFP structure has been developed with the high integration of a circuit system mounted on a semiconductor pellet.
The number of outer leads arranged along one side of the sealing body increases, and the number of pins tends to increase.

The semiconductor device having the QFP structure is subjected to an aging test (acceleration test) and a selection test in the manufacturing process. The aging test is the one in which the circuit operation of the circuit system mounted on the semiconductor pellet is performed under conditions of use (load is applied) that are more severe than the conditions of use by the customer, causing defects during use by the customer. In a sense, the purpose is to accelerate the generation of defects and to eliminate defective products in the initial stage before shipping to customers. The screening test is intended to screen the electrical characteristics of the aged semiconductor pellets and screen the semiconductor device for non-defective and defective products.

[0004]

A failure analysis is performed on a semiconductor device which has become a defective product in the screening test. In the failure analysis, for example, a probe needle is brought into contact with a predetermined outer lead, and the resistance value of a semiconductor element forming a circuit system and the conduction state between wirings are checked. The predetermined outer lead is selected by the operator counting the number of outer leads from the first stage of the lead arrangement in which a large number of outer leads are arranged on one side of the sealing body.

However, the semiconductor device having the QFP structure tends to have a large number of pins, and the number of outer leads arranged on one side of the sealing body is 70 to 120. For this reason, there arises a problem that work efficiency at the time of failure analysis is reduced.

It is an object of the present invention to provide a technique capable of improving work efficiency during failure analysis of a semiconductor device in which a large number of outer leads are arranged along one side of a sealing body.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In a semiconductor device in which a large number of outer leads are arranged along one side of the sealing body, a scale for counting the number of the outer leads is formed for each predetermined number of leads.

[0010]

According to the above-mentioned means, the number of the outer leads 3 can be grasped on the scale and the number of the outer leads 3 can be easily counted, so that the predetermined outer leads 3 can be easily selected. it can. As a result, QF
It is possible to improve work efficiency during failure analysis of a semiconductor device that employs the P structure.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with embodiments in which the present invention is applied to a semiconductor device adopting a QFP structure.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals and their repeated description will be omitted.

(Embodiment 1) FIG. 1 (plan view) shows a schematic structure of a semiconductor device having a QFP structure which is Embodiment 1 of the present invention.

As shown in FIG. 1, in a semiconductor device having a QFP structure, a semiconductor pellet 2 is sealed with a sealing body 1 having a rectangular plane. The sealing body 1 is formed of, for example, an epoxy resin and is molded by a transfer molding method. The semiconductor pellet 2 mounts a circuit system such as a memory circuit, a logic circuit, or a mixed circuit thereof.

On the outside of each of the four sides of the sealing body 1, a large number of outer leads 3 are arranged along the respective sides. The outer lead 3 is electrically connected to an external terminal (bonding pad) of the semiconductor pellet 2 via an inner lead sealed with the sealing body 1 and a bonding wire.

After molding the sealing body 1, the outer leads 3 are
It is cut from the lead frame and formed into, for example, a gull wing shape. The lead frame is, for example, Fe-Ni.
(For example, Ni content is 42 or 50 [%]) alloy, Cu alloy or the like.

Although not limited to this, the semiconductor device having the QFP structure has a multi-pin structure in which 384 outer leads 3 are arranged, and 96 outer leads 3 are arranged on each side of the sealing body 1. . In other words, the semiconductor device having the QFP structure has a four-direction lead array structure in which the lead array 4 including 96 outer leads 3 is arranged on each side of the sealing body 1.

The lead array 4 is provided with a scale for counting the number of outer leads 3. The scale is composed of outer leads 3A that are colored for each predetermined number of leads. The outer leads 3A are formed, for example, every five leads from the first stage of the lead array 4. The outer leads 3A are colored after the molding of the sealing body 1. The outer leads 3A may be colored in the lead frame forming step.

In this way, by constructing a scale for counting the number of outer leads 3 by the outer leads 3A colored for each predetermined number of leads, the number of outer leads 3 can be grasped by the scale (outer leads 3A). Since the number of the outer leads 3 can be easily counted, the predetermined outer leads 3 can be easily selected. As a result, it is possible to improve work efficiency during failure analysis of a semiconductor device that employs the QFP structure.

(Embodiment 2) FIG. 2 (plan view of a main portion) shows a schematic structure of a semiconductor device having a QFP structure which is Embodiment 2 of the present invention.

As shown in FIG. 2, in the semiconductor device having the QFP structure, the semiconductor pellet 2 is sealed with the sealing body 1 having a rectangular plane. This QFP structure semiconductor device has a multi-pin structure in which 384 outer leads 3 are arrayed, as in the case of the above-described first embodiment, and each side of the sealing body 1 has 96 parts.
Arrange the outer leads 3 of the book. In other words, the semiconductor device having the QFP structure has a four-direction lead array structure in which the lead array 4 including 96 outer leads 3 is arranged on each side of the sealing body 1.

The lead array 4 is provided with a scale for counting the number of outer leads 3. This graduation is composed of outer leads 3B that are formed wider than the lead width (width in the lead arrangement direction) of the other outer leads 3 for each predetermined number of leads. The outer leads 3B are formed, for example, every five leads from the first stage of the lead array 4.

As described above, by constructing a scale for counting the number of outer leads 3 with the outer leads 3B formed wider than the lead width of the other outer leads 3 for each predetermined number of leads, the scale ( Outer lead 3
You can check the number of outer leads 3 in B),
Since the number of outer leads 3 can be easily counted, a predetermined outer lead 3 can be easily selected. As a result, it is possible to improve work efficiency during failure analysis of a semiconductor device that employs the QFP structure.

Further, by arranging the outer leads 3B formed wider than the lead widths of the other outer leads 3 for each predetermined number of leads, after mounting the semiconductor device having the QFP structure on the mounting substrate, the mounting substrate is mounted. Since the stress generated by the deformation, warpage, etc. can be relieved, the outer lead 3 can be prevented from peeling off after mounting.

(Embodiment 3) FIG. 3 (plan view of a principal portion) shows a schematic structure of a semiconductor device having a QFP structure which is Embodiment 3 of the present invention.

As shown in FIG. 3, in the semiconductor device having the QFP structure, the semiconductor pellet 2 is sealed by the sealing body 1 having a rectangular plane. This QFP structure semiconductor device has a multi-pin structure in which 384 outer leads 3 are arrayed, as in the case of the above-described first embodiment, and each side of the sealing body 1 has 96 parts.
Arrange the outer leads 3 of the book. In other words, the semiconductor device having the QFP structure has a four-direction lead array structure in which the lead array 4 including 96 outer leads 3 is arranged on each side of the sealing body 1.

A scale for counting the number of outer leads 3 is formed on one surface of the sealing body 1. This graduation is composed of marks 5 formed in the lead arrangement 4 for each predetermined number of leads. The mark 5 is, for example, the sealing body 1.
The surface is formed of paint marks or the surface of the sealing body 1 is uneven. The marks 5 are formed, for example, every five lines counting from the first stage of the lead array 4. The mark 5 formed by the paint mark is formed on the one surface of the sealing body 1 after the molding of the sealing body 1 in a marking step of displaying a product type, a manufacturer name, and the like. In addition, the mark 5 formed by unevenness is
It is formed together with the molding of the sealing body 1 by forming irregularities in a mold for molding the sealing body 1.

As described above, by forming a scale for counting the number of outer leads 3 by the marks 5 formed on the one surface of the sealing body 1 for each predetermined number of leads, the outer leads can be formed by the scale (mark 5). You can grasp the number of 3
Since the number of outer leads 3 can be easily counted, a predetermined outer lead 3 can be easily selected. As a result, it is possible to improve work efficiency during failure analysis of a semiconductor device that employs the QFP structure.

Further, since the mark 5 formed of the paint mark is formed in the marking process, it is possible to suppress an increase in the number of manufacturing processes due to the formation of the mark 5.

Further, since the mark 5 formed by the unevenness is formed in the molding process of the sealing body 1, it is possible to suppress an increase in the manufacturing process due to the formation of the mark 5.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor device in which a semiconductor pellet is hermetically sealed with a sealing body made of ceramics.

Further, the present invention can be applied to a semiconductor device adopting a two-way lead arrangement structure.

Further, the present invention can be applied to a semiconductor device adopting a one-way lead arrangement structure.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to improve the work efficiency during failure analysis of a semiconductor device in which a large number of outer leads are arranged along one side of the sealing body.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device adopting a QFP structure which is Embodiment 1 of the present invention.

FIG. 2 is a plan view of essential parts showing a schematic configuration of a semiconductor device adopting a QFP structure which is Embodiment 2 of the present invention.

FIG. 3 is a plan view of a principal part showing a schematic configuration of a semiconductor device adopting a QFP structure which is Embodiment 3 of the present invention.

[Explanation of symbols]

1 ... Sealing body, 2 ... Semiconductor pellet, 3 ... Outer lead, 4 ... Lead arrangement, 5 ... Mark.

Claims (5)

[Claims] 1. A semiconductor device in which a large number of outer leads are arranged along one side of a sealing body, wherein a scale for counting the number of the outer leads is formed for each predetermined number of leads. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the scale is formed on an outer lead or a sealing body. 3. The semiconductor device according to claim 2, wherein the scale is composed of a colored outer lead. 4. The semiconductor device according to claim 2, wherein the scale is composed of an outer lead formed wider than a lead width of another outer lead. 5. The semiconductor device according to claim 2, wherein the scale is composed of a mark formed on one surface of the sealing body.