JPH0831929A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method, of a semiconductor device, which increases a wiring density and which reduces the chip size. CONSTITUTION:A connecting hole 5 larger than that of the part of a lower-layer interconnection 3 as a substratum is formed in an interlayer insulating film 4. A slide-down part 9 in which the interlayer insulating film has been removed is formed at the inside part of the lower-layer interconnection 3 inside the connecting hole 5. A plasma oxide film 10 is grown in the slide-down part 9. The plasma oxide film is left only in the slide-down part 9, and a buried part 11 is formed. Then, an upper-layer interconnection 6 is connected to the lower-layer interconnection 3 via the connecting hole 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to wirings of different layers,
That is, the present invention relates to a method for manufacturing a semiconductor device in which the lower layer wiring and the upper layer wiring are connected.

[0002]

2. Description of the Related Art In general, with the progress of steppers, especially the dramatic improvement in resolution, devices having a design rule of submicron to half micron, and recently, quarter micron have been developed. However, the alignment accuracy with respect to each layer and the miniaturization of the above-mentioned pattern have not made much progress, and are, so to speak, capped. Therefore, it is necessary to secure an alignment margin (overlap) of about 0.3 μm with respect to the underlying pattern, which is a bottleneck in determining a design rule.

A conventional method of manufacturing a semiconductor device for connecting different layers of wiring will be described below. FIG. 3 is a cross-sectional view in order of the steps of a conventional method for manufacturing a semiconductor device, and FIG. 4 is a mask layout diagram of the conventional semiconductor device. In FIG. 3, as components, 1 is a semiconductor substrate, 2 is an oxide film,
3 is a lower layer wiring, 4 is an interlayer insulating film, 5 is a connection hole, 6 is an upper layer wiring, and in FIG. 4, 7 is a lower layer wiring-connection hole overlap, and 8 is a lower layer wiring separation.

A method of manufacturing a semiconductor device including the above components and a mask layout diagram will be described. First, as shown in FIG. 3A, an oxide film 2 for insulatingly separating an element such as a transistor from a wiring layer is formed on a semiconductor substrate 1.
After forming, the lower layer wiring 3 is formed by the usual lithography technique and etching technique. Next, as shown in FIG. 3B, after forming an interlayer insulating film 4 for further insulating the upper layer wiring, only the portion of the lower layer wiring 3 which is desired to be electrically connected to the upper layer wiring is normally formed. The inter-layer insulating film 4 is opened by the lithography technique and the etching technique described above to form the connection hole 5. Next, as shown in FIG. 3C, an upper layer wiring 6 is provided so as to fill the connection hole 5, and a pattern is formed by a usual lithography technique and etching technique. Here, FIG.
As shown in FIG. 3, the lower layer wiring 5 for forming the connection hole 5 is formed in consideration of the mask misalignment in the lithography process.
In order to secure the connection hole overlap 7, the size is larger than the portion without the connection hole 5.

[0005]

By the way, with the miniaturization of the design rule, the line width of wiring, the spacing, and the size of the connection hole have been reduced, but the alignment margin due to the alignment accuracy of the stepper has been improved. Not not. That is, since the lower layer wiring-connection hole overlap 7 shown in FIG. 4 cannot be reduced, the chip size can be reduced only by the reduction of the lower layer wiring separation 8. If the lower layer wiring-connection hole overlap 7 is made smaller than the alignment margin of the present device, the connection hole 5 will be formed off the lower layer wiring 3, so that the wiring step coverage in the connection hole 5 is deteriorated. However, problems in terms of initial characteristics and reliability such as an increase in electrical resistance or disconnection occur.

The present invention solves the above-mentioned conventional problems, and is a method of manufacturing a semiconductor device in which a connection hole having a good shape can be formed without ensuring an overlap as an alignment margin with an underlying pattern. The purpose is to provide.

[0007]

In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises embedding a step-out portion generated by opening a connection hole larger than an underlying wiring with an insulating film. It has a feature.

[0008]

According to this method, since it is not necessary to secure the overlap as the alignment margin with the underlying pattern, the wiring density is increased, the chip size can be reduced, and the connection hole does not step over the underlying pattern. A good shape can be stably formed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view in order of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a mask layout diagram of the semiconductor device according to the embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is an oxide film, 3 is a lower layer wiring, 4 is an interlayer insulating film, 5 is a connection hole,
Reference numeral 6 is an upper layer wiring, which are the same as those described in the above-mentioned conventional technique. Reference numeral 9 is a stepped-out portion, 10 is a plasma oxide film, and 11 is a buried portion.

A method of manufacturing a semiconductor device including the above components will be described. First, as shown in FIG. 1A, after an oxide film 2 for insulatingly separating an element such as a transistor from a wiring layer is formed on a semiconductor substrate 1, a lower wiring 3 is formed by a usual lithography technique and etching technique. To do. Next, as shown in FIG. 1B, after forming an interlayer insulating film 4 for further insulating the upper layer wiring, only a portion of the lower layer wiring 3 which is to be electrically connected to the upper layer wiring,
The interlayer insulating film 4 is opened by the usual lithography technique and etching technique, and the connection hole 5 is formed. At this time, the feature of the present embodiment is that the contact hole 5 is made larger than the size of the underlying lower layer wiring 3, and the stepped-out portion 9 where the interlayer insulating film 4 is partially or completely removed is formed on the side portion of the lower layer wiring 3. Form.
Then, the dimension measurement of the stepped-out portion 9 is performed. Next, as shown in FIG. 1C, a plasma oxide film 10 having a film thickness calculated from the dimensions of the step-off portion 9 is grown on the entire surface.
Next, as shown in FIG. 1D, the entire surface is etched (doped sputter etching) in an atmosphere of Ar gas doped with CHF ₃ gas, and only the stepped-out portion 9 is exposed to the plasma oxide film 1.
The embedded portion 11 is formed while leaving 0. Since the bottom dimension of the buried portion 11 depends on the film thickness of the plasma oxide film 10 grown on the entire surface, the dimension of the stepped-out portion 9 is measured to determine the film thickness of the plasma oxide film 10 to be grown. To do. Next, the upper wiring 6 is embedded so as to fill the connection hole 5.
Is provided, and a pattern is formed by the usual lithography technique and etching technique.

As described above, according to the present embodiment, it is not necessary to secure the lower layer wiring-connection hole overlap as shown in FIG. 2, and as a result, the wiring density can be made extremely high, and the chip can be made accordingly. The size can be reduced.

Although a method of manufacturing a semiconductor device having a connection hole between multi-layer wirings has been described here, the same applies to a method of manufacturing a semiconductor device having a connection hole for connecting a gate electrode and a wiring.

[0013]

As is apparent from the above description of the embodiment, the present invention fills the misalignment margin of the underlying pattern with the insulating film by forming the connecting portion larger than the underlying pattern, which is generated by opening the connecting hole. This is an excellent method of manufacturing a semiconductor device, which can eliminate the overlap dimension that is secured as a result, increase the wiring density as a result, and can reduce the chip size.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in order of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Figure 2] Same mask layout diagram

3A to 3C are cross-sectional views in order of steps of a conventional method for manufacturing a semiconductor device.

[Fig. 4] Same mask layout diagram

[Explanation of symbols]

 1 Semiconductor Substrate 2 Oxide Film 3 Lower Layer Wiring 4 Interlayer Insulating Film 5 Connection Hole 6 Upper Layer Wiring 8 Lower Layer Wiring Separation 9 Step Out Part 10 Plasma Oxide Film 11 Embedded Section

Claims (2)

[Claims] 1. A semiconductor device having multilayer wiring,
The step of forming a lower layer wiring on a semiconductor substrate, the step of growing an interlayer insulating film for electrical insulation from other layers, and the step of forming a connection hole for establishing electrical connection with the lower layer wiring as a base A step of etching the interlayer insulating film larger than the size of the lower layer wiring to open a hole, and growing a portion of the insulating film on the side of the lower layer wiring in the connection hole where the interlayer insulating film has been removed to grow the entire surface. A method of manufacturing a semiconductor device, which includes a step of embedding by an etching method and a step of forming an upper wiring. 2. A step of forming a gate electrode film on a semiconductor substrate, a step of growing an interlayer insulating film for electrical insulation from other layers, and a step of electrically connecting with the gate electrode film. A step of etching the inter-layer insulating film larger than the size of the gate electrode portion serving as a base to open the connection hole; and removing the inter-layer insulating film at a side portion of the gate electrode film in the connection hole. A method of manufacturing a semiconductor device, comprising: a step of filling an insulating film by a method of growing an insulating film and etching the entire surface; and a step of forming wiring for connecting each element.