JPH08316949A - Block synchronization processing circuit - Google Patents

Abstract

PURPOSE: To prevent the block resynchronization processing from being carelessly started by the deviation of the detection timing of Bic especially during the forward protection operation by improving the noise tolerance for clock reproducing to surely synchronize a block. CONSTITUTION: An inputted data signal S1 is successively stored in a shift register 3, and the data signal having the same length as a Bic pattern is always recorded. A Bic detection timing counter 9 outputs a Bic detection timing signal S3 to a comparison circuit 7 based on the counted value of an N3 counter and the detection width from a detection width selection circuit 11. The circuit 7 compares data stored in the register 3 and a Bic pattern storage part 5 with each other and outputs a Bic detection signal S4 at the time of coincidence. The signal S4 is sent to a forward/backward protection circuit 15 and a counter 9. The counter 9 is reset based on the signal S4. The circuit 15 performs the forward/backward protection operation based on the signal S4 and outputs a block synchronizing signal in the case of settlement of synchronism but outputs a signal in the low level in the case of unsettlement of synchronism.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block synchronization processing circuit, and more particularly to serially transferring data using a clock signal and a data signal, using a block identification code signal (BIC signal) for synchronization detection, and protecting the front side. The present invention relates to a block synchronization processing circuit that performs block synchronization determination using a circuit and a rear protection circuit.

[0002]

2. Description of the Related Art Conventionally, there is known a communication system for serially transferring data using a block signal and a data signal. An example of such a communication system is F
M multiplex broadcasting is mentioned. In FM multiplex broadcasting, data is transmitted by being multiplexed with FM broadcasting (main broadcasting). In an FM multiplex broadcast receiver, data and clock are reproduced from the multiplexed signals and processed. The data is transmitted in units of packets for each block. Each of the blocks has a predetermined block identification code (hereinafter referred to as "BIC"), and in the FM multiplex broadcast receiver, the BIC is determined from the received data string.
The block division is detected by extracting the pattern, and the reception block synchronization is determined by detecting the BIC pattern a plurality of times (the number of times of forward protection / the number of times of backward protection). In FM multiplex broadcasting, four types of patterns BIC1 to BIC4 are used.

The packet unit is composed of information (data (block) and parity) and BIC. Therefore, if the number of bits of information is N1, the number of bits of BIC is N2, and the number of bits of one packet is N3, the relationship of N3 = N1 + N2 is established. In FM multiplex broadcasting, for example, the number of bits of information N1 = 272, the number of bits of BIC N3 = 16, and the number of bits of one packet N3 = 288.

In the FM multiplex broadcast receiver, block synchronization is processed by a block synchronization processing circuit. The block synchronization processing circuit includes a BIC detection circuit. BI
The C detection circuit includes a comparison circuit (comparison circuit corresponding to each of BIC patterns 1 to 4) for comparing the received data string with the BIC pattern, and an N3 (eg, 288) -bit output circuit for detecting the BIC pattern. It consists of an interval cyclic counter. In the conventional detection circuit, the received data string is compared with the BIC pattern according to the detection timing of the 1-bit width output at intervals of N3 bits in the cyclic counter, and the BIC pattern of the BIC is determined by the comparison result. Detection is determined,
It is determined that the BIC is not detected due to the mismatch.

BIC detection is performed for each reception clock in the initial state (before the block protection state and before the backward protection process). Once the BIC pattern is detected and the backward protection operation is started, the cyclic counter is initialized, and in the subsequent processing, the BIC generated from the cyclic counter is detected as shown in FIG. At each timing (b), the stored BIC pattern is compared with the received data (a).

The received BIC pattern may be partially garbled due to noise. As a countermeasure against these noises, conventionally, a process has been performed in which an allowable error number of BIC patterns is set in a circuit and it is determined that the patterns are the same even if there is a difference in the patterns within the allowable error number.
For example, the received data (a) as shown in FIG.
When the BIC pattern (b) stored in the circuit is compared with the BIC pattern (b) stored in the circuit, in order to determine that the two are the same, it is not necessary for the corresponding data to be completely the same, and the error allowable number Even if there is a difference in the following data, both are judged to be the same.

[0007]

However, in the conventional block synchronization processing circuit, when noise such as multipath / fading is added to the received signal, or noise such as static electricity / line noise of power source enters the receiver. In some cases, the reproduction of the data and clock from the multiplexed signal may not be performed normally.

That is, as shown in FIG. 8, the number of clocks of the data DATA2 received is increased / decreased by noise, and the count of the cyclic counter and the timing of the BIC signal in the received data are deviated by even one bit. Then, as shown in FIG. 6, the position of comparison between the received data (a) and the BIC pattern (b) recorded in the circuit shifts, and even if the contents of both are the same, different patterns are obtained. It is determined that there is. As a result of not detecting the BIC signal in this way, there is a case where the synchronization determination is not performed during the forward protection operation, the block synchronization is once released, and the synchronization detection processing (rearward protection) is performed again. Therefore, when data shift due to noise occurs in the conventional block detection circuit, the number of forward protections for block synchronization from the time the shifts occur until the block synchronization is released, and the number of backward protections for establishing block synchronization thereafter. This caused a state in which blocks for the total number of times could not be received. This is because during forward protection, data is descrambled in a bit-shifted state, so completely different data is reproduced, and during rearward protection, data acquisition is not performed.

This phenomenon will be described with reference to FIG. In FIG. 4, (a) is received data, (b) is a comparison timing of BIC patterns stored in the circuit, and (c) is a signal indicating that the received BIC signal and the BIC detection timing signal match. , (D) is a block synchronization signal indicating that block synchronization is established, and (e) is a counter reset signal for a cyclic counter for adjusting the output timing of the BIC detection timing signal.

Referring to the figure, the BIC signal of the data (a) received at the time t1 and the BIC pattern (b) coincide with each other, whereby the BIC signal is detected (c). Further, in this state, the block synchronization signal (d) is High.
Assume level. At time t2, time t1
The BIC signal is detected similarly to the above. From time t2 to t
Since the received data (a) is deviated by the noise generated during the period 3, the BI received at the time t3 is received.
A mismatch occurs between the C signal (a) and the BIC detection timing signal (b), so that the BIC signal is not detected at time t3 (c). In response to the fact that the BIC signal is not detected, the circuit performs the forward protection operation from time t3. After that, BIC signal of received data and B
It remains displaced from the IC detection timing signal. Since the BIC signal is not detected a plurality of times during the forward protection operation, the block synchronization signal becomes Low at time t4.
It is a level. From time t4, the backward protection operation for establishing block synchronization is performed. In the backward protection operation, it is determined that the synchronization is established at time t5 based on the detection of the BIC signal of the preset number of times (the backward protection number). In the example of FIG. 4, the data is not reproduced from time t3 to time t5.

The present invention has been made in order to solve the above problems, and improves the noise resistance in the clock reproduction to ensure the block synchronization,
In particular, it is an object of the present invention to provide a block synchronization processing circuit that does not inadvertently enter the block resynchronization processing due to a shift in the BIC detection timing during the forward protection operation.

[0012]

According to a first aspect of the present invention, there is provided a block synchronization processing circuit comprising a storage means for storing an identification code formed of a plurality of continuous data and a plurality of continuously input data. Detecting means for detecting continuous data in the data sequence that is more than the number of data forming the identification code, and identification means for identifying the data corresponding to the stored identification code from the detected data. It is equipped with.

A block synchronization processing circuit according to a second aspect is the block synchronization processing circuit according to the first aspect,
Output means for outputting a data detection timing signal based on the identification output of the identification means is further provided, and the detection means detects the data based on the detection timing signal. The block synchronization processing circuit described.

According to another aspect of the block synchronization processing circuit of the present invention, a front protection circuit for performing a front protection operation, a rear protection circuit for performing a rear protection operation, and a memory for storing an identification code composed of a plurality of continuous data. And a continuous data consisting of a first data number larger than the number of data forming the identification code, from the data string consisting of a plurality of data continuously input during the forward protection operation. A second detection unit that is smaller than the first data number and is equal to or larger than the number of data items forming the identification code is selected from the first detection unit and the data string formed of a plurality of data that are continuously input during the backward protection operation. Second detection means for detecting continuous data consisting of the number of data, and identification means for identifying data corresponding to the stored identification code from the detected data are provided.

[0015]

A block synchronization processing circuit according to a first aspect of the present invention stores an identification code composed of a plurality of continuous data,
Detects more continuous data than the number of data forming the identification code from the data string composed of a plurality of continuously input data, and corresponds to the stored identification code from the detected data. Identify the data.

According to a second aspect of the present invention, in addition to the function of the block synchronous processing circuit according to the first aspect, the block synchronous processing circuit outputs a data detection timing signal based on the identification output of the identification means, and the detection timing signal. Detect data based on.

A block synchronization processing circuit according to a third aspect of the present invention stores an identification code composed of a plurality of continuous data, and stores a data string composed of a plurality of data continuously input during a forward protection operation. The continuous data having the first number of data larger than the number of data forming the identification code is detected from among the data, and the first of the data strings composed of a plurality of data continuously input during the backward protection operation is detected. Continuous data having a second data number smaller than the data number of 1 and not less than the data number forming the identification code is detected, and the data corresponding to the stored identification code is identified from the detected data.

[0018]

1 is a block diagram showing the structure of a block synchronization processing circuit according to an embodiment of the present invention.

Referring to the figure, the block synchronization processing circuit is based on a demodulation circuit 1 for demodulating a received signal (RFIN) and a data signal (S1) and a clock signal (S2) output by the demodulation circuit 1. The shift register 3 that temporarily stores the contents of the data signal (S1), the BIC pattern storage unit 5 that stores a plurality of BIC patterns, the BIC detection timing counter 9 that outputs the BIC detection timing signal, and the BIC detection timing counter 9 A comparison circuit 7 that compares the contents of the shift register 3 with the BIC pattern of the BIC pattern storage unit 5 based on the BIC detection timing signal, and a forward protection / rear protection process based on the output (S4) of the comparison circuit 7. / Rear protection circuit 15
, A detection width selection circuit 11 for setting the output width of the BIC detection timing signal, and an allowable error number selection circuit 13 for selecting an allowable error number in each of the front protection operation / rear protection operation.
And the BIC output by the BIC detection timing counter 9
A data signal (S1) and a clock signal (S) output by the demodulation circuit 1 based on the detection timing signal (S3).
Descramble circuit 1 for descramble 2)
And 7.

The shift register 3 stores the received data having the same number of bits as the number of bits of the BIC pattern.

The feature of the block synchronization determination circuit in this embodiment is that the detection width of the BIC is variable (± M bits). That is, in FIG.
A BIC pattern stored in the pattern storage unit 5,
Assuming that the received data signal 45 is compared, in the conventional technique, only the data having the same length as the data included in the BIC pattern storage unit 5 (FIG. 2C) is the comparison target. However, in the present embodiment, the detection width has a width of ± M bits, and the data included in the detection width is the object of comparison. That is, the detection width M
If = 1, in addition to the data of (c), the data at the positions of (b) and (d) are to be compared, and if the detection width M = 2, it is added to the data of (c) (a). , (B),
The data at the positions of (d) and (e) are to be compared. The detection width (± M bits) is set in consideration of the correlation for each BIC pattern, the autocorrelation when a bit shift occurs, and the allowable number of errors.

For example, when the correlation of the BIC pattern (including the bit shift) is m1 bit (for example, 3 bits) and the allowable error number is m2 bit (for example, 2 bits), the detection width is ± m3 bit (m3 = m1). -M2: Set as a width of, for example, ± 1 bit. The detection width M
Can be set within the range of M ≦ m3.

Further, the detection width is set independently during the backward protection process and the forward protection process of block synchronization. The detection width MB during the rear protection operation and the detection width MF during the front protection operation are input to the detection width selection circuit 11 shown in FIG. 1, and either one of them is input to the BIC detection timing counter 9 based on the block synchronization signal. That is, in the state where the block synchronization is established, the block synchronization signal is at the High level and the forward protection operation is performed, so the detection width selection circuit 11 outputs the detection width of the MF to the BIC detection timing counter 9. On the other hand, in the state where the block synchronization is lost, the block synchronization signal is at the Low level, and the backward protection operation is performed, so the detection width selection circuit 11 is
The detection width of is output to the BIC detection timing counter 9. Normally, MB ≦ M in order to prevent erroneous synchronization of block synchronization and prevent out-of-synchronization which is composed of correct synchronization of block synchronization.
The value of F is set. It is desirable that the value of MB be 1 as in the conventional case in order to prevent erroneous block synchronization.

As in the conventional case, different allowable values for the BIC signal error are used during the forward protection operation and the backward protection operation. Each allowable error number is input to the allowable error number selection circuit 13, and one of them is selected by the block synchronization signal and input to the comparison circuit 7.

Next, the operation of the block synchronization processing circuit in this embodiment will be described with reference to FIG.

The received signal (RFIN) is demodulated by the demodulation circuit 1
Demodulated by. The demodulation circuit 1 outputs a data signal S1 (SDATA) and a clock signal S2 (SCLK) of the received signal (RFIN), each of which is input to the shift register 3. The input data signal S1 is sequentially stored in the shift register 3, and a data signal having the same length as the BIC pattern is always recorded. The BIC detection timing counter 9 outputs N3 based on the clock signal.
Count the number of clocks. Further, the BIC detection timing counter 9 sends a B count to the comparison circuit 7 based on the count of N3 and the detection width input from the detection width selection circuit 11.
The IC detection timing signal S3 (BICEN) is output. The comparison circuit 7 compares the data recorded in the shift register 3 based on the BIC detection timing signal S3 with B
The data stored in the IC pattern storage unit 5 is compared, and if the comparison results are in agreement, the BIC detection signal S4 (BICEX) is output. At this time, the data in the shift register 3 and the data in the BIC pattern storage unit 5 do not have to completely match, and if the error is within the number of bits within the allowable BIC error number input from the allowable error number selection circuit 13, the error is detected. The data are determined to be the same. The BIC detection signal S4 is sent to the front / rear protection circuit 15 and the BIC detection timing counter 9. BIC
The detection timing counter 9 resets the counter based on the input BIC detection signal S4. The front / rear protection circuit 15 performs a front / rear protection operation based on the BIC detection signal S4, outputs a block synchronization signal (High level signal) when synchronization is established, and outputs Low level when synchronization is not established. Output a signal.

FIG. 3 is a timing chart showing the processing in the block synchronization processing circuit in this embodiment.

Referring to the drawing, (a) is the received data signal, (b) is the position where the BIC is detected based on the BIC detection timing signal output from the BIC detection timing counter 9, and (c) is the BIC detection. The signal S4 is shown.

In the BIC detection timing counter 9, the value of N3 is counted based on the clock signal. BI
The C detection timing counter 9 outputs a BIC detection timing signal with a detection width of M before and after each count of the value N3. Therefore, the BIC is detected with the detection width ± M (b). The BIC corresponding to the data signal (a) received while the BIC detection timing signal is being output.
If it is determined that there is a signal, the comparison circuit 7 outputs B
The IC detection signal S4 is output (c). The value of the counter of the BIC detection timing counter 9 is reset based on the BIC detection signal S4, and the count of the value N3 is newly started from the reset time.

As a result, even if a deviation occurs in the received data signal (a) due to noise generated between times t2 and t3, if the deviation is within the detection width M, the BIC
Since the signal is detected and the count value of the BIC detection timing counter 9 is also reset based on the detected signal, the next BIC detection timing signal comes to coincide with the BIC signal interval of the received data signal. Therefore, it is possible to prevent the block synchronization from being accidentally lost due to the shift of the BIC detection timing during the forward protection operation due to noise or the like.

In the present embodiment, the data is not reproduced even if the data signal is deviated due to noise.
It is possible to prevent the inconvenience that the data is not reproduced for a long time as in the conventional technique, because only the block in which the shift occurs occurs.

In this embodiment, the BIC pattern (BI
C1 to C4) are all detected with the same weighting, but since there is a certain law in the arrangement of BIC patterns transmitted in FM multiplex broadcasting, BICs to be detected are
By limiting the pattern, it is possible to further reduce the false detection of BIC.

[0033]

According to the block synchronization processing circuit of the present invention, since the data corresponding to the identification code is identified from the continuous data that is larger than the number of pieces of data forming the identification code,
It is possible to prevent non-detection of the identification code due to data shift, and block synchronization can be reliably performed.

In addition to the effect of the circuit according to the first aspect, the block synchronization processing circuit according to the second aspect outputs the detection timing signal of the detection means based on the identification output of the identification means. The signal corresponding to can be identified.

A block synchronization processing circuit according to a third aspect of the present invention detects continuous data having a first number of data larger than the number of data forming the identification code during the forward protection operation, and detects the first data during the backward protection operation. Since continuous data having a second number of data smaller than the number and not less than the number of data forming the identification code is detected, it is possible to more appropriately determine the synchronization establishment / out-of-sync.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a block synchronization processing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a BIC signal detection operation in a block synchronization processing circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart showing a BIC signal detection process in the block synchronization processing circuit according to the embodiment of the present invention.

FIG. 4 is a timing chart for explaining detection of a BIC signal performed in a conventional block synchronization processing circuit and a process associated therewith.

FIG. 5 is a diagram for explaining a BIC signal determination method performed in a conventional block synchronization processing circuit.

FIG. 6 is a diagram for explaining a problem of a conventional block synchronization processing circuit.

FIG. 7 is a diagram for explaining a BIC detection timing of a conventional block synchronization processing circuit.

FIG. 8 is a diagram for explaining a problem when a data shift occurs due to noise in a conventional block synchronization processing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 demodulation circuit 3 shift register 5 BIC pattern storage unit 7 comparison circuit 9 BIC detection timing counter 11 detection width selection circuit 13 allowable error number selection circuit 15 forward / backward protection circuit 17 descramble circuit 45 input data string

Claims (3)

[Claims] 1. A storage means for storing an identification code composed of a plurality of continuous data, and a number of data forming the identification code from a data string composed of a plurality of continuously input data. A block synchronization processing circuit comprising: detection means for detecting more continuous data than that; and identification means for identifying data corresponding to the stored identification code from the detected data. 2. The output means for outputting a data detection timing signal based on the identification output of the identification means, wherein the detection means detects the data based on the detection timing signal. Block synchronization processing circuit. 3. A front protection circuit for performing a front protection operation, a rear protection circuit for performing a rear protection operation, a storage means for storing an identification code composed of a plurality of continuous data, and a continuous protection circuit during the front protection operation. First detection means for detecting continuous data having a first number of data larger than the number of pieces of data forming the identification code from a data string formed of a plurality of pieces of data input as data; During the operation, a continuous data consisting of a second data number smaller than the first data number and equal to or more than the data number forming the identification code is selected from a data string formed of a plurality of data that are continuously input. A block synchronization processing circuit, comprising: a second detection unit that detects the data, and an identification unit that identifies the data corresponding to the stored identification code from the detected data.