JPH08316837A - Double integration system a/d conversion method and its device - Google Patents

Abstract

PURPOSE: To realize the double integration system A/D conversion method and its device in which dispersion in the A/D conversion time-due to a level of an input analog signal is less. CONSTITUTION: A charging section 3 charges a capacitor 2 with a 1st current proportional to an input analog signal only for a prescribed time. A reverse charging section 4 starts reverse charging of the capacitor 2 by a 2nd current being a prescribed current without awaiting the end of charging of the charging section 3. When the voltage of the capacitor 2 restores to an original voltage by the reverse charging by the 2nd current during the charging by the 1st current, a 2nd integral period signal generating section 5 uses the reverse charging section 4 to interrupt tentatively reverse charging. Then the reverse charging is restarted synchronously with a 2nd integration start discrimination timing signal generated for a prescribed period on the condition that the capacitor 2 is again charged. The time for 2nd integration is measured by a counter 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to AD conversion technology,
In particular, the present invention relates to a double integration type AD conversion method and apparatus.

[0002]

2. Description of the Related Art Generally, three types of AD conversion methods are known: a low speed / high accuracy counting method, a medium speed / medium accuracy successive approximation method, and a high speed / low accuracy parallel comparison method. Since high accuracy is required for AD conversion in an active distance measuring device used for automatic focusing, etc., a low-speed and high-accuracy counting method has been favored.

A typical example of a low-speed, high-precision counting method is called a double integration method. In the conventional AD conversion of the double integration method, the capacitor is charged with a current proportional to the value of the input analog signal for a certain period of time, and then reversely charged with a reference current having a polarity opposite to that of the input signal, and the voltage of the capacitor is restored to the original value. The counter charges the reverse charge time required to return to the voltage. Here, charging the capacitor with a current proportional to the value of the input analog signal is called "first integration", and reverse charging with a reference current of opposite polarity is called "inverse integration" or "second integration". There is.

[0004]

For example, when the clock for counting is 64 KHz, the maximum time of the second integration is 4 ms {(1 / 64K
Hz) × 2 ⁸ }. Therefore, if the first integration time is also set to 4 ms, it takes 8 ms to AD-convert the maximum input analog signal. On the other hand, in the case of a minute input analog signal, the time of the second integration is very short, so A
The D conversion time is 4 ms, which is almost equal to the first integration time.
That is, the conventional method has a problem that the AD conversion time greatly varies depending on the size of the input analog signal, and the usability is not good. Note that the method of increasing the reference current used for the second integration to shorten the maximum value of the second integration time causes an increase in error and requires a large reference current to flow, which causes difficulty in circuit design.

Therefore, an object of the present invention is to provide a double integration type AD conversion method and apparatus in which variations in AD conversion time due to the size of an input analog signal are suppressed.

[0006]

In order to achieve the above object, the present invention starts the second integration without waiting for the end of the first integration. As a result, the maximum end time of the second integration is advanced, the AD conversion time at the time of the maximum input analog signal can be shortened, and the variation in the AD conversion time due to the size of the input analog signal can be reduced.

However, depending on the timing of starting the second integration and the size of the input analog signal, the voltage of the capacitor may return to the original voltage due to the reverse charging by the second current during the period of the first integration. . Therefore, in such a case, the reverse charging is temporarily interrupted, and then the second integration is restarted on condition that the capacitor starts to be charged again. Therefore, the second integration may be performed intermittently, and the second integration time in that case is the cumulative time of each.

If the second integration is restarted immediately after the capacitor starts to be charged again after the second integration is interrupted, the second integration must be immediately interrupted again. When the input analog signal is very small, The interruption and resumption of the second integration frequently occur, which causes an error. Therefore, the second integration is restarted in synchronization with the second integration start determination timing signal that occurs in a predetermined cycle.

A double integration AD device for implementing the above double integration AD conversion method receives an AD conversion start signal and a clock as input, and performs a first integration over a time T from the time when the AD conversion start signal is turned on. A period signal is turned on, and a timing signal generation circuit that generates a second integration start determination timing signal every time time T / N (N is a positive integer) has elapsed from the time when the AD conversion start signal was turned on, a capacitor, During the ON period of the first integration period signal, a charging unit that charges the capacitor with a first current proportional to the value of the input analog signal, and the capacitor is in a charging state or a reverse charging state as viewed from a reference voltage. Whether or not the capacitor is in a charged state, the second integration period signal is turned on in synchronization with the second integration start determination timing signal, and the capacitor is reversely charged. A second integration period signal generation unit that turns off the second integration period signal when the state becomes a state, and a second current having a constant value and a constant value during the ON period of the second integration period signal. And a counter for counting the clock during the ON period of the second integration period signal.

Further, in a preferred embodiment of the present invention, the second integration period signal generator compares the voltage of the capacitor with a reference voltage to determine whether the capacitor is in a charged state as viewed from the reference voltage. A comparator for judging whether or not the battery is in a reverse charge state, holding a judgment signal of the comparator in synchronization with the second integration start judgment timing signal, and holding the held judgment signal by the judgment signal of the comparator. A latch that is reset at the time of switching from the charge state to the determination of the reverse charge state, and a logical product condition signal of the output signal of the latch and the determination signal of the comparator, which is held in synchronization with the clock, and the held signal Is output as the second integration period signal.

[0011]

When the AD conversion start signal is turned on, the timing signal generating circuit keeps the first signal for the time T (for example, 4 ms).
Turn on the integration period signal. As a result, the charging unit starts charging the capacitor with the first current proportional to the input analog signal. Further, when the AD conversion start signal is turned on, T / N (for example, when N = 16, 250 μ
The timing signal generation circuit generates the second integration start determination timing signal each time the time s) elapses.

The second integration period signal generator monitors by a comparator whether the capacitor is in a charged state or a reverse charged state with respect to the reference voltage, and the second integrated period is provided on the condition that the capacitor is in a charged state. Second in synchronization with the start determination timing signal
Turn on the integration period signal. That is, the second integration period signal is set by holding the judgment signal of the comparator in the latch and setting the logical product condition signal of the output signal of the latch and the judgment signal of the comparator in the flip-flop in synchronization with the clock. turn on. As a result, in parallel with the first integration, the reverse charging unit starts reverse charging of the capacitor with the second current, and the counter starts counting clocks.

Assuming that the first current generated by the charging section at the maximum input analog signal is equal to the second current of the reverse charging section, the first current and the second current cancel each other during AD conversion of the maximum input analog signal. Therefore, the voltage of the capacitor at the start of the second integration is maintained until the end of the first integration, and the voltage of the capacitor returns to the original voltage when T / N has elapsed after the end of the first integration. In this case, the second integration is continuously performed for T time.

On the other hand, when the input analog signal is small, the second current is larger than the first current, so that the capacitor returns to the original voltage during the first integration period, and the second current causes the reverse charging state. It In such a reverse charging state, the flip-flop of the second integration period signal generator is reset by the clock immediately after that, and the second integration period signal is turned off. As a result, the counting of the clock by the counter is interrupted, the second integration by the reverse charging unit is interrupted, and only the first integration is performed again. Then, when the capacitor is charged again, the flip-flop of the second integration period signal generator is set in synchronization with the second integration start determination timing signal, and the second integration period signal is turned on,
The second integration by the reverse charging unit is restarted again, and the counter also restarts counting clocks.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a double integration type AD converter according to an embodiment of the present invention comprises a timing signal generating circuit 1
, Integrating capacitor 2, charging section 3, and reverse charging section 4
A second integration period signal generator 5, an AND gate 6,
It is composed of a counter 7 and a NOR gate 8.

The timing signal generation circuit 1 receives the AD conversion start signal R and the clock CL and generates a first integration period signal and a second integration start determination timing signal. In this embodiment, the clock CL is 64 KHz, and the timing signal generation circuit 1 turns on the first integration period signal for a period of 4 ms which is a time period corresponding to 256 clocks from the time when the AD conversion start signal R is turned on. To Further, after the AD conversion start signal R is turned on, the second integration start determination timing signal is generated every time 250 μs, which is a time corresponding to 16 clocks, elapses.

Two charging units 3 and 4 are connected to the integrating capacitor 2. One is a charging unit 3 which is in charge of the first integration, and charges the capacitor 2 with a first current proportional to the input analog signal during the period when the first integration period signal is on. The other is the reverse charging unit 4 which is in charge of the second integration.
Thus, during the period in which the second integration period signal generated from the second integration period signal generator 5 is on, the capacitor 2 is reversely charged by the second current having a constant value and a polarity opposite to that of the first current. The capacitor 2 is initially set to a voltage equal to the reference voltage before the AD conversion start signal is turned on.

The second integration period signal generator 5 monitors whether the capacitor 2 is in a charged state or a reverse charged state with respect to the reference voltage Vref, and determines whether the capacitor 2 is in a charged state, the second integration start determination. The second integration period signal is turned on in synchronization with the timing signal. Further, thereafter, when the capacitor C is in the reverse charging state, the second integration period signal is immediately turned off, and when the capacitor C is in the charging state again, the second integration period is synchronized with the second integration start determination timing signal. The operation of turning on the signal is repeated.

In the present embodiment, the second integration period signal generator 5
Compares the voltage of the capacitor 2 with the reference voltage Vref,
When the voltage of the capacitor 2 is lower than the reference voltage Vref, "1" is output, and otherwise, "0" is output, and the output of the comparator 51 is synchronized with the second integration start determination timing signal. Latch 52 for holding and latch 52
Of the AND gate and the output of the comparator 51, and a D-type flip-flop 54 that holds the output of the AND gate 53 in synchronization with the clock CL. The output of the D-type flip-flop 54. Becomes the second integration period signal. This second integration period signal is applied to the reverse charging unit 4 described above.
And to one input of the AND gate 6. Note that when the AD conversion activation signal R is turned on, the latch 52 and the D-type flip-flop 54 are reset, and the second integration period signal is initialized to the off state. The latch 52 outputs the output of the comparator 51 from “1” to “0”.
Even when it changes to, it is reset to "0".

The clock CL is supplied to the other input of the AND gate 6, and the clock C is supplied while the second integration period signal supplied to one input is on.
L is passed and output to the counter 7. Counter 7
Counts the clock CL output from the AND gate 6. The counter 7 is reset to 0 when the AD conversion start signal R is turned on.

The NOR gate 8 is a gate for determining the end of AD conversion, and after the first integration period signal is turned off,
The AD conversion end signal is output at the timing when the second integration period signal is turned off. This AD conversion end signal is supplied to a circuit in the subsequent stage (not shown), and in the circuit in the subsequent stage, the count value of the counter 7 is read when the AD conversion end signal is input, and the AD conversion result is obtained.

Next, the second embodiment of the present invention configured as described above.
The operation of the multiple integration AD converter will be described.

FIG. 2 is an operation timing chart of the embodiment of FIG. 1 at the time of AD conversion of the maximum input analog signal. When the AD conversion start signal R is turned on, the first integration period signal from the timing signal generation circuit 1 is turned on,
The charging unit 3 charges the capacitor 2 with the maximum first current. 2 after turning on the AD conversion start signal R
When 50 μs has elapsed, the timing signal generation circuit 1 outputs the second integration start determination timing signal. At this timing, as shown in FIG. 2, since the voltage of the capacitor C is sufficiently lower than the reference voltage Vref, the output of the comparator 51 becomes “1” and the latch 52 latches “1”. Therefore, the output of the AND gate 53 becomes "1", and "1" is set in the D-type flip-flop 54,
The second integration period signal is turned on. As a result, the reverse charging unit 4 starts reverse charging of the capacitor 2 with the second current,
Further, since the AND gate 6 is opened, the counter 7 starts counting the clock CL.

In the present embodiment, the value of the second current of the reverse charging section 4 is set equal to the first current of the charging section 3 at the time of the maximum input analog signal. Second
The current and the voltage cancel each other out, and the voltage of the capacitor C remains constant as shown in FIG. When the first integration period signal from the timing signal generation circuit 1 is turned off 4 ms after the AD conversion start signal R is turned on, the reverse charging unit 4 is turned on.
Due to the reverse charging only, the voltage of the capacitor C rises toward the reference voltage Vref. Then, at the clock CL immediately after the voltage of the capacitor C exceeds the reference voltage Vref, the output signal of “0” of the comparator 51 causes D
Type flip-flop 54 is reset to "0", and the second
The integration period signal turns off. As a result, the reverse charging is stopped, the AND gate 6 is closed to stop the counting operation of the counter 7, and the AD conversion end signal is output from the NOR gate 8.

FIG. 3 is an operation timing chart of the embodiment of FIG. 1 when the input analog signal is relatively small.
When the AD conversion start signal R is turned on, the capacitor 2 is charged by the charging unit 3 with the first current proportional to the input analog signal, as described above. When 250 μs has elapsed after the AD conversion start signal R was turned on, the capacitor C
Voltage is lower than the reference voltage Vref, but the degree of decrease is smaller than that in the case of the maximum input analog signal in FIG. At this point, the timing signal generation circuit 1
When the second integration start determination timing signal is output from
Since the voltage of the capacitor C is lower than the reference voltage Vref,
Similarly to the above, the output of the comparator 51 becomes "1", the latch 52 latches "1", the output of the AND gate 53 becomes "1", and the D-type flip-flop 54 is set to "1". The two integration period signal is turned on. As a result, the reverse charging unit 4 starts the reverse charging of the capacitor 2 with the second current, and the counter 7 starts counting the clock CL.

As described above, the value of the second current of the reverse charging unit 4 is set equal to the first current of the charging unit 3 at the time of the maximum input analog signal. Therefore, when the input analog signal is small, the second current Is higher than the first current, and the voltage of the capacitor C gradually increases toward the original voltage as shown in FIG. Then, the voltage of the capacitor C becomes the reference voltage Vr.
At the clock CL immediately after exceeding ef, the D-type flip-flop 5 is caused by the output signal of “0” of the comparator 51.
4 is reset to "0", and the second integration period signal is turned off. As a result, the reverse charging is stopped and the counter 7
Counting operation stops. It should be noted that the latch 52 that holds “1” has the output of the comparator 51 from “1” to “0”.
It is reset at the timing of changing to and becomes "0".

When the reverse charging is stopped, the capacitor C is only charged by the charging section 3 again, so that the voltage thereof drops again as shown in FIG. Then, when the timing signal generation circuit 1 outputs the second integration start determination timing signal, the voltage of the capacitor C is changed to the reference voltage Vr.
If it is lower than ef, the output of "1" of the comparator 51 is latched by the latch 52, the output of the AND gate 53 becomes "1", and the output of the D-type flip-flop 54 becomes "1" in synchronization with the clock CL immediately after. Is set, the reverse charging by the reverse charging section 4 is restarted, and the clock C of the counter 7 is set.
L counting is restarted.

When the charging by the charging section 3 is completed 4 ms after the AD conversion start signal R is turned on by repeating the above operation, only the reverse charging by the reverse charging section 4 is performed.
Although not shown in FIG. 3, the voltage of the capacitor C rises toward the reference voltage Vref. Then, at the clock CL immediately after the voltage of the capacitor C exceeds the reference voltage Vref, due to the output signal of “0” of the comparator 51,
The D-type flip-flop 54 is reset to "0" and the second integration period signal is turned off. As a result, the reverse charging is stopped, the AND gate 6 is closed, and the counter 7 is closed.
Counting operation stops, and the AD from NOR gate 8
A conversion end signal is output.

As described above, according to the embodiment shown in FIG. 1, the time required for AD conversion of the maximum input analog signal is four.
ms + 250μs, AD depending on the size of the input signal
The variation width of the conversion time can be suppressed to 250 μs.

[0030]

As described above, according to the present invention, the time required for AD conversion of the maximum input analog signal can be shortened, and at the same time, the double integration can be performed with less variation in AD conversion time depending on the size of the input signal. There is an effect that system AD conversion can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a double integration AD converter according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the embodiment of FIG. 1 when the input analog signal has a maximum value.

FIG. 3 is an operation timing chart of the embodiment of FIG. 1 when the input analog signal is relatively small.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Timing signal generating circuit 6 ... AND gate 2 ... Capacitor 7 ... Counter 3 ... Charging part 8 ... NOR gate 4 ... Reverse charging part 5 ... Second integration period signal generating part 51 ... Comparator 52 ... Latch 53 ... AND gate 54 ... D-type flip-flop

Claims (4)

[Claims] 1. The first current required to restore the voltage of the capacitor at the reference voltage to the reference voltage when the capacitor is charged with the first current proportional to the value of the analog input signal for a certain time. Double integration method A in which the AD conversion result of the analog input signal is obtained from the reverse charging time of the capacitor by the second current having a constant value with reverse polarity.
In the D conversion method, reverse charging by the second current is started without waiting for completion of charging by the first current.
Multiple integration AD conversion method. 2. The reverse charging by the second current is interrupted every time the voltage of the capacitor returns to the reference voltage by the reverse charging by the second current during the charging by the first current, and then the voltage of the capacitor is changed. The reverse charging by the second current is restarted in synchronism with a second integration start determination timing signal generated in a predetermined cycle on the condition that is charged again when viewed from the reference voltage. Of 2
Multiple integration AD conversion method. 3. An AD conversion start signal and a clock are input, the first integration period signal is turned on for a time T from the ON time of the AD conversion start signal, and the time T / N is passed from the ON time of the AD conversion start signal. (N is a positive integer) A timing signal generation circuit that generates a second integration start determination timing signal each time a time elapses, a capacitor, and a first signal proportional to the value of the input analog signal during the ON period of the first integration period signal. A charging unit that charges the capacitor with one current, and whether the capacitor is in a charged state as viewed from a reference voltage,
The reverse charge state is monitored, and the second integration period signal is turned on in synchronization with the second integration start determination timing signal on the condition that the charge state is present, and the capacitor is in the reverse charge state. A second integration period signal generating section for turning off the second integration period signal at a time point; and a second current having a constant value and a polarity opposite to the first current during the on period of the second integration period signal A double integration AD converter, comprising: a reverse charging section for reverse charging; and a counter for counting the clock during the ON period of the second integration period signal. 4. The second integration period signal generator compares the voltage of the capacitor with a reference voltage to determine whether the capacitor is in a charged state or a reverse charged state as seen from the reference voltage. A comparator and a judgment signal of the comparator held in synchronization with the second integration start judgment timing signal, and the held judgment signal is used for judging whether the judgment signal of the comparator is from a charging state to a reverse charging state. A latch that resets at the time of switching and a logical product condition signal of the output signal of the latch and the determination signal of the comparator are held in synchronization with the clock, and the held signal is output as a second integration period signal. The double integration AD converter according to claim 3, wherein the AD converter comprises a flip-flop.