JP3586314B2 - Double integration type AD converter - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a technique of AD conversion, about AD varying retrofit location of particular double integration method.
[0002]
[Prior art]
Generally, three types of AD conversion methods are known: a low-speed and high-precision counting method, a medium-speed and medium-precision successive approximation method, and a high-speed and low-precision parallel comparison method. Since high accuracy is required for the AD conversion in the active distance measuring device used, a low-speed and high-accuracy counting method has been awarded.
[0003]
A typical example of a low-speed and high-accuracy counting method is a so-called double integration method. In the conventional double integration A / D conversion, a capacitor is charged for a certain period of time with a current proportional to the value of an input analog signal, and then reversely charged with a reference current having a polarity opposite to that of the input signal. The reverse charging time required to return to the voltage is counted by the counter. Here, charging the capacitor with a current proportional to the value of the input analog signal is referred to as “first integration”, and reverse charging with a reference current having a reverse polarity is referred to as “reverse integration” or “second integration”. There is.
[0004]
[Problems to be solved by the invention]
For example, assuming that the clock for counting is 64 KHz, in the case of AD conversion of 8-bit output, the maximum time of the second integration is 4 ms {(1/64 KHz) × 2 ⁸ }. Therefore, assuming that the time of the first integration is also 4 ms, the AD conversion of the maximum input analog signal takes 8 ms. On the other hand, in the case of a minute input analog signal, the second integration time is very short, and the AD conversion time is 4 ms, which is almost equal to the first integration time. That is, in the conventional method, there is a problem that a large variation occurs in the AD conversion time depending on the magnitude of the input analog signal, and the usability is not good. Note that the method of increasing the reference current used for the second integration to shorten the maximum value of the second integration time causes an increase in error and involves a difficulty in circuit design because a large reference current must be passed.
[0005]
Accordingly, an object of the present invention is to provide a double integral type AD varying retrofit location with less variation in AD conversion time by the magnitude of the input analog signal.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention starts the second integration without waiting for the end of the first integration. As a result, the maximum end time of the second integration is advanced, so that the AD conversion time at the time of the maximum input analog signal can be reduced, and the variation of the AD conversion time due to the size of the input analog signal can be reduced.
[0007]
However, depending on the timing at which the second integration is started and the magnitude of the input analog signal, the voltage of the capacitor may return to the original voltage due to reverse charging by the second current during the period of the first integration. Therefore, in such a case, the reverse charging is temporarily interrupted, and then the second integration is restarted on condition that the capacitor starts to be charged again. Therefore, the second integration may be performed intermittently, in which case the second integration time is the accumulated time of each.
[0008]
If the second integration is restarted immediately after the capacitor starts to be charged again after the interruption of the second integration, the second integration must be interrupted immediately. If the input analog signal is small, the second integration is stopped. Is frequently interrupted and restarted, causing an error. Therefore, the restart of the second integration is performed in synchronization with the second integration start determination timing signal generated in a predetermined cycle.
[0009]
The double integration type AD device that implements the above-described double integration type AD conversion method receives an AD conversion start signal and a clock, and outputs a first integration period signal over a time T from the time when the AD conversion start signal is turned on. A timing signal generating circuit for generating a second integration start determination timing signal every time T / N (N is a positive integer) from the time when the A / D conversion start signal is turned on; a capacitor; A charging unit for charging the capacitor with a first current proportional to the value of the input analog signal during an ON period of the integration period signal, and monitoring whether the capacitor is in a charged state or a reverse-charged state as viewed from a reference voltage The second integration period signal is turned on in synchronization with the second integration start determination timing signal on condition that the capacitor is in a charged state, and the capacitor is in a reverse charged state. A second integration period signal generating unit for turning off the second integration period signal at a point; and, during the ON period of the second integration period signal, setting the capacitor by a second current having a constant value and a reverse polarity to the first current. A reverse charging unit for performing reverse charging; and a counter that counts the clock during the ON period of the second integration period signal.
[0010]
In a preferred embodiment of the present invention, the second integration period signal generation section compares the voltage of the capacitor with a reference voltage to determine whether the capacitor is in a charged state or a reversely charged state in view of the reference voltage. A comparator for determining whether or not the comparator is in the second integration start determination timing signal, and holding the determination signal in response to the determination signal of the comparator from the state of charge. A latch that resets when switching to the reverse charge state determination, and a logical product condition signal of an output signal of the latch and a determination signal of the comparator are held in synchronization with the clock; And a flip-flop that outputs an integration period signal.
[0011]
[Action]
When the AD conversion start signal is turned on, the timing signal generation circuit turns on the first integration period signal for a time T (for example, 4 ms). Thus, the charging unit starts charging the capacitor with the first current proportional to the input analog signal. When the AD conversion start signal is turned on, the timing signal generation circuit generates a second integration start determination timing signal every time T / N (for example, 250 μs when N = 16) elapses after the ON.
[0012]
The second integration period signal generation section monitors, by a comparator, whether the capacitor is in a charged state or a reversely charged state as viewed from the reference voltage, and the second integration start determination timing is determined on the condition that the capacitor is in the charged state. The second integration period signal is turned on in synchronization with the signal. That is, by holding the determination signal of the comparator in the latch, and setting the logical product condition signal of the output signal of the latch and the determination signal of the comparator in the flip-flop in synchronization with the clock, the second integration period signal is obtained. turn on. Thus, in parallel with the first integration, the reverse charging unit starts reverse charging the capacitor with the second current, and the counter starts counting clocks.
[0013]
Assuming that the first current generated by the charging unit at the time of the maximum input analog signal is equal to the second current of the reverse charging unit, the first current and the second current are canceled at the time of AD conversion of the maximum input analog signal. The voltage of the capacitor at the start of the second integration is maintained until the end of the first integration, and after the end of the first integration, the voltage of the capacitor returns to the original voltage when T / N has elapsed. In this case, the second integration is performed continuously for T time.
[0014]
On the other hand, when the input analog signal is small, the capacitor returns to the original voltage during the period of the first integration because the second current is larger than the first current, and the capacitor is brought into the reverse charge state by the second current. In such a reverse charging state, the flip-flop of the second integration period signal generation unit is reset by the clock immediately after that, and the second integration period signal is turned off. Thus, the counting of the clock by the counter is interrupted, the second integration by the reverse charging unit is interrupted, and only the first integration is performed again. When the capacitor is charged again, the flip-flop of the second integration period signal generation unit is set in synchronization with the second integration start determination timing signal, the second integration period signal is turned on, and the reverse charging unit again operates. The second integration is resumed, and the counter also resumes counting clocks.
[0015]
【Example】
Referring to FIG. 1, a double integration type AD converter according to an embodiment of the present invention includes a timing signal generation circuit 1, an integration capacitor 2, a charging unit 3, a reverse charging unit 4, and a second integration unit. It includes a period signal generator 5, an AND gate 6, a counter 7, and a NOR gate 8.
[0016]
The timing signal generation circuit 1 receives the AD conversion start signal R and the clock CL, and generates a first integration period signal and a second integration start determination timing signal. In the present embodiment, the clock CL is 64 KHz, and the timing signal generation circuit 1 turns on the first integration period signal for a period of 4 ms, which is a time equivalent to 256 clocks from the time when the AD conversion start signal R is turned on. To After the A / D conversion start signal R is turned on, a second integration start determination timing signal is generated every time 250 μs, which is a time equivalent to 16 clocks, elapses.
[0017]
Two charging units 3 and 4 are connected to the integrating capacitor 2. One is a charging unit 3 that performs first integration, and charges the capacitor 2 with a first current proportional to the input analog signal during a period in which the first integration period signal is on. The other is a reverse charging unit 4 for performing the second integration. During the period in which the second integration period signal generated from the second integration period signal generation unit 5 is on, the reverse charging unit 4 has a constant value opposite to the first current. The capacitor 2 is reversely charged with the second current. Note that the capacitor 2 is initially set to a voltage equal to the reference voltage before the AD conversion start signal is turned on.
[0018]
The second integration period signal generation unit 5 monitors whether the capacitor 2 is in a charged state or a reverse charged state in view of the reference voltage Vref, and generates a second integration start determination timing signal on condition that the capacitor 2 is in the charged state. The second integration period signal is turned on in synchronization. When the capacitor C is reversely charged, the second integration period signal is immediately turned off. When the capacitor C is charged again, the second integration period signal is synchronized with the second integration start determination timing signal. The operation of turning on the signal is repeated.
[0019]
In the present embodiment, the second integration period signal generator 5 compares the voltage of the capacitor 2 with the reference voltage Vref, and outputs “1” if the voltage of the capacitor 2 is lower than the reference voltage Vref; A comparator 51 that outputs 0 ”; a latch 52 that holds the output of the comparator 51 in synchronization with the second integration start determination timing signal; and an AND gate that ANDs the output of the latch 52 and the output of the comparator 51 It is composed of a gate 53 and a D-type flip-flop 54 that holds the output of the AND gate 53 in synchronization with the clock CL, and the output of the D-type flip-flop 54 becomes a second integration period signal. The second integration period signal is supplied to the above-described reverse charging unit 4 and also to one input of the AND gate 6. When the AD conversion start signal R is turned on, the latch 52 and the D-type flip-flop 54 are reset, and the second integration period signal is initialized to an off state. The latch 52 is also reset to “0” when the output of the comparator 51 changes from “1” to “0”.
[0020]
The clock CL is supplied to the other input of the AND gate 6, and the clock CL is passed to the counter 7 while the second integration period signal supplied to the one input is on. I do. The counter 7 counts the clock CL output from the AND gate 6. The counter 7 is reset to 0 when the AD conversion start signal R is turned on.
[0021]
The NOR gate 8 is a gate that determines the end of the AD conversion, and outputs an AD conversion end signal at a timing when the second integration period signal is turned off after the first integration period signal is turned off. The A / D conversion end signal is supplied to a subsequent circuit (not shown), and the latter circuit reads the count value of the counter 7 when the A / D conversion end signal is input, and obtains an A / D conversion result.
[0022]
Next, the operation of the double-integration type AD converter according to the present embodiment configured as described above will be described.
[0023]
FIG. 2 is an operation timing chart of the embodiment of FIG. 1 at the time of AD conversion of the maximum input analog signal. When the AD conversion start signal R is turned on, the first integration period signal from the timing signal generation circuit 1 is turned on, and the capacitor 2 is charged by the charging unit 3 with the maximum first current. When 250 μs elapses after the AD conversion start signal R is turned on, the timing signal generation circuit 1 outputs a second integration start determination timing signal. At this timing, as shown in FIG. 2, since the voltage of the capacitor C is sufficiently lower than the reference voltage Vref, the output of the comparator 51 becomes "1", and "1" is latched in the latch 52. Therefore, the output of the AND gate 53 becomes "1", "1" is set in the D-type flip-flop 54, and the second integration period signal is turned on. As a result, the reverse charging unit 4 starts reverse charging the capacitor 2 with the second current, and the counter 7 starts counting the clock CL because the AND gate 6 is opened.
[0024]
In the present embodiment, the value of the second current of the reverse charging unit 4 is set to be equal to the first current of the charging unit 3 at the time of the maximum input analog signal. Are offset, and the voltage of the capacitor C changes with a constant value as shown in FIG. When the first integration period signal from the timing signal generation circuit 1 is turned off 4 ms after the A / D conversion start signal R is turned on, only the reverse charging by the reverse charging unit 4 is performed, and the voltage of the capacitor C becomes the reference voltage. It rises toward Vref. Then, at the clock CL immediately after the voltage of the capacitor C exceeds the reference voltage Vref, the D-type flip-flop 54 is reset to “0” due to the output signal of “0” of the comparator 51, and the second integration is performed. The period signal is turned off. Thereby, the reverse charging is stopped, the AND gate 6 is closed, the counting operation of the counter 7 is stopped, and the AD conversion end signal is output from the NOR gate 8.
[0025]
FIG. 3 is an operation timing chart of the embodiment of FIG. 1 when the input analog signal is relatively small. When the AD conversion start signal R is turned on, the capacitor 2 is charged by the charging unit 3 with the first current proportional to the input analog signal, as described above. When 250 μs elapses after the A / D conversion start signal R is turned on, the voltage of the capacitor C is lower than the reference voltage Vref, but the degree of the decrease is smaller than in the case of the maximum input analog signal of FIG. At this time, when the second integration start determination timing signal is output from the timing signal generation circuit 1, the voltage of the capacitor C is lower than the reference voltage Vref, so that the output of the comparator 51 becomes "1" as described above, "1" is latched by the latch 52, the output of the AND gate 53 becomes "1", "1" is set in the D-type flip-flop 54, and the second integration period signal is turned on. Thereby, the reverse charging unit 4 starts reverse charging the capacitor 2 with the second current, and the counter 7 starts counting the clock CL.
[0026]
As described above, the value of the second current of the reverse charging unit 4 is set equal to the first current of the charging unit 3 at the time of the maximum input analog signal. Therefore, when the input analog signal is small, the second current is smaller. Above the first current, the voltage of the capacitor C gradually increases toward the original voltage as shown in FIG. Then, at the clock CL immediately after the voltage of the capacitor C exceeds the reference voltage Vref, the D-type flip-flop 54 is reset to “0” due to the output signal of “0” of the comparator 51, and the second integration is performed. The period signal is turned off. Thereby, the reverse charging stops and the counting operation of the counter 7 stops. The latch 52 holding “1” is reset at the timing when the output of the comparator 51 changes from “1” to “0”, and becomes “0”.
[0027]
When the reverse charging stops, the capacitor C is only charged by the charging unit 3 again, so that the voltage of the capacitor C decreases again as shown in FIG. When the voltage of the capacitor C is lower than the reference voltage Vref at the time when the second integration start determination timing signal is output from the timing signal generation circuit 1, the output of "1" of the comparator 51 is latched by the latch 52, The output of the AND gate 53 becomes "1", "1" is set in the D-type flip-flop 54 in synchronization with the clock CL immediately thereafter, the reverse charging by the reverse charging unit 4 is restarted, and the counter 7 Clock CL is restarted.
[0028]
The above operation is repeated, and when charging by the charging unit 3 ends 4 ms after the AD conversion start signal R is turned on, only reverse charging by the reverse charging unit 4 is performed, which is not shown in FIG. However, the voltage of the capacitor C increases toward the reference voltage Vref. Then, at the clock CL immediately after the voltage of the capacitor C exceeds the reference voltage Vref, the D-type flip-flop 54 is reset to “0” due to the output signal of “0” of the comparator 51, and the second integration is performed. The period signal is turned off. As a result, the reverse charging is stopped, the AND gate 6 is closed, the counting operation of the counter 7 is stopped, and the AD conversion end signal is output from the NOR gate 8.
[0029]
As described above, according to the embodiment shown in FIG. 1, the time required for AD conversion of the maximum input analog signal is 4 ms + 250 μs, and the variation width of the AD conversion time due to the magnitude of the input signal is suppressed to 250 μs.
[0030]
【The invention's effect】
As described above, according to the present invention, the time required for AD conversion of the maximum input analog signal can be shortened, and the AD conversion of the double integration method in which the variation of the AD conversion time due to the magnitude of the input signal is small. There is an effect that it can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a double integration type AD converter according to an embodiment of the present invention.
FIG. 2 is an operation timing chart of the embodiment of FIG. 1 when an input analog signal has a maximum value.
FIG. 3 is an operation timing chart of the embodiment of FIG. 1 when an input analog signal is relatively small.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 timing signal generating circuit 6 AND gate 2 capacitor 7 counter 3 charging unit 8 NOR gate 4 reverse charging unit 5 second integration period signal generating unit 51 comparator 52 latch 53 AND gate 54 D-type flip-flop

Claims (2)

An A / D conversion start signal and a clock are input, the first integration period signal is turned on for a time T from the on time of the A / D conversion start signal, and the time T / N (N is a positive A timing signal generating circuit for generating a second integration start determination timing signal every time an integer has passed;
A capacitor,
A charging unit that charges the capacitor with a first current proportional to a value of an input analog signal during an ON period of the first integration period signal;
It monitors whether the capacitor is in a charging state or a reverse charging state in view of a reference voltage, and turns on a second integration period signal in synchronization with the second integration start determination timing signal on condition that the capacitor is in a charging state. A second integration period signal generation unit that turns off the second integration period signal when the capacitor is in a reverse charge state;
A reverse charging unit that reverse charges the capacitor with a second current having a constant value and a reverse polarity to the first current during an ON period of the second integration period signal;
And a counter for counting the clock during the ON period of the second integration period signal. The second integration period signal generation unit includes:
By comparing the voltage of the capacitor with a reference voltage, a comparator that determines whether the capacitor is in a charged state or in a reverse charge state from the viewpoint of a reference voltage,
The determination signal of the comparator is held in synchronization with the second integration start determination timing signal, and the held determination signal is switched when the determination signal of the comparator switches from the charging state to the determination of the reverse charging state. A latch to reset with
A flip-flop for holding a logical product condition signal of an output signal of the latch and a determination signal of the comparator in synchronization with the clock, and outputting the held signal as a second integration period signal. 2. The double integration type AD converter according to claim 1, wherein:

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