JPH08316822A - Cmos logic circuit - Google Patents

Abstract

PURPOSE: To reduce power consumption and switching noise by decreasing a through-current in the CMOS logic circuit without degrading the drive capability of transistors(TRs). CONSTITUTION: Drains of a P-channel TR 5 and of an N-channel TR 6 are connected, sources of the P-channel TR 5 and the N-channel TR 6 are connected and the source of the N-channel TR 6 is connected to a gate of the P-channel TR 5. Then the sources and the drains of the P-channel and N-channel TRs are used for a signal transmission reception section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention suppresses the occurrence of shoot-through current and reduces power consumption and switching noise.
The present invention relates to a MOS logic circuit.

[0002]

2. Description of the Related Art Conventionally, in a CMOS logic circuit, a structure has been used in which the drains of a P-channel transistor and an N-channel transistor are connected to each other, and the connection point is used as an output part. This will be described below with reference to the drawings. explain.

The logic circuit shown in FIG. 2 is a circuit diagram of a conventional CMOS logic circuit called an inverter, in which 1 is an input section, 2 is a P-channel transistor, 3 is an N-channel transistor, and 4 is an output section.

The operation of the CMOS logic circuit configured as described above will be described below. The state in which a drain current flows through a transistor is on and the state in which a transistor is in high impedance is off. The high potential and the low potential with respect to the threshold value of the logic circuit are described as H level and L level, respectively.

Now, the potential Vi input from the input section 1 is H
At the level, the P-channel transistor 2 is off and N
Since the channel transistor 3 is turned on, the potential Vo output from the output unit 4 becomes the ground potential, and the L level potential is output. When the potential Vi of the input section 1 is L level, the P-channel transistor 2 is turned on and the N-channel transistor 3 is turned off, so that the potential V of the output section 4 is
o becomes the positive power supply potential Vdd, and the H level potential is output.

[0006]

However, in the conventional CMOS logic circuit described above, when the potential Vi of the input section 1 is near the threshold value of the logic circuit, both the P-channel transistor 2 and the N-channel transistor 3 are turned on. Therefore, there is a problem that a shoot-through current flows between the positive power supply potential Vdd and the ground power supply potential GND, which not only increases power consumption but also causes switching noise, and suppresses this shoot-through current. In order to do so, it was necessary to reduce the driving ability of the transistor.

The present invention solves the above-mentioned conventional problems, and provides a CMOS logic circuit in which the shoot-through current is reduced without lowering the driving capability of the transistor, and the power consumption is reduced and the switching noise is reduced. The purpose is to

[0008]

To achieve this object, in a CMOS logic circuit of the present invention, the drains of a P-channel transistor and an N-channel transistor are connected to each other, and the source of the P-channel transistor and the N-channel transistor are connected. Of the N-channel transistor and the source of the N-channel transistor are connected to the gate of the P-channel transistor, and the sources and drains of the P-channel transistor and the N-channel transistor are used as a signal transfer unit.

[0009]

With this configuration, when a shoot-through current is generated, the positive power supply voltage is the same as the conventional C voltage according to Kirchhoff's law.
Compared to the MOS logic circuit, the voltage is divided into a larger number of drain-source voltages, so that the drain-source voltage per transistor is reduced and the shoot-through current is suppressed.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of a CMOS logic circuit according to an embodiment of the present invention. In addition,
The same parts as those of the conventional one are designated by the same reference numerals.

In FIG. 1, reference numeral 1 is an input portion, 2 is a P-channel transistor, 3 is an N-channel transistor, and 4 is an output portion.
In the present invention, the following components, that is, a P-channel transistor 5 and an N-channel transistor 6 are added between the P-channel transistor 2 and the N-channel transistor 3 as shown.

With respect to the CMOS logic circuit configured as described above, first, the operation when the potential Vi of the input section 1 is near the threshold value of the logic circuit will be described. in this case,
P-channel transistor 2 and N-channel transistor 3
Are both turned on, and the gate-source voltage of the P-channel transistor 5, that is, the gate-source voltage of the N-channel transistor 6 becomes substantially equal to the difference between the positive power supply potential Vdd and the ground potential GND. , P-channel transistor 5 and N-channel transistor 6 have higher threshold voltages. Therefore, the P-channel transistors 2 and 5 and the N-channel transistors 3 and 6 are all turned on, and a through current flows.

When a shoot-through current flows, according to Kirchhoff's law, a positive power supply voltage is applied to the P-channel transistor 2,
5, the drain-source voltage of each of the N-channel transistors 3 and 6 is equal to the sum of the drain-source voltages of the N-channel transistors 3 and 6, so that the drain-source voltage of each transistor is smaller than that in the conventional CMOS logic circuit, and the power supply current is , The drain current of the transistor 2 becomes equal to the magnitude of the drain current, and as a result, the through current can be suppressed low.

Next, the case where the potential Vi of the input section 1 changes from the L level to the H level will be described. When the potential Vi of the input section 1 changes from the L level to the H level, the P channel transistor 5 is Gate-source voltage, that is, N
The gate-source voltage of the channel transistor 6 temporarily becomes a value near the threshold value of the logic circuit, and a through current flows as in the case described above.

While the through current is flowing, the P-channel transistors 2 and 5 and the N-channel transistors 3 and 6 are all on, and the voltage is the voltage between the gate and the source of the P-channel transistor 5, that is, the N-channel. The gate-source voltage of the transistor 6 is higher than the threshold voltage of either the P-channel transistor 5 or the N-channel transistor 6.

When the potential Vi of the input section 1 becomes H level,
First, the P-channel transistor 2 is turned off. When the P-channel transistor 2 is turned off, the drain current of the P-channel transistor 5 also stops flowing.

At this time, the P-channel transistor 5 is
Since the channel transistor 3 is on, the gate becomes the ground potential and forms a channel, but since the drain current does not flow, the potential of the source of the P channel transistor 5 is the potential immediately before the P channel transistor 2 is turned off. It becomes a constant value while holding.

Since the N-channel transistor 6 is turned on, the source of the N-channel transistor 6 becomes the ground potential, and the voltage between the gate and the source becomes constant at a value higher than the threshold voltage. , The output section 4 is driven to the ground potential. Therefore, the output unit 4 stabilizes at the ground potential and outputs the L-level potential Vo.

Next, the case where the potential Vi of the input section 1 changes from the H level to the L level will be described. When the potential Vi of the input section 1 changes from the H level to the threshold voltage of the logic circuit, All of the P-channel transistors 2 and 5 and the N-channel transistors 3 and 6 are turned on again. The gate-source voltage of the P-channel transistor 5, that is, the gate-source voltage of the N-channel transistor 6 is
P-channel transistor 5 and N-channel transistor 6
Which is higher than either threshold voltage.

When the potential Vi of the input section 1 becomes L level, the N-channel transistor 3 is first turned off. N
When the channel transistor 3 is turned off, the drain current of the N-channel transistor 6 also stops flowing.

At this time, the N-channel transistor 6 has P
Since the channel transistor 2 is on, the gate is at the positive power supply potential Vdd and forms a channel. However, since the drain current does not flow, the source potential of the N-channel transistor 6 becomes a constant value while holding the potential immediately before the N-channel transistor 3 is turned off.

In the P-channel transistor 5, since the P-channel transistor 2 is still on, the source becomes the positive power supply potential Vdd, and the voltage between the gate and the source is constant at a level equal to or higher than the threshold voltage. So
The output section 4 is driven until it reaches the positive power supply potential Vdd.

Therefore, the output section 4 stabilizes at the positive power supply potential Vdd and outputs the H-level potential Vo.

As described above, according to this embodiment, by inserting the P-channel transistor 5 and the N-channel transistor 6 in series between the drains of the P-channel transistor 2 and the N-channel transistor 3, the P-channel transistor at the time of the occurrence of the through current is generated. The voltage between the drain and the source of the channel transistor 2 can be suppressed below that of the conventional CMOS logic circuit, and as a result, the shoot-through current can be limited.

The output section 4 is driven by transistors 5, 6
Therefore, the shoot-through current can be limited without impairing the driving ability.

Although the above embodiment has been described based on the inverter circuit, a general CM other than the inverter circuit is used.
The same effect can be obtained also in the OS logic circuit.

[0027]

According to the present invention, a P channel transistor and an N
The drains of the channel transistors are connected to each other, and the P
The source of the channel transistor is connected to the gate of the N-channel transistor, the source of the N-channel transistor is connected to the gate of the P-channel transistor, and the source and drain of the P-channel transistor and the N-channel transistor are connected to each other. By using the transfer unit, it is possible to realize an excellent CMOS logic circuit that can suppress the through current without lowering the driving ability of the transistor and can reduce the power consumption and the switching noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a CMOS logic circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional CMOS logic circuit.

[Explanation of symbols]

1, 5 ... P-channel transistor, 2, 6 ... N-channel transistor, 3 ... Input section, 4 ... Output section.

Claims (3)

[Claims] 1. A drain of a P-channel transistor and an N-channel transistor are connected to each other, a source of the P-channel transistor is connected to a gate of the N-channel transistor, and a source of the N-channel transistor is connected to a gate of the P-channel transistor. Connected,
A CMOS logic circuit, wherein a source and a drain of the P-channel transistor and the N-channel transistor are used as a signal transfer unit. 2. A drain of a P-channel transistor and an N-channel transistor are connected to each other, a source of the P-channel transistor is connected to a gate of the N-channel transistor, and a source of the N-channel transistor is connected to a gate of the P-channel transistor. Connected,
A CMOS logic circuit, wherein the drain connection point is used as an output section. 3. A drain of a P-channel transistor and an N-channel transistor are connected to each other, a source of the P-channel transistor is connected to a gate of the N-channel transistor, and a source of the N-channel transistor is connected to a gate of the P-channel transistor. Connected,
A CMOS logic circuit, characterized in that the sources of the P-channel transistor and the N-channel transistor are provided with an input section via a switching element, and an output section is provided at a connection point of the drain.