JPH0690159A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the malfunction or radio wave fault of an external circuit by performing the gate control of the respective MOS transistors(Tr) of a P channel and an N channel corresponding to an input signal and the output signal of a NOT element. CONSTITUTION:This circuit is provided with a first control circuit 6 to input a signal IN to a terminal 1 and the output signal of a NOT element 3 and to output the gate control signal of a P channel MOS TR 4, and the gate signal of an N channel TR 5 is controlled by a second control circuit 7 while inputting the signal IN and the output signal of the element 3. The circuits 6 and 7 can output the gate control signals for which timing is shifted each other. Therefore, the gates of the TR 4 and 5 are independently controlled so that they can not be simultaneously turned on. Thus, a through current is reduced, overshoot or undershoot generated at an output signal OUT is suppressed, and the malfunction or radio wave fault of the external circuit can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit in a CMOS integrated circuit.

[0002]

2. Description of the Related Art Conventionally, an output buffer circuit for a semiconductor integrated circuit, which has a large driving capability and outputs a signal input to an input terminal, is generally shown in FIG. Those having various circuit configurations are known. This output buffer circuit includes a NOT element 103 whose input side is connected to an input terminal 101, a P-channel MOS transistor 104 whose source is a power source, whose drain is an output terminal 102 and whose gate is connected to the output side of a NOT element 103, and whose source is The drain is connected to the ground, the output terminal 102 is connected to the gate, and the NOT element 103 is connected to the gate.
N-channel MOS transistor 105 connected to the output side of
It consists of and.

Then, the signal I input to the input terminal 101 is input.
N is inverted by the NOT element 103 to turn on one of the CMOS transistors 104 and 105 and output terminal
It operates so as to transmit a signal equal to the logic level input to the input terminal 101 to the input terminal 102. For example, when a signal IN having a logic level "H" is input to the input terminal 101, the output of the NOT element 103 becomes "L" level and the P channel MOS
The transistor 104 is turned on, the N-channel MOS transistor 105 is turned off, and the signal OUT having the logic level "H" appears at the output terminal 102.

[0004]

In the case of such a conventional output buffer circuit, as shown in the timing chart of FIG. 5, for example, the logic signal IN input to the input terminal 101 changes from "L" level to "L" level. When it changes to H ”level,
The output node c of the NOT element 103 gradually changes from "H" level to "L" level. Where V _a = V _DD −
When V _TP , V _b = V _SS + V _TN (where V _TP and V _TN are threshold voltages of P-channel and N-channel MOS transistors, respectively, and V _DD and V _SS are power supply and ground potentials) When the voltage of the output node c is higher than V _a , only the N-channel MOS transistor 105 is on, and when it is lower than V _b , only the P-channel MOS transistor 104 is on.

However, the voltages at the output node c are V _a and V _b.
, The N-channel and P-channel transistors 104 and 105 are turned on, a current (penetration current) flows from the power supply to the ground, and a particularly large external load is driven. To increase the size of the channel MOS transistors 104 and 105, and to shorten the gate length for higher speed and higher integration,
As shown in FIG. 6, overshoot and undershoot occur in the output signal OUT due to the external load and the shoot-through current, which causes malfunction of the external circuit, radio interference, and the like.

The present invention has been made in order to solve the above problems in the conventional output buffer circuit, and reduces the shoot-through current and suppresses overshoot and undershoot occurring in the output signal to prevent malfunction of the external circuit. It is an object of the present invention to provide an output buffer circuit capable of reducing radio interference.

[0007]

In order to solve the above problems, the present invention, as shown in the conceptual diagram of FIG. 1, has a first P having a source connected to a power source and a drain connected to an output terminal 2.
A channel MOS transistor 4, a first N-channel MOS transistor 5 whose source is grounded and whose drain is connected to an output terminal 2, and NOT whose input side is connected to an input terminal 1.
In the output buffer circuit having the element 3, the first control for inputting the input signal IN applied to the input terminal 1 and the output signal of the NOT element 3 and outputting the gate control signal of the first P-channel MOS transistor 4 A circuit 6 and a second control circuit 7 that receives the input signal IN applied to the input terminal 1 and the output signal of the NOT element 3 and outputs the gate control signal of the first N-channel MOS transistor 5 are provided. It is what constitutes.

In the output buffer circuit configured as described above, the first control circuit 6 and the second control circuit 7 have their gate control signals a and b whose timings are shifted from each other, as shown in the timing chart of FIG. Can be output,
As a result, the gates of the first P-channel MOS transistor 4 and the first N-channel MOS transistor 5 can be independently controlled so that they are not simultaneously turned on. Therefore, it is possible to reduce the through current, suppress the overshoot and the undershoot that occur in the output signal OUT, and reduce the malfunction of the external circuit, the radio interference, and the like.

[0009]

EXAMPLES Next, examples will be described. FIG. 3 is a circuit configuration diagram showing a specific embodiment of the output buffer circuit according to the present invention. In the figure, 11 is an input terminal, 12 is an output terminal, 13 is a NOT element, and 14, 15, 16 are P-channel MOS.
Transistors 17, 18, 19 are N-channel MOS transistors. Then, the P-channel MOS transistor 14
And 15 constitute the first control circuit, and the N channel MO
The S-transistors 17 and 18 form a second control circuit. The size of the P-channel MOS transistor 15 is P
Larger than the size of the channel MOS transistor 14,
The size of the N-channel MOS transistor 18 is larger than that of the N-channel MOS transistor 17.

The drains of the P-channel MOS transistor 16 and the N-channel MOS transistor 19 are commonly connected and connected to the output terminal 12.
Sources of S-transistors 15 and 16 are for power supply and N-channel M
The sources of the OS transistors 18 and 19 are connected to ground. The gate of the P channel MOS transistor 16 is connected to the drain of the P channel MOS transistor 15 and the source of the P channel MOS transistor 14, while the gate of the N channel MOS transistor 19 is connected to the N channel MO transistor.
It is connected to the drain of the S transistor 18 and the source of the N-channel MOS transistor 17. The gate of the P-channel MOS transistor 15 and the gate of the N-channel MOS transistor 18 are connected to the input terminal 11 together with the input side of the NOT element 13, and the gate and drain of the P-channel MOS transistor 14 and the N-channel MOS transistor 17 are connected. The gate and drain are connected to the output side of the NOT element 13, respectively.

In FIG. 3, 20 is the gate capacitance of the P-channel MOS transistor 16 existing at the node a and P
A stray capacitance composed of diffusion capacitances of the channel MOS transistors 14 and 15, and 21 is an N channel M existing at the node b.
Gate capacitance of OS transistor 19 and N-channel MOS
It is a stray capacitance composed of diffusion capacitances of the transistors 17 and 18.

Next, the operation of the output buffer circuit thus constructed will be described with reference to the timing chart of FIG. First, for the sake of explanation, the input terminal 11 and the output terminal 12 are set to the “L” level as an initial state. At this time, the P-channel MOS transistor 15 is turned on and the N-channel MOS transistor 18 is turned off. On the other hand, NOT
Since the output of element 13 is at "H" level, N channel M
The OS transistor 17 is turned on and the P-channel MOS transistor 14 is turned off. As a result, the node a is set to the power supply V _DD potential of "H" level by the P channel MOS transistor 15, while the node b is set to the N channel MO.
The S-transistor 17 brings it to the "H" level, but its voltage value is a voltage value lower than the power supply _VDD potential by the threshold voltage of the N-channel MOS transistor 17. As a result, the P-channel MOS transistor 16 is turned off, the N-channel MOS transistor 19 is turned on, and the “L” level output signal OUT appears at the output terminal 12.

Next, from this state, the input signal IN is changed to that shown in FIG.
As shown in, the operation when the level is changed to "H" will be described. When the input signal IN becomes "H" level, the P-channel MOS transistor 15 is turned off,
The channel MOS transistor 18 is turned on. At this time, the P-channel MOS transistor 14 has the NOT element 13
Remains in the off state until the output of the node becomes "L" level, and the voltage of the node a is the stray capacitance 10 existing in the node a.
Thus, the "H" level is maintained. On the other hand, the voltage of the node b is determined by the N-channel MOS transistor 17 being the NOT element 13
Even when the output of is turned on until it goes to the "L" level, the voltage value changes toward the "L" level by the N-channel MOS transistor 18 having a large transistor size.

After this, when the output of the NOT element 13 changes from the "H" level to the "L" level, the N-channel MOS
The transistor 17 is turned off, and the node b is at "L" level (V
At the same time as _SS ), the P-channel MOS transistor 14
Is turned on, and the stray capacitance 10 that maintains the voltage of the node a is connected to the P-channel MOS transistor 14 and NOT.
It is discharged by the element 13 and becomes "L" level later than the node b. The voltage level at this time has a voltage value higher than the output of the NOT element 13 by the threshold voltage of the P-channel MOS transistor 14. As a result, the N-channel MOS transistor 19 is turned off first, the P-channel MOS transistor 16 is turned on, and the output terminal 12 becomes "H" level.

Next, the operation when the input signal IN changes from "H" level to "L" level will be described.
When the input signal IN becomes "L" level, N channel MO
The S-transistor 18 is turned off, and the N-channel MO is maintained until the output of the NOT element 13 is inverted and becomes "H" level.
The S transistor 17 remains in the off state, and the voltage value of the node b is maintained at the “L” level by the stray capacitance 21 existing in the node b. On the other hand, even if the P-channel MOS transistor 14 is in the ON state until the output of the NOT element 13 becomes the “H” level, the P-channel MOS transistor 15 having a large transistor size is in the ON state, so that the voltage value of the node a is Change to "H" level.

After this, when the output of the NOT element 13 changes from the "L" level to the "H" level, the P-channel MOS
The transistor 14 is turned off, the node a is set to the “H” level (V _DD ), and at the same time, the N-channel MOS transistor 17 is turned on, and the floating capacitance 21 that maintains the voltage of the node b is transferred to the N-channel MOS transistor 17. And is charged by the NOT element 13 and is "H" after the node a.
It becomes a level. The voltage level at this time has a voltage value lower than the output of the NOT element by the threshold voltage of the N-channel MOS transistor 17. As a result,
After the P-channel MOS transistor 16 is turned off first,
The N-channel MOS transistor 19 turns on, and the output terminal becomes "L" level.

As described above, according to this embodiment, the P-channel MOS transistor 16 and the N-channel M in the final output stage are provided.
It operates so that the OS transistor 19 and the OS transistor 19 are not turned on at the same time.

[0018]

As described above on the basis of the embodiments,
According to the present invention, the P-channel MOS transistor and the N-channel MOS transistor in the final output stage of the output buffer circuit are prevented from being turned on at the same time, whereby the through current flowing from the power supply to the ground side can be reduced. Therefore, it is possible to realize the output buffer circuit in which the overshoot and the undershoot that occur in the output signal are suppressed, and the malfunction of the external circuit and the radio interference are reduced.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining an output buffer circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the output buffer circuit shown in FIG.

FIG. 3 is a circuit configuration diagram showing a specific embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a circuit configuration diagram showing a configuration example of a conventional output buffer circuit.

FIG. 6 is a timing chart for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 NOT Element 4 First P-Channel MOS Transistor 5 First N-Channel MOS Transistor 6 First Control Circuit 7 Second Control Circuit

Claims (3)

[Claims] 1. A first P-channel MOS transistor having a source connected to a power supply and a drain connected to an output terminal, a first N-channel MOS transistor having a source connected to ground and a drain connected to an output terminal, and an input side to an input side. A first control circuit for inputting an input signal applied to an input terminal and an output signal of a NOT element and outputting a gate control signal of a first P-channel MOS transistor in an output buffer circuit having a NOT element connected to And a second control circuit for inputting the input signal applied to the input terminal and the output signal of the NOT element and outputting the gate control signal of the first N-channel MOS transistor.
An output buffer circuit, which is controlled so that the transistor and the first N-channel MOS transistor are not turned on at the same time. 2. The first control circuit includes a first drain
Second P-channel MOS transistor in which the source is connected to the power source and the gate is connected to the input terminal of the P-channel MOS transistor, and the source is the gate of the first P-channel MOS transistor and the drain and the gate are the output of the NOT element. Third P-channel MO connected to the side
The second control circuit includes a second N-channel MOS transistor having a drain connected to the gate of the first N-channel MOS transistor, a source connected to the ground, and a gate connected to an input terminal, and a source. First
The third N-channel MOS transistor having a drain and a gate connected to the output side of the NOT element
The output buffer circuit according to claim 1, wherein the output buffer circuit comprises a channel MOS transistor. 3. A second P that constitutes the first control circuit.
The size of the channel MOS transistor is set to the third P
A second N-channel MO which is larger than the size of the channel MOS transistor and which constitutes the second control circuit.
The size of the S-transistor is set to the third N-channel MO.
The output buffer circuit according to claim 2, wherein the output buffer circuit is configured to be larger than the size of the S transistor.