JPH05191256A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the semiconductor device the operation delay time of a bus driver circuit and capable of shortening improving the operating speed of the entire circuit. CONSTITUTION:The semiconductor device provided with plural circuit blocks 1, 2, a signal line 3, and a driver circuit 4 for the signal line 3 and transferring a signal to other circuit block via the driver circuit 4 and the signal line 3 is provided with a means 5 converting a low amplitude signal in a circuit block of a signal sender source into a higher amplitude signal than a power supply voltage of the circuit block and the driver circuit 4. Then the converted said signal is applied to the input to the driver circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to speeding up a low voltage MOS type integrated circuit.

[0002]

2. Description of the Related Art In a large-scale logic LSI, many bus lines exist between a plurality of circuit blocks in a chip. For example, as shown in FIG. 2, when a signal is transferred from the functional block 1 to the functional block 2, the functional block 1 and the functional block 2 are connected by a bus line 3 and the signal is transferred by the bus driver circuit 6. It was At this time, a signal equal to the potential in the circuit block was also input to the gate of the transistor of the bus driver circuit 6 that drives the bus line.

[0003]

In recent years, with the aim of reducing the power consumption of the chip, the voltage of the chip has been reduced. However, when the power supply voltage of the circuit is lowered in the same process, the power consumption can be reduced, and at the same time, the operating speed of the circuit is reduced. In particular, a bus driver circuit that drives a bus line having a large parasitic capacitance has a long delay time due to a decrease in power supply voltage, and has a large effect on the operating speed of the entire circuit. An object of the present invention is to provide a semiconductor device that reduces the operation delay time of a bus driver circuit in a low voltage circuit and improves the operation speed of the entire circuit.

[0004]

In order to solve the above problems, it is necessary to improve the driving capability of the bus driver circuit and reduce the delay time. The cause of the decrease in the operating speed of the bus driver circuit is that the gate applied voltage of the bus driver circuit is decreased due to the decrease in the power supply voltage of the circuit. Therefore, a semiconductor device of the present invention for achieving the above object has a plurality of circuit blocks, a signal line, and a driver circuit for the signal line, and the driver circuit and the signal line are transmitted from the circuit block of the signal transmission source. In a semiconductor device that transfers a signal to another circuit block via a circuit, for example, as shown in FIG. 1, a low-amplitude signal in the circuit block 1 from which the signal is transmitted is transferred to the circuit block 1 and the driver circuit 4. Means 5 for converting into a high amplitude signal larger than the power supply voltage
And the converted signal is applied to the input of the driver circuit 4.

Here, when the means for converting to the high-amplitude signal drives the bus line 3 for transferring the signal between the circuit blocks of the integrated circuit as shown in FIG. 1, the input to the bus driver circuit 4 is performed. Be prepared for. Alternatively, the means for converting the signal into the high-amplitude signal may be, for example, as shown in FIG.
, The clock generation circuit 32 in the logic integrated circuit 31
When driving the clock signal line 34 that supplies the clock signal to the circuit block to be controlled from the above, it may be provided for the input to the clock driver circuit 33. Alternatively, a means for converting the signal into the high-amplitude signal is described in, for example, FIG.
As shown in FIG. 1, the input to the output driver circuit 41 that gives a signal output from the encoder 40 of the parallel multiplier 39 in the arithmetic integrated circuit to the decoder 43 via the output signal line 42 may be provided.

In this case, the means for converting to the high-amplitude signal comprises a CMOS inverter circuit connected between voltage power supplies that provide the voltage level of the high-amplitude signal, and the CMOS inverter circuit is of the first conductivity type. A series configuration of a MOS transistor and a second conductivity type MOS transistor, the series configuration having gates connected to each other as an input;
A configuration in which the drains are connected to each other for output, and the threshold voltage of the first conductivity type MOS transistor is high and the threshold voltage of the second conductivity type MOS transistor is low, or the threshold voltage of the first conductivity type MOS transistor is low. And a threshold voltage of the second conductivity type MOS transistor is set to be high, or a threshold voltage of both the first conductivity type MOS transistor and the second conductivity type MOS transistor is set to be high. If so, the circuit is simple and there is no fear of through current, which is preferable.

Further, in this case, the driver circuit for driving the signal line by giving the high amplitude signal to the input is, for example, as shown in FIG.
As shown in FIG.
It includes a series configuration in which transistors are connected in series, and the series configuration includes the source of one MOS transistor and the source of the other M transistor.
It is assumed that the output is connected to the drain of the OS transistor, and one input of the gate inputs of both transistors is an inverting input with respect to the other, and the high amplitude signal is applied to both inputs. For example, it is preferable for driving the signal line at a low voltage and a high speed without causing a drop in the threshold voltage of the transistor in the output voltage of the driver circuit.

[0008]

When the high-amplitude signal 8 shown in FIG. 1 is input to the bus driver circuit 4, for example, when the circuit configuration of the present invention is used,
The bus line can be speeded up as compared with the conventional circuit configuration in which the low-amplitude signal 12 shown in (1) is input to the bus driver circuit 6. For example, in the circuit shown in FIG. 3, when the power supply voltage is 1.5V and the gate input voltage of the NMOS transistor 10 is boosted by 1V to 2.5V, the signal delay time becomes about half. At this time, the PMOS transistor 9
May be the same low amplitude signal 12 as in the prior art. That is, in the present invention, since the high-amplitude signal 8 is only input to the gate of the driver circuit, the power loss is not increased and the speed can be increased.

A bus line for transferring a signal between circuit blocks of an integrated circuit, a clock signal line for supplying a clock signal from a clock generation circuit in a logic integrated circuit to a circuit block to be controlled, or a bus line in an arithmetic integrated circuit The output signal line from the encoder of the parallel multiplier to the decoder has a large load capacitance. Therefore, if a high-amplitude signal is applied to the inputs of the driver circuits for these signal lines especially in the case of a low-voltage power supply by the means of the present invention, high speed operation can be achieved despite the low-voltage circuit. Become.

[0010]

FIG. 1 shows a first embodiment of the present invention. Figure 1
Is a semiconductor integrated circuit having the circuit configuration of the present invention. In FIG. 1, a signal is transferred from the functional block 1 to the functional block 2 via the bus line 3. Further, the circuit configuration is such that the output signal from the functional block 1 is converted into a high potential signal by the level conversion circuit 5 to drive the bus driver circuit 4. In FIG. 1, the amplitude of the input signal of the bus driver circuit 4 is higher than the potential of the power source in the functional block 1 and the bus driver circuit. That is, the level conversion circuit 5 converts the signal into a signal having a high signal amplitude, and the signal is input to the gate of the bus driver circuit 4 to increase the driving capability of the bus driver circuit 4. As a result, the delay time of the bus line 3 can be shortened. Moreover, since only the gate potential of the bus driver is boosted, it does not lead to an increase in power consumption.

FIG. 3 shows a specific circuit example of the bus driver circuit 4 used in the first embodiment. The bus driver circuit uses an NMO when the bus line is of the precharge type.
It is composed of an S transistor 10 and a PMOS transistor 9 for precharging. Here, the effect of improving the driving capability will be concretely shown in the case of the circuit of FIG. As various conditions in FIG. 3, the low-voltage power supply 7 and the low-amplitude signal 12 are 1.5 V, the high-amplitude signal 8 is 2.5 V, the load capacitance CL of the bus line 3 is 2 pF, the pre-charging PMOS transistor 9 and the driving circuit. When the gate width (W) of the NMOS transistor 10 is 50 μm, the delay time is 0.22
ns, the low amplitude signal 12 is transferred to the NMOS transistor 1
It is about twice as fast as 0.54 ns when input to the 0 gate. However, the calculated value of the delay time is a value obtained by computer simulation.

FIG. 4 shows a concrete circuit example of the level conversion circuit used in the first embodiment. The level conversion circuit is 4
It is composed of a level shift circuit unit and an inverter 17 in which individual MOS transistors are combined. The sources of the PMOS transistors 13 and 14 of the level shift circuit section are connected to the high potential power source 11, and the low amplitude signal 12 is input to the gates of the NMOS transistors 15 and 16. Then, the high amplitude signal 8 is output from the drains of the PMOS transistor 14 and the NMOS transistor 16,
It is input to the gate of the bus driver circuit. The circuit of FIG. 4 has a circuit system in which the outputs of the drains of the other transistors are input to the gates of the transistors 13 and 14, and therefore, there are advantages that the speedup and the through current can be reduced.

FIG. 5 shows a concrete circuit example of another level conversion circuit used in the circuit configuration of the present invention. The circuit shown in FIG. 5 is a bootstrap circuit, which is composed of PMOS transistors 19, NMOS transistors 18, 20, and 21 and capacitors 23 and 23, and converts a low-amplitude signal into a high-amplitude signal. Figure 6
5 shows a schematic diagram of operation waveforms of the bootstrap circuit shown in FIG. The operation of the circuit will be described with reference to FIGS. 5 and 6. First, when IN1 changes from “High” to “Low”, the PMOS transistor 19 turns “ON” and the NMOS transistor
The transistor 21 turns off. At the same time, I
When N2 changes to "High", a high voltage is applied to the gate of the NMOS transistor 20, so that the NMOS transistor 20 is strongly "ON" and the output terminal rises to the low potential power supply 7. Next, after IN2 changes to "Low", the NMOS transistor 20 turns "OFF", and the OUT node is disconnected from the low potential power supply 7, IN3 changes to "Lo".
When w ”changes to“ High ”, the potential of the output terminal further increases by ΔV due to the influence of the capacitor 23. The rising voltage ΔV at this time is the capacitance value of the capacitor 23 and the load capacitance connected to the output terminal. Therefore, when the capacitance value of the capacitor 23 is sufficiently larger than the load capacitance of the output terminal, the potential rises to twice the low potential power source 7. However, if the capacitance value of the capacitor 23 is too large, A large amount of power is required to charge 23, which is an adverse effect in reducing power consumption.The level-converted high-amplitude signal 8 is input to the gate of the bus driver circuit.

FIG. 7 shows a specific circuit configuration of another level conversion circuit used in the circuit configuration of the present invention. The circuit shown in FIG. 7 is a level conversion circuit having a CMOS inverter configuration, and the PMOS transistor 2 having a high threshold voltage Vth.
4 and NMOS transistor 2 having a low threshold voltage Vth
It consists of 5. The source of the PMOS transistor 24 is connected to the high potential power supply 11. The low amplitude signal 1 is applied to the gates of the PMOS transistor 24 and the NMOS transistor 25.
Enter 2. By properly setting the Vth of the PMOS transistor 24, the power supply voltage of the circuit, and the amplitude of the low-amplitude signal,
A high-amplitude signal 8 equal to the high-potential power supply 11 is output to the output of the inverter. For example, the input low amplitude signal 12
When the "High" level of the PMOS transistor 24 is 1.5V and the high potential power source 11 is 2.5V, the Vt of the PMOS transistor 24 is
If h is 1 V or more, it functions as a level conversion circuit.
Here, a normal CM having a low Vth is used as the level conversion circuit.
When the OS inverter is used, the input "High"
Since the level electric potential is lower than the electric potential which is Vth lower than the source electric potential of the PMOS transistor, the PMOS transistor does not “OFF” and the through current always flows, and the power consumption increases. However, in this circuit, the PMOS transistor 2
4 has a high Vth, and the PMOS transistor 24 and the NMO
Since the S-transistor 25 does not turn “ON” at the same time, a shoot-through current can be prevented. Therefore, by using the circuit of the present invention, the level conversion circuit can be configured with a small number of elements. Here, in FIG. 7, the PMOS transistor 24
A PMOS transistor with high Vth is used as
Like the NMOS transistor 25, it is configured by using a transistor having a low Vth, and P by changing the substrate potential.
A method of changing the Vth of the MOS transistor 24 can be considered. Further, the PMOS transistor 24 having a low Vth
Even in the case of using, the levels shown in FIG. 7 can be converted to a higher potential by connecting the circuits shown in FIG. 7 in cascade.

Next, FIG. 8 shows a basic circuit configuration of another bus driver circuit used in the circuit configuration of the present invention. The bus driver circuit shown in FIG. 8 is a circuit applicable to a bus line that is not of the precharge type. Here, when the CMOS inverter circuit as shown in FIG. 8 is used for the bus driver circuit, there arises a problem that the driving capability of the PMOS transistor 26 is significantly reduced when the potential of the low potential power source 7 is low. This is because the potential difference between the source potential of the PMOS transistor 26 and the “Low” level of the input signal decreases when the power supply voltage decreases, and the current drive capability when the transistor is “ON” decreases due to the nature of the PMOS transistor. .. This problem can be solved by using a circuit configured as shown in FIG. The circuit shown in FIG. 9 has a configuration in which two NMOS transistors 29 and 30 are connected in series. The low voltage power supply 7 is connected to the drain of the NMOS transistor 29. In addition, an inverter 28 is arranged to control the gate of the NMOS transistor 29. The power source of the inverter 28 is connected to the high potential power source 11. The high potential amplitude signal 8 output from the level conversion circuit is input to the gates of the NMOS transistors 29 and 30. The reason why the speed can be increased by using the circuit shown in FIG. 9 is that the carrier mobility of the NMOS transistor is about three times higher than that of the PMOS transistor. Also, by applying a high voltage to the gate of the NMOS transistor, the potential between the gate and the source can be increased, and the transistor can be strongly turned “ON”. Conventionally, when the circuit shown in FIG. 9 is used for a bus driver circuit, since the drain potential of the NMOS transistor and the signal potential of the gate input are equal, the “High” level of the output potential of the circuit rises only up to the power supply voltage −Vth. There wasn't. Therefore, the output buffer such as a bus driver circuit of a low voltage circuit is unsuitable because the signal level is lowered. However, in the circuit configuration of the present invention, since a high-potential signal is input to the gate of the NMOS transistor 29, the potential drop of the power supply voltage -Vth does not occur and it can be used as a bus driver circuit or an output buffer for a low-voltage circuit. is there. Also, the CMOS that was used in the past
When an inverter is used, P
Although the gate-source potential of the MOS transistor becomes small and the driving capability is deteriorated, the circuit of FIG.
Since it is composed of an OS transistor and a high voltage is applied to the gate, the potential difference between the gate and the source is large, and there is no problem in lowering the driving capability due to the lowering of the power supply voltage. In FIG. 9, the inverter 28 is used to control the gate of the NMOS transistor 29, but the NMOS transistor 30 may be controlled by the inverter.

A second embodiment of the present invention is shown in FIG. FIG. 10 shows a circuit configuration of the logic LSI 31. The logic LSI 31 is usually composed of many functional blocks. In FIG. 10, functional blocks 35 to 38 are shown as a large number of functional blocks. Then, each functional block is supplied with a clock signal from the clock generation circuit 32 as a control signal. As described above, since a large number of functional blocks are connected to the output signal line 34 of the clock generation circuit, the load capacity is large. Therefore, the clock driver circuit has a large load capacity and the logic LSI 3
When the voltage of the whole 1 is lowered, the clock driver circuit 33
Delay causes problems. In particular, the clock signal in the logic LSI controls the entire LSI, and a reduction in the operating frequency of the clock signal leads to a reduction in the performance of the entire LSI. Here, as shown in FIG. 10, the output signal from the clock generation circuit is converted into a signal having a high signal amplitude by the level conversion circuit 5, and the signal is converted into the clock driver circuit 3.
By inputting to the gate of 3, it is possible to prevent the operating frequency of the clock signal from being lowered even when the voltage is low. in this way,
If the circuit of the present invention is used for a signal line having a large load capacity other than the bus line, the delay time can be shortened even when the voltage is low.

A third embodiment of the present invention is shown in FIG. FIG. 11 shows a part of the Booth encoder 40 and the Booth decoder 43 of the parallel type multiplier 39 using the secondary Booth algorithm. Booth encoder 4
Reference numeral 0 is a circuit for converting an input binary number into a code for calculation. The Booth decoder 43 is a circuit that calculates a partial product between two input signals. Here, considering a case where a multiplier of 8 × 8 bits is configured, a maximum of nine Booth decoder circuits 43 are connected to the output signal line 42 of the Booth encoder 40. Also, booth encoder 4
Since the output signal line 42 of 0 has a long wiring length, the load capacitance is considerably large. In the case of the 8 × 8 bit parallel type CMOS multiplier, the load capacitance per signal line of the Booth encoder is about 1 pF. For the above reason, when the voltage of the parallel type multiplier 39 is lowered, the delay of the output driver circuit 41 which outputs the signal of the Booth encoder 40 causes the speed reduction of the entire multiplier. Here, as shown in FIG. 11, if the output signal from the Booth encoder 40 is converted into a signal of high signal amplitude by the level conversion circuit 5 and the signal is input to the gate of the output driver circuit 41, even at low voltage. The delay time can be shortened. Thus, by using the circuit of the present invention for a signal line having a large load capacitance other than the bus line, the delay time can be shortened even when the voltage is low.

In the embodiment shown above, the potential 4 in the circuit is
4 and the input potential 45 of the driver circuit is a positive potential as shown in FIG. 12, and the low potential side of the signal is G
Only the case of the ND level and the high potential side of the signal is different has been described. However, the present invention can be applied even when the potential 44 in the circuit and the input potential 45 of the driver circuit are different from the above. For example, as shown in FIG. 13, even when the potential 44 in the circuit and the input potential 45 of the driver circuit are negative, and the high potential side of the signal is at the GND level and the low potential side of the signal is different, the present invention is applied. Applicable. In this case, the signal of the bus driver circuit input potential 45 is input to the gate of the PMOS transistor. Since the potential 44 in the circuit and the input potential 45 of the driver circuit are both negative potentials, the potential between the gate and the source is increased by applying a high amplitude signal of negative potential to the gate of the PMOS transistor. This is because the transistor can be strongly turned on. Further, such a level conversion circuit under a negative power supply voltage can obtain a desired output by reversing the polarities of the transistors.

FIG. 14 shows another example of setting the power supply voltage.
~ Fig. 17 can be considered. In FIG. 14, the potential 44 in the circuit
And the high potential side of the input potential 45 of the driver circuit is GN
It is shown that the potential 44 in the circuit changes in the range of + VDD to GND, and the input potential 45 of the driver circuit changes from + VDD to −VSS in agreement with the potential of + VDD higher than D. .. In this case, FIG.
The effect of the present invention can be obtained by configuring the circuit so that a high-amplitude signal of negative potential is input to the gate of the PMOS transistor as in the case of. In FIG. 15, the potential 44 in the circuit and the low potential side of the input potential 45 of the driver circuit match at −VSS, and the potential 44 in the circuit is −VSS.
To GND, the input potential 45 of the driver circuit changes.
Shows the case where it changes in the range of −VSS to + VDD. In this case, the effect of the invention can be obtained by inputting a high-amplitude signal to the gate of the NMOS transistor as described in detail in this embodiment. Further, as shown in FIGS. 16 and 17, when the potential 44 in the circuit changes within the range of GND to + VDD or −VSS to GND, the input potential 45 of the bus driver circuit is changed to −.
If the circuit is configured so as to change from VSS to + VDDH or −VSSL to + VDD, both the PMOS transistor and the NMOS transistor can be strongly turned “ON”. Therefore, even when a CMOS driver circuit is used, the effect of the present invention can be obtained. Can be expected. At this time, the potential of the substrate needs to be set to the highest potential or the lowest potential of the input potentials 45 of the driver circuit so as to prevent the leakage current.

Examples of power supply voltage used are shown in FIGS.
However, in the present invention, by applying a signal with a high amplitude to the input of the bus driver circuit than the potential in the circuit,
Regardless of which case the power supply voltage is used, the driving capability of the driver circuit is increased and the signal delay time is reduced.

[0021]

The present invention has the effect of reducing the delay time of the driver circuit by boosting the gate potential of the driver circuit that drives the signal line. For example, when the ratio of the delay time of the driver circuit in the circuit group operating in one machine cycle is small, the effect of improving the speed by the circuit of the present invention is small. However, when the ratio of the delay time of the driver circuit in one machine cycle is large, the effect of speed improvement by the circuit of the present invention is very large.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a conventional circuit configuration.

FIG. 3 is a diagram showing a specific circuit configuration of a bus driver circuit used in an embodiment of a semiconductor device according to the present invention.

FIG. 4 is a diagram showing a specific circuit configuration example of a level conversion circuit.

FIG. 5 is a diagram showing another specific circuit configuration example of the level conversion circuit.

6 is a schematic diagram of operation waveforms of the level conversion circuit shown in FIG.

FIG. 7 is a diagram showing another specific circuit configuration of the level conversion circuit.

FIG. 8 is a diagram showing a specific circuit configuration of a conventional bus driver circuit.

FIG. 9 is a diagram showing a specific circuit configuration of a bus driver circuit used in the circuit configuration of the present invention.

FIG. 10 is a diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 11 is a diagram showing a third embodiment of the semiconductor device according to the present invention.

FIG. 12 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

FIG. 13 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

FIG. 14 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

FIG. 15 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

FIG. 16 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

FIG. 17 is a diagram showing a potential of a signal amplitude used in an example of a semiconductor device according to the present invention.

[Explanation of symbols]

1 ... Function block 1 2 ... Function block 2 3 ... Bus line 4 ... Bus driver circuit 5 ... Level conversion circuit 6 ... Bus driver circuit 7 ... Low potential power supply 8 ... High amplitude signal 9 ... PMOS transistor 10 ... NMO
S transistor 11 ... High potential power supply 12 ... Low amplitude signal 13 ... PMOS transistor 14 ... PMO
S transistor 15 ... NMOS transistor 16 ... NMO
S transistor 17 ... Inverter 18 ... NMO
S transistor 19 ... PMOS transistor 20 ... NMO
S transistor 21 ... NMOS transistor 22 ... Capacitor 23 ... Capacitor 24 ... PMO
S transistor 25 ... NMOS transistor 26 ... PMO
S transistor 27 ... NMOS transistor 28 ... Inverter 29 ... NMOS transistor 30 ... NMO
S transistor 31 ... Logic LSI 32 ... Clock generation circuit 33 ... Clock driver circuit 34 ... Output signal line 35 ... Functional block 1 36 ... Functional block 2 37 ... Functional block 3 38 ... Functional block 4 39 ... Parallel multiplier 40 ... Booth Encoder 41 ... Output driver circuit 42 ... Output signal line 43 ... Booth decoder 44 ... Potential in circuit 45 ... Input potential of driver circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeo Kaku, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. In-house (72) Koichi Seki 1-280, Higashi Koikeku, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Mitsuru Hiraki, 1-280, Higashi Koikeku, Kokubunji, Tokyo, Hitachi, Central Research Center (72) Inventor Eigame Imaizumi 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd.

Claims (6)

[Claims] 1. A circuit having a plurality of circuit blocks, a signal line, and a driver circuit for the signal line, and transferring a signal from a signal source circuit block to another circuit block via the driver circuit and the signal line. In the semiconductor device according to the present invention, there is provided means for converting a low-amplitude signal in the circuit block that is the source of the signal into a high-amplitude signal that is larger than the power supply voltage of the circuit block and the driver circuit, and the converted signal is the driver. A semiconductor device characterized by being applied to an input of a circuit. 2. The semiconductor device according to claim 1, further comprising means for converting the high-amplitude signal into an input to a bus driver circuit for driving a bus line for transferring a signal between circuit blocks of an integrated circuit. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein the means for converting into the high-amplitude signal drives a clock signal line for supplying a clock signal from a clock generation circuit in a logic integrated circuit to a circuit block to be controlled. A semiconductor device provided for input to a clock driver circuit. 4. A semiconductor device according to claim 1, wherein the means for converting into the high-amplitude signal, an output driver circuit for giving a signal output from an encoder of a parallel multiplier in an arithmetic integrated circuit to a decoder via an output signal line. A semiconductor device characterized in that it is prepared for input to. 5. The semiconductor device according to claim 1, wherein the means for converting into the high-amplitude signal comprises:
A CM inverter circuit connected between voltage power supplies that provide the voltage level of the high-amplitude signal;
The OS inverter circuit includes a series configuration of a first-conductivity-type MOS transistor and a second-conductivity-type MOS transistor, which has a configuration in which gates are connected to each other for input and drains are connected to each other for output. And the first conductivity type MO
The threshold voltage of the S transistor is high, and the second conductivity type MO
The threshold voltage of the S transistor is low, the threshold voltage of the first conductivity type MOS transistor is low, the threshold voltage of the second conductivity type MOS transistor is high, or the first conductivity type MOS transistor and the second conductivity type. Shaped MOS
A semiconductor device comprising a structure in which both threshold voltages of transistors are set high. 6. The semiconductor device according to claim 1, wherein a driver circuit for driving the signal line by applying the high-amplitude signal to an input is a MOS between low-voltage power supplies of the driver circuit. It includes a series configuration in which transistors are connected in series. The series configuration is configured such that the source of one MOS transistor is connected to the drain of the other MOS transistor to provide an output, and the gate inputs of both transistors have one input to the other. On the other hand, the semiconductor device is characterized in that it has an inverting input and applies the high-amplitude signal to the both inputs.