JPH08316638A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH08316638A
JPH08316638A JP7115570A JP11557095A JPH08316638A JP H08316638 A JPH08316638 A JP H08316638A JP 7115570 A JP7115570 A JP 7115570A JP 11557095 A JP11557095 A JP 11557095A JP H08316638 A JPH08316638 A JP H08316638A
Authority
JP
Japan
Prior art keywords
wiring
conductors
conductor
wiring board
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7115570A
Other languages
Japanese (ja)
Inventor
Kenichi Aihara
憲一 合原
Takashi Okunosono
隆志 奥ノ薗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7115570A priority Critical patent/JPH08316638A/en
Publication of JPH08316638A publication Critical patent/JPH08316638A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: To provide a multilayer wiring board which can effectively prevent wiring conductors or through-hole conductors from occurring circuit brake and ensure electronic connection of each electronic part mounted on an insulating body. CONSTITUTION: A multilayer wiring board is comprised of wiring conductive bodies 2 which are arranged in multilayer in an insulating unit 1 made of ceramic sintered body, and wiring conductors 2 connected by through-hole conductors 3. The wiring conductors 2 and the through-hole conductors 3 are made of only one of tungsten, molybdenum or manganese and the cross section of the through-hole conductors 3 are over 30% of the cross section of the wiring conductors 2 in lateral direction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子やコンデン
サ、抵抗器等の電子部品が搭載される多層配線基板に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board on which electronic parts such as semiconductor elements, capacitors and resistors are mounted.

【0002】[0002]

【従来の技術】従来、多層配線基板、特に配線導体の導
通抵抗を低抵抗とした多層配線基板は一般に酸化アルミ
ニウム質焼結体等の電気絶縁性のセラミック質焼結体か
ら成る絶縁基体の内部及び表面にタングステン、モリブ
デン、マンガン等の高融点金属粉末から成る複数個の配
線導体を多層に配設するとともに各配線導体を絶縁基体
内に設けたタングステン、モリブデン、マンガン等の高
融点金属粉末から成るスルーホール導体で接続した構造
を有しており、絶縁基体の上面に半導体素子やコンデン
サ、抵抗器等の電子部品を搭載させるととも該電子部品
の電極を半田を介して配線導体に接続させることによっ
て絶縁基体上面に搭載された各電子部品はその各々が配
線導体を介して電気的に接続されるようになっている。
2. Description of the Related Art Conventionally, a multi-layer wiring board, particularly a multi-layer wiring board in which the conduction resistance of a wiring conductor is low, is generally an insulating base made of an electrically insulating ceramic sintered body such as an aluminum oxide sintered body. And a plurality of wiring conductors made of refractory metal powder such as tungsten, molybdenum, manganese, etc. on the surface are provided in multiple layers and each wiring conductor is provided in an insulating substrate. It has a structure in which it is connected by a through-hole conductor, and electronic components such as semiconductor elements, capacitors, and resistors are mounted on the upper surface of an insulating substrate, and the electrodes of the electronic component are connected to wiring conductors via solder. As a result, the electronic components mounted on the upper surface of the insulating substrate are electrically connected to each other via the wiring conductors.

【0003】尚、かかる従来の多層配線基板は通常、セ
ラミックスの積層技術及びスクリーン印刷等の厚膜技術
を採用することによって製作されており、具体的には以
下の方法によって製作されている。
Incidentally, such a conventional multilayer wiring board is usually manufactured by adopting a ceramics stacking technique and a thick film technique such as screen printing. Specifically, it is manufactured by the following method.

【0004】即ち、 (1) まず、酸化アルミニウム、酸化珪素、酸化マグネシ
ウム等の原料粉末に適当な有機バインダー、可塑剤、溶
剤を添加混合して泥漿状となすとともにこれを従来周知
のドクターブレード法やカレンダーロール法等のテープ
成形技術を採用して複数枚のセラミックグリーンシート
(セラミック生シート)を得、しかる後、各セラミック
グリーンシートの所定位置に穴あけ加工法によりスルー
ホールを形成する。
That is, (1) First, an appropriate organic binder, a plasticizer, and a solvent are added to and mixed with a raw material powder of aluminum oxide, silicon oxide, magnesium oxide or the like to form a sludge, and this is formed by a conventionally known doctor blade method. A plurality of ceramic green sheets (ceramic green sheets) are obtained by using a tape forming technique such as a calender roll method or the like, and then through holes are formed at predetermined positions of each ceramic green sheet by a drilling method.

【0005】(2) 次にタングステン、モリブデン等の高
融点金属粉末に適当な有機バインダー、可塑剤、溶剤を
添加混合して金属ペーストを得るとともに該金属ペース
トをスクリーン印刷法を採用することによって前記セラ
ミックグリーンシートの表面に所定パターンに印刷塗布
するとともに各セラミックグリーンシートのスルーホー
ル内に充填する。
(2) Next, a suitable organic binder, a plasticizer, and a solvent are added to and mixed with a refractory metal powder such as tungsten and molybdenum to obtain a metal paste, and the metal paste is screen-printed to obtain the metal paste. The surface of each ceramic green sheet is printed and applied in a predetermined pattern, and the through holes of each ceramic green sheet are filled.

【0006】(3) そして最後に表面及びスルーホールに
金属ペーストが塗布充填されたセラミックグリーンシー
トを上下に積層し、しかる後、これを還元雰囲気中もし
くは中性雰囲気中、約1600℃の温度で焼成すること
によって製品としての多層配線基板が完成する。
(3) Finally, ceramic green sheets whose surfaces and through holes are coated and filled with a metal paste are laminated one on top of the other, and thereafter, in a reducing atmosphere or a neutral atmosphere, at a temperature of about 1600 ° C. By firing, a multilayer wiring board as a product is completed.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この従
来の配線基板は配線導体及びスルーホール導体を形成す
るタングステン、モリブデンの電気抵抗値が4×10-6
Ω・cm〜8×10-6Ω・cmと高いこと、配線導体の
幅方向の断面積は一般に250×10-3mm2 〜750
×10-3mm2 であるのに対し、スルーホール導体の断
面積が2×10-3mm2 〜70×10-3mm2 と狭いこ
と等から配線導体及びスルーホール導体を介して各電子
部品に電気信号を流した場合、スルーホール導体に電気
が流れる際に大きなジュール発熱が発生し、これが絶縁
基体を局部的に加熱して絶縁基体にクラックや割れを発
生させてしまい、その結果、絶縁基体に取着されている
配線導体に断線等が招来し、絶縁基体上面に搭載されて
いる各電子部品の電気的接続の信頼性が低いものとなる
欠点を有していた。
However, in this conventional wiring board, the electric resistance value of tungsten and molybdenum forming the wiring conductor and the through-hole conductor is 4 × 10 −6.
Ω · cm to 8 × 10 −6 Ω · cm, and the cross-sectional area of the wiring conductor in the width direction is generally 250 × 10 −3 mm 2 to 750.
× 10 to -3 of a mm 2, each via a wiring conductor and the through-hole conductors from such that the cross-sectional area of the through-hole conductors is small and 2 × 10 -3 mm 2 ~70 × 10 -3 mm 2 electrons When an electric signal is applied to a component, a large amount of Joule heat is generated when electricity flows through the through-hole conductor, which locally heats the insulating base material and causes cracks or breaks in the insulating base material. The wiring conductor attached to the insulating substrate has a drawback that the wiring conductor is broken and the electrical connection of each electronic component mounted on the upper surface of the insulating substrate becomes unreliable.

【0008】[0008]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は配線導体やスルーホール導体に断線が招
来するのを有効に防止し、絶縁基体に搭載される各電子
部品の電気的接続を確実となすことができる多層配線基
板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent disconnection from occurring in a wiring conductor or a through-hole conductor, and to prevent the electronic components mounted on an insulating substrate from being broken. It is an object of the present invention to provide a multilayer wiring board capable of ensuring electrical connection.

【0009】[0009]

【課題を解決するための手段】本発明はセラミック質焼
結体から成る絶縁基体内に、複数個の配線導体を多層に
配設するとともに該各配線導体をスルーホール導体を介
して接続して成る多層配線基板であって、前記配線導体
及びスルーホール導体をタングステン、モリブデン、マ
ンガンの少なくとも1種で形成するとともにスルーホー
ル導体の断面積を配線導体の幅方向の断面積に対し30
%以上としたことを特徴とするものである。
According to the present invention, a plurality of wiring conductors are arranged in multiple layers in an insulating substrate made of a ceramic sintered body, and the respective wiring conductors are connected through through-hole conductors. In the multilayer wiring board, the wiring conductor and the through-hole conductor are formed of at least one of tungsten, molybdenum, and manganese, and the cross-sectional area of the through-hole conductor is 30 with respect to the cross-sectional area in the width direction of the wiring conductor.
% Or more.

【0010】[0010]

【作用】本発明の多層配線基板によれば、各配線導体を
接続するスルーホール導体の断面積を各配線導体の幅方
向の断面積に対し30%以上と広くしたことからスルー
ホール導体に電気が流れても該スルーホール導体におい
て大きなジュール発熱が発生することはなく、その結
果、絶縁基体に局部加熱によるクラックや割れ等の発生
はなく、これによって絶縁基体に取着されている配線導
体に断線等を招来することが有効に防止されて絶縁基体
上面に搭載されている各電子部品を配線導体及びスルー
ホール導体を介して確実に電気的接続することが可能と
なる。
According to the multilayer wiring board of the present invention, the cross-sectional area of the through-hole conductor connecting each wiring conductor is set to 30% or more of the cross-sectional area of each wiring conductor in the width direction. Does not generate a large amount of Joule heat in the through-hole conductor, and as a result, there is no occurrence of cracks or breaks in the insulating base due to local heating, and thus the wiring conductor attached to the insulating base is prevented. It is possible to effectively prevent the disconnection and the like, and it is possible to reliably electrically connect the electronic components mounted on the upper surface of the insulating substrate through the wiring conductor and the through-hole conductor.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の多層配線基板の一実施例を示し、1
は絶縁基体、2は配線導体、3はスルーホール導体であ
る。
The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of the multilayer wiring board of the present invention.
Is an insulating substrate, 2 is a wiring conductor, and 3 is a through-hole conductor.

【0012】前記絶縁基体1は酸化アルミニウム質焼結
体やムライト質焼結体、窒化アルミニウム質焼結体、ガ
ラスセラミックス焼結体等のセラミック質焼結体で形成
されており、その上面に半導体素子やコンデンサ、抵抗
器等の電子部品4が搭載される。
The insulating substrate 1 is formed of a ceramic sintered body such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body or a glass ceramic sintered body, and a semiconductor is formed on the upper surface thereof. Electronic components 4 such as elements, capacitors, and resistors are mounted.

【0013】前記絶縁基体1はその内部及び表面に複数
個の配線導体2が多層に形成されており、各配線導体2
は絶縁基体1内に設けたスルーホール導体3を介して電
気的に接続されている。
The insulating substrate 1 has a plurality of wiring conductors 2 formed in multiple layers inside and on the surface thereof.
Are electrically connected via a through-hole conductor 3 provided in the insulating substrate 1.

【0014】前記配線導体2及びスルーホール導体3は
絶縁基体1の上面に搭載される各電子部品4同士を相互
に電気的に接続するとともに各電子部品4を外部電気回
路に電気的に接続する作用を為し、タングステン、モリ
ブデン、マンガンの少なくとも1種で形成されている。
The wiring conductor 2 and the through-hole conductor 3 electrically connect the electronic components 4 mounted on the upper surface of the insulating substrate 1 to each other and also electrically connect the electronic components 4 to an external electric circuit. It acts and is formed of at least one of tungsten, molybdenum, and manganese.

【0015】また前記各配線導体2を電気的に接続する
スルーホール導体3はその断面積が各配線導体2の幅方
向の断面積に対し30%以上となっており、スルーホー
ル導体3の断面積が広いことからスルーホール導体3に
電気が流れても大きなジュール発熱を発生することはな
く、その結果、絶縁基体1に局部加熱によるクラックや
割れ等の発生がなく、これによって絶縁基体1に取着さ
れている配線導体2に断線等を招来することは有効に防
止され、絶縁基体1上面に搭載されている各電子部品4
を配線導体2及びスルーホール導体3を介して確実に電
気的接続することが可能となる。
The cross-sectional area of the through-hole conductor 3 for electrically connecting the wiring conductors 2 is 30% or more of the cross-sectional area of each wiring conductor 2 in the width direction. Since the area is large, even if electricity flows through the through-hole conductor 3, a large amount of Joule heat is not generated, and as a result, there is no occurrence of cracks or fractures due to local heating in the insulating base body 1. It is effectively prevented that the attached wiring conductor 2 is broken, and each electronic component 4 mounted on the upper surface of the insulating substrate 1 is prevented.
Can be surely electrically connected via the wiring conductor 2 and the through-hole conductor 3.

【0016】尚、前記スルーホール導体3はその断面積
が各配線導体2の幅方向の断面積に対し30%未満とな
るとスルーホール導体3の断面積が狭くなり、電気が流
れると大きなジュール発熱を起こして絶縁基体1にクラ
ックや割れ等を発生してしまう。従って、前記スルーホ
ール導体3はその断面積が各配線導体2の幅方向の断面
積に対し30%以上に特定される。
When the cross-sectional area of the through-hole conductor 3 is less than 30% of the cross-sectional area of each wiring conductor 2 in the width direction, the cross-sectional area of the through-hole conductor 3 becomes narrow, and a large amount of Joule heat is generated when electricity flows. And the insulating substrate 1 is cracked or broken. Therefore, the cross-sectional area of the through-hole conductor 3 is specified to be 30% or more of the cross-sectional area of each wiring conductor 2 in the width direction.

【0017】また前記配線導体2のうち絶縁基体1の上
面に形成されたものはその露出表面に更にニッケル、金
等の耐蝕性に優れ、且つ良導電性の金属をメッキ法によ
り1.0乃至20.0μmの厚みに被着させておくと、
配線導体2の酸化腐食が有効に防止されるとともに配線
導体2と電子部品4との電気的接続が良好となる。従っ
て、前記配線導体2のうち絶縁基体1の上面に形成され
たものはその露出表面に更にニッケル、金等の耐蝕性に
優れ、且つ良導電性の金属をメッキ法により1.0乃至
20.0μmの厚みに被着させておくことが好ましい。
Of the wiring conductors 2 formed on the upper surface of the insulating substrate 1, the exposed surface thereof is further plated with a metal having excellent corrosion resistance such as nickel and gold and having a good conductivity by plating. If it is applied to a thickness of 20.0 μm,
Oxidation corrosion of the wiring conductor 2 is effectively prevented, and the electrical connection between the wiring conductor 2 and the electronic component 4 is improved. Therefore, of the wiring conductors 2 formed on the upper surface of the insulating substrate 1, the exposed surface thereof is coated with a metal having excellent corrosion resistance such as nickel or gold and having a good conductivity by 1.0 to 20. It is preferable to deposit it to a thickness of 0 μm.

【0018】かくして上述の多層配線基板によれば絶縁
基体1の上面に半導体素子やコンデンサ、抵抗器等の電
子部品4を搭載するとともに各電子部品4の電極、端子
を半田等を介して配線導体2に接続すれば、絶縁基体1
の上面に搭載される半導体素子やコンデンサ等の電子部
品4はその各々が配線導体2及びスルーホール導体3を
介して電気的に接続され、これによって所定の電気回路
を形成することとなる。
Thus, according to the above-mentioned multilayer wiring board, electronic components 4 such as semiconductor elements, capacitors, and resistors are mounted on the upper surface of the insulating substrate 1, and electrodes and terminals of each electronic component 4 are wired via solder or the like. Insulating substrate 1 if connected to 2
The electronic components 4 such as semiconductor elements and capacitors mounted on the upper surface of each are electrically connected to each other via the wiring conductors 2 and the through-hole conductors 3, thereby forming a predetermined electric circuit.

【0019】次に上述の多層配線基板の製造方法につい
て図2(a)乃至(c)に基づき説明する。
Next, a method of manufacturing the above-mentioned multilayer wiring board will be described with reference to FIGS. 2 (a) to 2 (c).

【0020】先ず、図2(a)に示す如く3枚のセラミ
ックグリーンシート10a 、10b 、10c を準備するととも
にセラミックグリーンシート10a 、10b の所定位置にス
ルーホールa を形成する。
First, as shown in FIG. 2A, three ceramic green sheets 10a, 10b and 10c are prepared and through holes a are formed at predetermined positions of the ceramic green sheets 10a and 10b.

【0021】前記セラミックグリーンシート10a 、10b
、10c は例えば多層配線基板の絶縁基体が酸化アルミ
ニウム質焼結体で形成されている場合には、酸化アルミ
ニウム、酸化珪素、酸化マグネシウム、酸化カルシウム
等の原料粉末に適当な有機バインダー、可塑剤、溶剤を
添加混合して泥漿状となし、しかる後、前記泥漿物を従
来周知のドクターブレード法やカレンダーロール法等を
採用し、シート状に成形することによって形成される。
The ceramic green sheets 10a and 10b
, 10c is, for example, when the insulating substrate of the multilayer wiring board is formed of an aluminum oxide sintered body, an organic binder, a plasticizer, or a suitable organic binder for the raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. It is formed by adding a solvent and mixing it to form a sludge, and then forming the sludge into a sheet by using a conventionally known doctor blade method, calender roll method or the like.

【0022】また前記セラミックグリーンシート10a 、
10b へのスルーホールa の形成はセラミックグリーンシ
ート10a 、10b に従来周知のプレス孔開け加工法により
所定径の貫通孔を開けることによって各セラミックグリ
ーンシート10a 、10b の所定位置に形成される。
Further, the ceramic green sheet 10a,
The through holes a are formed in the ceramic green sheets 10a, 10b by forming through holes having a predetermined diameter in the ceramic green sheets 10a, 10b by a conventionally known press punching method.

【0023】次に図2(b)に示す如く、前記各セラミ
ックグリーンシート10a 、10b 、10c の各々の表面に金
属ペーストを所定パターンに被着させて配線導体パター
ン20を形成し、同時にスルーホールa 内に金属ペースト
を充填させてスルーホール用導体層21を形成する。
Next, as shown in FIG. 2B, a metal paste is applied in a predetermined pattern on the surface of each of the ceramic green sheets 10a, 10b, 10c to form a wiring conductor pattern 20, and at the same time, through holes are formed. The conductor layer 21 for through holes is formed by filling the inside of a with a metal paste.

【0024】前記配線導体パターン20及びスルーホール
用導体層21を形成する金属ペーストはタングステン、モ
リブデン、マンガンの少なくとも1種から成る高融点金
属粉末に適当な有機バインダー、可塑剤、溶剤を添加混
合し、ペースト状となすことによって形成される。
The metal paste for forming the wiring conductor pattern 20 and the through-hole conductor layer 21 is obtained by adding a suitable organic binder, a plasticizer and a solvent to a refractory metal powder made of at least one of tungsten, molybdenum and manganese and mixing them. It is formed by forming a paste.

【0025】また前記配線導体パターン20及びスルーホ
ール用導体層21の形成は金属ペーストをセラミックグリ
ーンシート10a 、10b 、10c の各々の表面にスクリーン
印刷法により印刷塗布することによって行われる。
The wiring conductor pattern 20 and the through-hole conductor layer 21 are formed by printing and applying a metal paste on the surface of each of the ceramic green sheets 10a, 10b and 10c by a screen printing method.

【0026】次に前記表面に配線導体パターン20が形成
され、スルーホールa 内にスルーホール用導体層21が充
填された各セラミックグリーンシート10a 、10b 、10c
を図2(c)に示す如く、各セラミックグリーンシート
10a 、10b 、10c 表面に形成させた配線導体パターン20
がセラミックグリーンシート10a 、10b のスルーホール
a内に充填させたスルーホール用導体層21で電気的に接
続されるようにして上下に積層し積層体Lを形成する。
Next, each of the ceramic green sheets 10a, 10b, 10c, in which the wiring conductor pattern 20 is formed on the surface and the through-hole conductor layer 21 is filled in the through-hole a.
As shown in Fig. 2 (c), each ceramic green sheet
Wiring conductor pattern 20 formed on the surface of 10a, 10b, 10c
Are laminated vertically so as to be electrically connected by the through-hole conductor layer 21 filled in the through-holes a of the ceramic green sheets 10a and 10b to form a laminated body L.

【0027】そして最後に前記積層体Lを還元雰囲気
中、約1600℃の温度で焼成し、各セラミックグリー
ンシート10a 、10b 、10c と配線導体パターン20とスル
ーホールa内に充填したスルーホール用導体層21とを焼
結一体化することによって図1に示す絶縁基体1の内部
及び表面にスルーホール導体3によって電気的に接続さ
れている配線導体2を配設した製品としての多層配線基
板が完成する。
Finally, the laminated body L is fired in a reducing atmosphere at a temperature of about 1600 ° C., and the ceramic green sheets 10a, 10b, 10c, the wiring conductor pattern 20, and the through-hole conductor filled in the through-hole a. By sintering and integrating the layer 21, a multilayer wiring board as a product having wiring conductors 2 electrically connected by through-hole conductors 3 inside and on the surface of the insulating substrate 1 shown in FIG. 1 is completed. To do.

【0028】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

【0029】[0029]

【発明の効果】本発明の多層配線基板によれば、各配線
導体を接続するスルーホール導体の断面積を各配線導体
の幅方向の断面積に対し30%以上と広くしたことから
スルーホール導体に電気が流れても該スルーホール導体
において大きなジュール発熱が発生することはなく、そ
の結果、絶縁基体に局部加熱によるクラックや割れ等の
発生はなく、これによって絶縁基体に取着されている配
線導体に断線等を招来することが有効に防止されて絶縁
基体上面に搭載されている各電子部品を配線導体及びス
ルーホール導体を介して確実に電気的接続することが可
能となる。
According to the multilayer wiring board of the present invention, the cross-sectional area of the through-hole conductor connecting the wiring conductors is set to 30% or more of the cross-sectional area in the width direction of each wiring conductor. No large Joule heat is generated in the through-hole conductor even when electricity is applied to the through-hole conductor, and as a result, there is no occurrence of cracks or cracks in the insulating base due to local heating, and the wiring attached to the insulating base is thereby prevented. It is possible to effectively prevent the conductor from being broken, and it is possible to reliably electrically connect the electronic components mounted on the upper surface of the insulating substrate via the wiring conductor and the through-hole conductor.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多層配線基板の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing an embodiment of a multilayer wiring board of the present invention.

【図2】(a)乃至(c)は図1に示す多層配線基板の
製造方法を説明するための各工程毎の断面図である。
2A to 2C are cross-sectional views in each step for explaining a method of manufacturing the multilayer wiring board shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・・・・・・・・・絶縁基体 2・・・・・・・・・・・・・配線導体 3・・・・・・・・・・・・・スルーホール導体 4・・・・・・・・・・・・・電子部品 1 ... Insulating substrate 2 ... Wiring conductor 3 ... Through-hole conductor 4 ..... electronic components

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミック質焼結体から成る絶縁基体内
に、複数個の配線導体を多層に配設するとともに該各配
線導体をスルーホール導体を介して接続して成る多層配
線基板であって、前記配線導体及びスルーホール導体を
タングステン、モリブデン、マンガンの少なくとも1種
で形成するとともにスルーホール導体の断面積を配線導
体の幅方向の断面積に対し30%以上としたことを特徴
とする多層配線基板。
1. A multi-layer wiring board comprising a plurality of wiring conductors arranged in multiple layers in an insulating substrate made of a ceramic sintered body, and the wiring conductors being connected via through-hole conductors. A multilayer structure in which the wiring conductor and the through-hole conductor are formed of at least one of tungsten, molybdenum, and manganese, and the cross-sectional area of the through-hole conductor is 30% or more of the cross-sectional area in the width direction of the wiring conductor. Wiring board.
JP7115570A 1995-05-15 1995-05-15 Multilayer wiring board Pending JPH08316638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7115570A JPH08316638A (en) 1995-05-15 1995-05-15 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7115570A JPH08316638A (en) 1995-05-15 1995-05-15 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH08316638A true JPH08316638A (en) 1996-11-29

Family

ID=14665839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7115570A Pending JPH08316638A (en) 1995-05-15 1995-05-15 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH08316638A (en)

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