JPH08307170A - High frequency amplifier circuit - Google Patents

Abstract

PURPOSE: To attain a wide band and low power consumption by forming the amplifier circuit with a drive stage of a low voltage and a high voltage output stage to apply a drive voltage to a load and providing a multiplexer with buffer to select any of plural drive signals to the drive stage. CONSTITUTION: The amplifier circuit is made up of a low voltage drive stage 80 and a high voltage amplification output stage 70 and the drive stage 80 and the high voltage output stage 70 are connected to form a cascode amplifier. The low voltage drive stage 80 is made up of an LSI of complementary bipolar transistors (TRs) and configured with a 2-input multiplexer with buffer at an input stage, a voltage/current (V/I) conversion circuit 20 having a conversion impedance Zx connecting to the output of the multiplexer and a gain controller 31 using a multiplier function at its next stage. Through the configuration above, an equivalent load of the amplifier output is relieved and most of the circuits are operated in the current mode, then the operation at a high speed for a broad frequency band is attained.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a complementary transistor circuit, an amplifier using the complementary transistor circuit (particularly, a video amplifier for amplifying a video signal), and a CR.
The present invention relates to a T display device, and more particularly to providing an element circuit and a system suitable for high definition and low power consumption of a CRT display device.

[0002]

2. Description of the Related Art A high-definition CRT display device known as a so-called CRT display device for a computer has been changed from a 1M pixel display, which is currently mainstream, to a 2M pixel display.
There is a demand for higher definition to 4M pixels, and accordingly, the video amplification system is changed from 100MHz to 150MHz, 300
It is becoming increasingly necessary to increase the bandwidth to MHz. Further, since the output requires a large amplitude of 40 to 50 Vpp and a DC bias level of 100 V, high precision and low power consumption are also required.

A video amplifier which is one of the main objects of the present invention is described in, for example, Japanese Patent Application Laid-Open No. 61-228778, "Amplification Circuit" by the inventors including a part of the present inventors. Discloses a high voltage cascode amplifier driven by a monolithic stage that includes functions such as a video multiplexer, a gain controller, a current amplifier and the like.

In US Pat. No. 4,494,075, one of the current mirrors having the opposite polarity on the load side of the multiplier is formed as a Darlington circuit, and the V _{BE of} the current mirror changes in accordance with a change in the signal current, causing distortion. Are described. US Pat. No. 4,293,875 describes a video amplifier of a type in which a cathode of a CRT is driven by a complementary transistor push-pull circuit using a bias circuit with a level shift. Further, US Pat. No. 4,051,521 describes a composite signal video amplifier which drives a high voltage cascode amplifier with a low voltage complementary emitter follower amplifier.

Further, "New Low Frequency High Frequency Circuit Design Manual", CQ Publishing, 1988, 4, 30 first edition) p2
Nos. 58 to 259 describe a device using a complementary transistor circuit as a differential analog switch.

A relatively recent research result of a wideband video amplification system of a high-definition CKT display device has been described in 1989 as a model for performing high-precision high-frequency output stage feedback. Solid State Circuit Conference Digest of Technical Papers, pp. 70-71 (19
89 IEEE International Solid-State Circuits Conf
erence Digest of Technical Papers pp. 70-71 (Fe
b.1989)). Further, for the cascode type that does not perform high-frequency feedback from the high-frequency output stage, see IEE Transaction on Consumer Electronics Vol. 34,
No. 3, August 1989, pages 426 to 433 (IEEE Tran
sactionson Consumer Electronics, Vol. 34, No.
3, AUGUST 1988 pp. 426-433).

[0007]

SUMMARY OF THE INVENTION Here, the above-mentioned Japanese Patent Laid-Open No.
Although the prior art described in -228778 can satisfy the function requirements, sufficient consideration is not given to simplification of each functional circuit and reduction of the number of amplification stages, and the circuit configuration becomes complicated, and future There is a problem that is difficult to cope with the widening of the operating frequency. In addition, although the above-mentioned USP3 documents and differential analog switch documents individually describe element technologies such as complementary transistor circuits, like the present invention, complementary transistor circuits are used as gain controllers for video amplifiers and Nothing is mentioned about simplification by fully using it for a current mirror circuit or the like in the output stage.

Further, among the above-mentioned prior arts, the high-frequency negative feedback method has a shortage of gain margin and phase margin at high frequencies due to the delay of a single loop of the circuit, causing unstable phenomena such as oscillation to appear, and a high voltage output. The negative feedback loop from the stage itself becomes a load on the amplifier and consumes high-frequency power, thus limiting broadband operation.

In the cascode amplification method of the above-mentioned prior art, the high-frequency signal negative feedback path from the output stage can be omitted by maintaining the signal current of the cascode stage with high precision. Since the problem of instability can be avoided, a wider band can be achieved. However, even in the cascode method, a negative feedback path for direct current reproduction for generating a reference direct current voltage corresponding to the back porch point of the video signal in the amplifier output voltage cannot be omitted, and therefore the feedback connected to the high voltage high bandwidth output stage is still available. Since the road remains and becomes a load, it is a limiting factor for wide band and low power consumption. The reason is that the high-precision feedback resistor connected to the high-voltage output stage is large in size to withstand relatively large power consumption and large in power consumption (∝ΔCV ² f) due to its parasitic capacitance. The parasitic load (for example, 1 to 2 PF) corresponds to the cathode load capacitance (for example, 4 to 6 P) of a high-definition CRT.
F) tends to decrease year by year due to technological progress, resulting in an increase in the ratio.

An object of the present invention is to provide a high frequency amplifier circuit having a wide band and low power consumption.

[0011]

A feature of the present invention for achieving the above object is to provide a low-voltage drive stage which inputs a plurality of drive signals for driving a load and generates a drive current for the load. , A high voltage output stage that amplifies the drive current by high voltage and supplies the drive voltage to the load, and the low voltage drive stage comprises a buffered multiplexer for selecting one of the plurality of drive signals, The buffered multiplexer is
A first differential stage composed of a pair of npn transistors, a constant current circuit for current biasing provided on the common emitter side thereof, and a first differential stage and a pair of pnp transistors of interest. It is composed of a second differential stage and a constant current circuit for current bias provided on the common emitter side, and the base of one of the pnp transistors forming the second differential stage has the first difference. The emitter output of the moving stage is p
The output of another differential stage is connected to the base of the np transistor, and the base of one of the npn transistors forming the first differential stage is controlled as an input terminal and the base of the other npn transistor is controlled. The terminal is used, and the common emitter of the second differential stage is used as the output terminal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

First, the overall circuit system will be described, and then a detailed circuit modification will be described.

FIG. 1 is a circuit block diagram of an indirect feedback video amplifier of the present invention and a CRT display device using the same.

The video amplifier in FIG. 1 comprises a low-voltage driving stage 80 and a high-voltage amplification output stage 70, each of which is constituted by a complementary bipolar transistor LSI circuit.
The driving stage 80 and the high voltage output stage 70 are connected to form a cascode amplifier.

An analog video signal is applied to the input of the low-voltage drive LSI 80 from a signal source E _S via a 75Ω terminating resistor R _S and a large-capacity coupling capacitor C _Xi .
The output of the high voltage output stage 70 is connected to the cathode electrode of the CRT via a bias voltage source 75 for brightness control, and the video signal applied to the input terminal T11 of the drive stage LSI 80 is amplified and the cathode electrode of the CRT is amplified. It drives and displays a CRT according to the applied signal.

The drive stage LSI 80 is made of a complementary bipolar transistor LSI, and its configuration is a voltage / current having a conversion impedance Z _x connected to the 2-input buffered multiplexer 10 of the input stage and its output side. The (V / I) conversion circuit 20 is further connected to the gain controller 31 having a multiplication function.
The gain controller 31 is _supplied with a control voltage from the resistor R _G2 via the control circuit 32 and the resistor R _G1 .

The output of the gain controller 31 has two current outputs of opposite phases to each other. The output is subtracted by the auxiliary current mirror amplifier 40 and is connected so as to drive the output stage current mirror amplifiers 51 to 54. There is.

The feedback current mirror amplifier 69 is connected to a 5V power supply V _CC via the external resistor R _F, its output sampling switch 61, a capacitor C _X2, amplifier 62, via a resistor R80, R90 input Are connected so as to be negatively fed back.

The outputs of the output stage current mirror amplifiers 51-54 are combined and connected to the cascode high voltage output stage 70. The high voltage output stage 70 is composed of a cascode circuit including a high voltage power transistor 71, a diode 72 and a load resistance R _L and a buffer amplifier including transistors 73 and 74.

The video amplifier configured as described above is an inverting amplifier of a high voltage output with a gain of about 100 times, and the input / output gain can be expressed by the following relationship.

[0022]

[Equation 1]

Here, Z _X is the external impedance of the V / I converter, R _L is the load resistance of the cascode high-voltage output stage, and K is the gain of the video LSI, which varies according to the control voltage of the gain controller.

As shown in FIGS. 2 (a) and 2 (b), the video input signal is given as an AC signal with a maximum of about 1 V _PP , while the output signal for controlling the cathode of the CRT is a high DC voltage. Since it is necessary to provide the voltage as a superimposed DC signal, it is necessary to reproduce a stable and accurate DC component. This reference DC level has the waveforms shown in FIGS.
This is done at the point indicated as the back porch after the horizontal sync pulse. The operation of the embodiment of the present invention shown in FIG. 1 is performed as follows.

When a periodic sampling pulse at the time of the back porch is applied to the sampling control terminal T61 of the sample and hold switch 61 in FIG. 1, the feedback voltage from the feedback current mirror circuit 69 changes to the sampling switch 6.
1, the capacitor C _{X2 of the} hold circuit is charged, and is fed back to the input via the amplifier 62 and the bias resistor R89. The DC loop gain of this feedback loop is several hundred times. Since this feedback is a negative feedback for feeding back the voltage drop due to the external resistor R _F12 of the positive phase current mirror 69, the amplifier settles to a constant value after a time sufficiently longer than the time constant of C _X1 · R 89 of the input stage. . The current of the output stage current mirror at this time is I _O , and the current of the feedback current mirror is I _O
/ N, the DC voltage of the high voltage output stage is V _O , the feedback voltage from the feedback current mirror is V _F , the power source voltage of the high voltage stage is V _H , and the power source voltage of the low voltage stage is V _CC . A relationship is established.

[0026]

[Equation 2]

When I _O is erased, it can be expressed as follows.

[0028]

(Equation 3)

That is, the equation (2) is based on V _{O of the} high voltage output stage.
It is shown that V _C is accurately determined by feeding back a low voltage V _F without feeding back V _C. The specific setting of V _O is
Either change R _F to obtain the desired V _O or V _F
Can be changed (by changing the voltage of the reference terminal T63 of the amplifier 62). This feedback is an indirect feedback performed by generating a feedback current similar to the output current.
Since the ratio N in the case of using the current mirror circuit depends on the emitter size ratio of the transistor, it is stable regardless of the large or small range of the current I _O , so that the output voltage can be controlled with high accuracy.

Thus, no feedback impedance element is required in the high-voltage output stage, the power consumption (ΔCV ² f) due to the parasitic capacitance is eliminated, and a wide band operation with low power consumption becomes possible. Also, since the feedback has a low voltage amplitude, the response of the feedback is fast. Further, it is also useful in terms of miniaturization and reliability.

Another embodiment of the present invention will be described below with reference to the circuit diagram of a more detailed embodiment. FIG. 3 is a detailed circuit diagram of the embodiment corresponding to FIG. 1 already described. The same parts or equivalent parts are denoted by the same reference numerals.

In a high-speed, high-precision feedback circuit, a similar measure is required in a sample hold. The sampling switch 61 of FIG. 3 is configured by combining a high-precision analog switch 4 and a high-speed low output impedance charging switch. The transistor Q73 as an analog switch of the sampling switch 61 has its base connected to a constant current circuit formed by a pair of transistors Q70 and Q71, and also connected to one Q76 of a differential transistor pair. The collector of the transistor Q73 is connected to the collector of the feedback current mirror transistor Q69 which is connected to the electrode V _CC via the resistor R _F. The emitter side of Q73 is connected to the hold capacitor C _X2 via the transistor Q72 of the Emitch follower. The current of the above-described constant current circuit Q71 is set to an electrode of about 10 μA at which the offset voltage of the switch transistor Q73 is minimum, and a capacitor C11 for speeding up is separately connected during driving, and a differential current of 300 μA at maximum is added. Is set at a minimum sample time (about 50 ns in the embodiment). The emitter of the transistor Q72 is connected to the other transistor Q75 of the differential pair as a pulse current bieye source.

The operation of the sampling switch 61 connected as described above is as follows. In the steady state, the transistor pair Q76 is on and Q75 is off, so both transistors Q73 and Q72 are off. When an "L" level sample signal is applied to the sample control terminal T61, the transistor Q76 of the differential pair is turned off, and the transistor Q75 is turned on to differentially drive and conduct Q73. Sampling is performed rapidly by lowering the emitter output impedance. In the latter half of the sampling period, the base-collector reverse current of Q73 reaches a steady value (about 10 μA) at which Q73 gives the minimum offset voltage, and the low offset of switch 4 and the high-speed sampling are compatible.

The terminal voltage of the hold capacitor C _X2 is fed back to the input side of the video amplifier via a differential amplifier including transistors Q78, Q79 and Q80. Because the accuracy of the sample hold circuit that needs to be managed as the sum of the sampling switch 61 and the hold amplifier 62, V _BE of V _BE of the transistor Q81 of the transistors Q72 is a current flowing in Q72 to match Q81
Are designed to be as equal as possible. Therefore, the accuracy of this sample and hold circuit can be 1 mV and the minimum sample time can be 50 ns.

One of the features of the present invention is the simplification of the circuit and the improvement of the performance by the complementary bipolar transistor circuit. Hereinafter, an embodiment of the two-input buffered multiplexer 10 which also serves as a part of the V / I conversion circuit will be described. The multiplexer 10 with a two-input buffer in FIG. 3 includes three differential pair transistor circuits. That is, the pair of transistors Q1 and Q2, the pair of transistors Q3 and Q4, the pair of transistors Q5 and Q6, of which the pair Q1, Q2 and Q3,
The pair Q4 is an input switch constituted by an NPN transistor, and the pairs Q5 and Q6 are constituted by pnp transistors of opposite polarities and also serves as a part of a V / I converter. Q1,
The Q2 pair and the Q3 and Q4 pairs are biased by the emitter resistors of R1 and R2, respectively, and also serve as V / I conversion.
The pair 5, 5 is biased by a constant current circuit formed by the transistor Q12. Each bias current is determined in consideration of complementarity such that the cutoff frequency f _T of each transistor is high and the rate of temperature change of the base-emitter voltage of the npn transistor and the pnp transistor at the operating point is equal. It is about 1 mA. In the pair of input transistors Q1 and Q2, the base of Q1 is connected to the signal input terminal T11, and the base of Q2 is biased to V _CC by the resistor R3 and connected to the control terminal T13. The output of the common emitter is Q5 of the pnp transistor pair.
Connected to the base of. Similarly, the base of the other pair of Q3 and Q4 has Q3 as an input terminal T12 and Q4 as a control terminal T1.
4, the common emitter is the Q / V of the transistor pair for V / I conversion.
6 connected to the base.

Next, the operation of this circuit will be described. Terminal T1
To select the input from 1 and deselect the signal at the terminal T12, set the control input terminal T13 to the "L" level and the terminal T1.
4 is set to "H" level. Then, the transistor pair Q1,
As for Q2, the signal is transmitted to Q5 with Q2 being cut off and Q1 as an emitter follower. Further, in the other transistor pair Q3 and Q4, only Q4 having a higher base voltage conducts, and its emitter voltage is input to Q6. Therefore, in the pnp transistor pair Q5 and Q6, only Q5 having a relatively low base voltage conducts, and eventually the input terminal T1
1 is selected as the V / I conversion signal. Terminal T1
In order to select the 2 side and deselect the terminal T11 side, the above-described operations have the opposite relationship. The input signal of the terminal T11 is VI
1, and a transistor pair Q5, Q6 that also functions as V / I conversion
The voltage of the common emitter as V _O the equivalent circuit at the time when and the unselected selection circuit described above and shown as being except for loading effect by Z _X of each Figure 4 (a), is as (b). That is, represented as a series-parallel switch of the two-stage, r _e is very small in emitter resistance of the transistor (approximately at 1mA 26Ω), Z _off because parasitic impedance between the base and emitter reverse biased, as two-step switch The on-off ratio is extremely large, up to several hundred MHz 5
It is 0 dB or more. In addition, when it is turned on, it operates as an emitter follower, so that the signal attenuation can be as small as 1% or less up to several hundred MHz.

Further, the multiplexer 10 with a buffer according to the present invention can perform an extremely wide band operation because it has a V / I conversion operation substantially using only two emitter follower stages.

The pnp transistors Q7, Q8 and Q9, Q in the 2-input buffered multiplexer 10 shown in FIG.
The two current mirrors 10 are the input current compensation of the two-input buffered multiplexer 10. As a result, the multiplexer maintains the high input impedance in combination with the emitter follower input type, and stabilizes the low-frequency characteristics of the video amplifier.

The two-input buffered multiplexer 10 of the present invention described above realizes simplification and high performance of the circuit by the complementary bipolar transistor circuit system which is one of the main means of the present invention. Here is an example.

Next, an embodiment of the V / I conversion circuit 20 of FIG. 3 will be described. One of the main means for widening the bandwidth of a video amplifier according to the present invention is to make the circuit as current operable as possible. Therefore, the voltage video input signal is quickly converted into a current signal without deterioration of S / N. The V / I conversion circuit 20 is a differential circuit including pnp transistors Q5 and Q6 also serving as output stages of the multiplexer and a new pnp transistor Q16. Each emitter has a pnp transistor Q1 forming a current mirror.
2, each with a bias current is supplied from Q13, conversion impedance Z _X for determining the conversion gain of V / I converter is connected. The transistor Q16 side is a reference for determining the center of the operating range, and a reference voltage is applied to the base of the transistor Q16 via the emitter follower Q15 by the voltage dividing circuit of the resistors R14 and R15. This reference voltage does not need to be strict because the signal input as a video amplifier is an AC input, and from the viewpoint of increasing the maximum allowable input of the circuit, the power supply V _CC is set to 1
/ 2 is set. This reference and the input terminals T11 and T13 of the 2-input buffered multiplexer 10 are V /
As the I conversion circuit, the transistor Q1 has the same level shift amount so that the offset is the same even when the temperature changes.
The operating current of 6 is set approximately equal to the operating current of the multiplexer.

In this V / I conversion circuit, the input signal selected by the two-input buffered multiplexer 10
5 and the common emitter of Q6.
Is converted to a current (ΔI = ΔV / Z _X ) by the V / I conversion impedance, and the collectors of the transistors Q5 and Q6 and the transistor Q1
The collector current of 5 is a signal that changes in the form of I ± ΔI. Conversion impedance Z _X is normally be resistors only, when actively changing the frequency characteristics of the V / I conversion capacitor, or an inductor is used in combination.

This V / I conversion circuit is a balanced circuit.
Since the input signal is a single-ended input, the frequency response of the differential output circuit in a high-frequency region is not usually the same. Therefore, in the embodiment of the present invention, the resistor R is connected to the output side.
Frequency response characteristics are matched by inserting 12, R13 and the capacitor C2.

Next, a current output type video gain controller will be described. In FIG. 3, a gain controller 31 includes npn transistors Q35 and Q3, which are so-called variable conductance type multiplying circuits including differential stages in which collectors of npn transistors Q37 to Q40 are cross-coupled.
Cascode amplifying circuit consisting of six, npn transistor Q
41, Q42, and resistors R39, R40. The control circuit 32 includes a voltage-current conversion circuit including npn transistors Q26 to Q29 and resistors R27 to R29, and a common base npn transistor Q
24 and Q25, a linearized logarithmic bias circuit, a control voltage dividing circuit including transistors Q30 to Q34 and resistors R30 to R38, a pnp transistor Q43 to Q45, and a variable bias current generating circuit including resistors R21 to R26.

The basic principle of this configuration is, for example, by Greven, translated by Nakazawa et al., Analog integrated circuit, Modern Science Co.
-9), pp. 234-242, discussed in detail as a four-quadrant multiplier. The video gain controller shown in FIG. 3 differs from this basic configuration in that the cascode amplifier circuits of Q35 and Q36, the control voltage dividing circuit, and the variable bias current generating circuit are added. here,
The cascode amplifier is connected to the output of the variable conductance multiplier to reduce the load impedance of the multiplication circuit, thereby improving the band.

The control voltage dividing circuit divides the voltage at the gain control terminal T31 by resistors R37 and R38 and supplies the divided voltage to the base of Q26, which is one input of the voltage-to-current conversion circuit. The reference voltage generated by the transistors Q30 to Q34 and the resistors R30, R31,
The voltage is supplied to the base of Q27 which is the other input of the voltage-current conversion circuit, through a buffer amplifier composed of R35 and R36. With such a configuration, the base point of Q27, which is the other input of the voltage-current conversion circuit, has a low impedance, the fluctuation of the reference voltage due to the current of the voltage dividing resistor R27 is significantly reduced, and the gain is accurately measured. You can control. Further, since the voltage of the gain control terminal T31 is divided and supplied to the voltage-to-current conversion circuit, the power supply voltage required for the voltage-to-current conversion circuit can be reduced.
Can be operated with a low voltage power supply (for example, a single 5 V power supply).

Next, the variable bias current generating circuit will be described. This circuit is a circuit for correcting a brightness level that changes according to a contrast gain. FIG.
, The output current difference I of the gain controller 31
_OG

[0047]

[Equation 4]

It becomes Here, K _G is the gain of the gain controller 31, Z _X is transformed impedance, V _R1 is the reference voltage of the voltage-current conversion circuit. Normally, V _i is V _R1 ±
Vary from [Delta] V, brightness level V _R1 - [delta
Set to V. At this time, I _OG is -K _G · ΔV / Z _X, and the changes in proportion to the gain K _G. The bias current generating circuit is configured to generate a current having a polarity opposite to this current change. That is, the transistors Q20, Q21, resistor R21, a current mirror circuit consisting of R22 detects the current difference of the voltage-to-current converter circuit a current proportional to the gain K _G to occur, the current gain transistor Q22, Q
23, a current shunt circuit composed of resistors R25 and R26 is adjusted to be equal to a change in the output current of the gain controller 31. With the above configuration, the output of the present bias current generating circuit can be equal in polarity to the change in brightness level with respect to the gain change. Therefore, this output current is added by the auxiliary current mirror amplifier 40 to change the brightness level. Can be corrected.

The offset addition circuit composed of R23 and R24 is a circuit for controlling the brightness level output current, and adjusts the brightness level output current value by the values of R23 and R24 and the voltage of the control terminal T32.

Next, the auxiliary current mirror amplifier 40 will be described. In FIG. 3, the present amplifier 40 includes a differential-single conversion circuit that converts the differential current output of the gain controller 31 into a single-ended signal, a pnp current mirror amplification circuit that outputs a plurality of amplified currents, and a pnp current mirror amplification circuit. It is composed of a base current correction circuit that corrects the dead zone.

Here, the differential-single conversion circuit has a pn
The current mirror circuit is composed of p-transistors Q43 to Q45 and resistors R41 to R43, and the collectors of the input / output terminals Q43 and Q44 of the current mirror are connected to the collectors of the outputs Q35 and Q36 of the gain controller, respectively. With this configuration, the collector current of the output Q44 of the current mirror circuit is controlled by the gain controller 31.
The output of the differential-to-single conversion circuit is the collector current difference between Q35 and Q36, which are the outputs of the gain controller 31, because they are equal to the collector current of Q35, which is one of the outputs. Therefore, the common mode noise generated by the power supply noise or the like can be significantly attenuated by the differential-single conversion circuit, so that parasitic oscillation due to the feedback loop via the power supply line can be prevented.

Next, the pnp current mirror amplifier circuit will be described. This circuit operates with the output current below the maximum rated current of the minimum size. If a current mirror that amplifies at a normal emitter area ratio (number ratio) is applied here, N output transistors are required regardless of the current density. For this reason, the capacity of the output transistor increases,
An obstacle to high-speed operation.

This circuit realizes the input / output transistors with the same size, and the principle is shown in FIGS.
FIG. 5 shows the relationship between the base-emitter voltage V _BE and the emitter current I _E of the transistor. From this figure, in order to obtain a current gain of N times a transistor of the same size, [Delta] V than the V _BE of the input transistor of the V _BE of the output transistor (= V
It may be driven by the _T I _n N) by more voltage. FIG. 6 shows a current amplifier circuit designed based on this idea. here,
Since the emitter current ratio of the transistors Q47 and Q48 having a common base is controlled to N: 1 by a current mirror constituted by Q471 to Q473 and Q481, the V _BE of Q48 is Q
Smaller by V _T I _n N than 47. As a result, V _{BE of the} output transistor Q49 is higher than V _BE of the input transistor.
Will be driven only by a voltage higher _T I _n N, the output current is N times the input current.

As described above, according to the current amplifying circuit shown in FIG. 6, an N-fold gain can be obtained with input / output transistors of the same size, so that the influence of the parasitic capacitance of the output transistor is small and the high-frequency characteristics are improved. I can do it.

In FIG. 3, a pnp current mirror amplifier circuit includes pnp transistors Q46 to Q52 and a resistor R44.
To R51. With this configuration, the gain setting V _T
The voltage of I _n N is generated by setting the resistance ratio of the resistors R46 and R47 to 1: N and the emitter currents of the common base transistors Q47 and Q48 to N: 1. This is R4
6, because the terminal voltage of R47 is determined by the V _BE of Q46 and Q49 and can be regarded as practically equal. In addition, and resistors R44 and R48~R51 which is connected to the emitter of the input transistor Q46 output transistor Q49~Q52 is intended to prevent the deterioration of characteristics due to V _BE variation of each transistor, the resistance ratio of N: set to 1 doing.

[0056] Further, the resistor R45 connected to the base of the input transistor Q46 is used to correct the gain variation of the current mirror according to variations in the current gain h _ie of the pnp transistor. In FIG. 3, the emitters of Q47 and Q48 for generating a gain setting voltage are connected to an input transistor Q46.
And the base currents of the output transistors Q49 to Q52. Here, the sum of the base currents of Q49 to Q52 is Q46 when the number of output transistors is M (4 in FIG. 3).
It becomes MN times as much. Therefore, when h _ie decreases, the emitter current of Q48 increases, and the gain decreases. On the other hand, the resistor R connected to the base of the input transistor Q46
45 is equivalent to in terms of the emitter resistor R45 / h _ie
Becomes This resistance is added to the emitter resistance R44. When h _fe decreases, the emitter resistance of the input transistor increases and the gain increases. Thus, the gain variation is the opposite polarity by h _ie the base current and the resistance R45 of the output transistor, can be corrected gain change by h _ie with R45. h _ie usually varies greatly with temperature. For this reason, this circuit has the effect that the gain change due to temperature can be reduced.

Next, the base current correction circuit will be described. In the pnp current mirror amplifier, the emitter current of the common base transistors Q47, Q48 becomes substantially constant current regardless of the input current, 1 / h _ie the current becomes a base current I _B. Since this base current I _B is obtained from the input current, a dead zone occurs in the input / output characteristics. The base current correction circuit is a circuit that corrects this dead zone, and is composed of transistors Q53 to Q55, resistors R52 and R53, and a capacitor C6. In this circuit, the sum of collector currents of Q47 and Q48 is made to flow to Q53, and the base current of Q53 is made Q
The current mirror is composed of 54, Q55 and R52, R53, and is turned back to the base of Q47, Q48. Since Q47, h _ie of Q48 and Q53 are approximately equal, the base current of Q53 is equal to the base current sum of Q47, Q48. For this reason, the base currents of Q47 and Q48 are supplied at the same current as the base current of Q53, and the dead zone of the input / output characteristics can be eliminated.

In the auxiliary current mirror amplifier 40, the output transistor Q2 of the variable bias current generating circuit is used.
The collector of 3 is the current mirror input transistor Q55
By connecting to the collector of the gain controller 31
, And the output current of the variable bias current generating circuit is added.

Next, a current mirror current amplifier circuit using npn transistors will be described. In FIG. 3, n
The pn current mirror current amplifier circuit is used for four blocks 51 to 54. The configuration and operation of this circuit will be described with reference to 51 block circuits. This circuit is based on a base current correction type current mirror circuit. That is, the transistors Q56 and Q58 for setting the mirror ratio and the resistor R
54, R55 and transistor Q5 for correcting base current
7, a resistor R58 is provided, and resistors R56 and R57 and a capacitor C7 are added to stabilize high-frequency response.

Here, the emitter area ratio of Q56 and Q58 is proportional to the current amplification factor, and R54 and R55 and R56 and R58
The resistance ratio of 57 is set to be inversely proportional. With this setting, the voltage drops of R54 and R55 become equal, and Q56
And Q58 can be driven with the same base-emitter voltage. As a result, the input / output current ratio becomes equal to the set current amplification factor.

In this circuit, the base current correction transistor Q
57 operates as an emitter follower and drives the output transistor Q58. When the current amplification factor of this output transistor is increased, the emitter area is increased and the emitter resistance R55 is decreased, which results in a large capacitive load. It is known that such a structure in which a capacitance is driven by an emitter follower circuit causes vibration in its response. R57 of this circuit prevents vibration by limiting the reduction of the high-frequency impedance of the load.

The capacitor C7 is connected to Q56 and Q57.
Is reduced by lowering the high-frequency impedance of the emitter of Q56.

The above-described operation of FIG. 3 is facilitated by the current operation and the complementary bipolar transistor circuit employed in the present invention.

FIG. 7 shows another embodiment of the indirect feedback type video amplifier. In the figure, the video amplifier is composed of a drive stage LSI 80 for the low voltage section, a high voltage output stage 70, a sample hold circuit 60, etc., and an input terminal T for the low voltage section.
11 is an input signal to terminal 1 via input capacitor C _X1
(Not shown) is added. The output of the output stage 70 is connected to the cathode R of the CRT. 7 are a high-voltage power supply + V _H (for example, 120 V) and a low-voltage power supply + V _CC (for example, 10 V).

The high voltage output stage 70 is composed of a load resistance _RL of several hundred ohms and a high frequency power transistor 71, and its base is _{supplied with} a fixed voltage of + V _CC . The emitter of the power transistor 71. emitter follower as the output stage current mirror 51, 52 and 53 of the low pressure section from the emitter resistor R _E1 is connected in series to form a so-called cascode amplifier. The cascode emitter follower has a transistor Q6 with a common base.
9 and emitter follower small volume consisting of the emitter resistor R _E2 is connected in parallel, their common base preamplifier 8
1 output. The collector of the transistor Q69 is connected through a resistor R _F in the power supply + V _CC, is input to the switch 61 of the sample-and-hold circuit 60.
The output side of the switch 61 is connected to the hold capacitor C _X2 and the input side of the amplifier 62. The other input of the amplifier 62 is input divided voltage of the resistors R601, consisting R602 source + V _CC, the output side 63 of the amplifier 62 is the resistor R8
9 is connected to the input of the preamplifier 81. The loop gain of this closed loop is about several hundreds.

In FIG. 7, the desired DC bias output of the high voltage output stage is V _O , the feedback voltage from the corresponding transistor Q69 is V _F , and the transistors Q69, 51, 52,
If the emitter-base voltage of 53 is V _BE and the output voltage of the amplifier 81 is V _A , V _O and V _F can be expressed by the following relationships.

[0067]

(Equation 5)

[0068]

(Equation 6)

From equations (5) and (6),

[0070]

(Equation 7)

Here, k in the equation (7) is a reference input voltage dividing ratio (≡R602) of the amplifier 62 of the sample hold circuit.
/ R601 + R602). Therefore, the desired V
Variable resistor R in FIG. 7 as _O, thereby satisfying the expression (7) for
_F is set.

With the above configuration, the control input terminal T61 of the sample and hold circuit 60 shown in FIG.
When a sampling pulse is applied during the period shown as the back porch of the waveform of the waveform, the voltage corresponding to the output voltage during the back porch is sampled and held, compared with a reference value, and the output voltage is corrected via the amplifier 62 and the resistor R89. Negative feedback. Since the sampling pulse is periodically applied every horizontal synchronization (1H period), the DC voltage of the output voltage finally becomes equal to the desired value which has been set, and holds the value. It should be noted that in the above equation (7) and the configuration of FIG. 7, the relationship between the output voltage and the feedback voltage is a symmetrical differential relationship that does not depend on temperature or the like. Therefore, the control is performed with good accuracy similar to the feedback from the high voltage output section.

In this way, all outputs are made only by the low-voltage circuit.
As a result of enabling the bias control of the voltage, the load on the high-voltage output unit is reduced (about 1 to 2 PF), so that the band can be improved by several tens of percent and the high-frequency power consumption can be reduced.
Further, it is desirable to omit the feedback resistor in the high voltage section from the viewpoint of cost and reliability, and it is easy to integrate circuits.

FIG. 8 shows an embodiment of the indirect feedback video amplifier applied to the embodiment of FIG. 1, and FIG. 9 shows an embodiment of the sample hold circuit applied to the embodiment of FIG. Since the configurations and operations of FIGS. 8 and 9 are equivalent to those of FIGS. 1 and 3, description thereof is omitted here.

FIG. 10 shows another embodiment of the indirect feedback video amplifier. The difference from the embodiment of FIG. 8 is that a peak hold circuit 6 is used instead of the sample hold circuit 60 of FIG.
5 is used. The peak hold circuit 65 is a diode 66, 67, resistors R601～R603, capacitor C _X, made from the amplifier 62, the peak value of the voltage generated at terminal T85 by the diode 66 and the capacitor C _X (voltage polarity generated at the terminal T85 is (The same as the polarity of the output). As a result, a voltage corresponding to the back porch level of the video signal can be obtained without using a timing signal as shown in FIG. 8, and the same effect as in FIG. 8 can be obtained. Note that the diode 67 and the resistor R
The circuit composed of 603 is for matching the input operating points of the amplifier 62.

Next, another embodiment of the indirect feedback video amplifier is shown in FIG. The difference from the embodiment of FIG.
An inverting amplifier using the pre-amplifier 81, to an output stage current mirror amplifier 51, 52 and 53 of the low pressure portion is replaced with pnp transistor, to constitute a emitter follower with its emitter connected to resistor R _E on the emitter side of the transistors It is. Further, the feedback voltage to the sample and hold circuit 60 is taken from the terminal T51.

In FIG. 11, if the emitter-base voltage of the output stage current mirror amplifiers 71, 51, 52, 53 is V _BE and the output voltage of the amplifier 81 is V _A , the desired DC bias output of the high voltage output stage is obtained. V _O and the feedback voltage V _F to the sample hold circuit 60 can be expressed by the following relationships.

[0078]

(Equation 8)

[0079]

V _F = V _A + V _BE (9) From equations (8) and (9),

[0080]

[Equation 10]

Since the relationship similar to the expression (7) is obtained, the output and voltage bias control can be performed only by the low-voltage circuit.

Further, another embodiment of the indirect feedback type video amplifier is shown in FIG. FIG. 12 shows an embodiment in which the feedback voltage input to the sample and hold circuit 60 is obtained from the output of the preamplifier 81, that is, from the intermediate stage of the low voltage circuit section. In this case as well, the same relationship as in equation (7) can be obtained, so that the output and voltage bias control can be performed only by the circuits in the low voltage section.

Thus, the output voltage (C
Negative feedback may be made indirectly to the input side from a portion having a voltage lower than the high voltage applied to the cathode of the RT display), and various modifications are included.

FIG. 13 shows an embodiment of the multiplexer applied to the embodiment of FIG. The configuration and operation of this embodiment are shown in FIG.
As described in.

FIG. 14 shows another embodiment of the multiplexer. In this embodiment, the multiplexer is composed of transistors Q5 and Q5.
6, Q201~Q203, is applied to a differential amplifier circuit constituting a constant current source I _3. Also in this embodiment,
When selecting the input signal V _IN1 , the control signals V _SW1 and V _SW1
Input GND and V _CC to _SW2 respectively. As a result, Q
3, Q6 is cut off, and Q1 and Q5 operate as an emitter follower. For this reason, V is applied to the input of the differential amplifier circuit.
_IN1 is selected. At this time, the base voltage of Q5 which is one input of the differential amplifier circuit is V _IN1 −V _BE , and the base voltage of Q16 which is the other input is V _REF −V _BE . For this reason, also in this embodiment, Q1, R1 and Q
By designing the R15 and R16 with good matching, the offset voltage can be reduced.

Next, another embodiment of the current amplifying circuit used for the auxiliary current mirror amplifier 40 will be described with reference to FIGS.

In FIG. 15, reference numeral 41 is an input terminal, 42 is an output terminal, and 43 is a power supply terminal. Q401, Q
402 is a transistor having two emitters connected in common, Q
Reference numerals 403 and Q404 are two transistors whose bases are commonly connected, and form a bridge circuit with diodes between the base and emitter of Q401 to Q404. The transistors Q401, Q411 to Q41N, Q421 have a current mirror configuration, and the collector of the transistor Q401 is connected to the input terminal 41 and the transistors Q411 to Q41N.
Is connected to the emitter of the transistor Q403, and the transistor Q421 is connected to the emitter of the transistor Q404. Also, transistors Q403 and Q4
The base of 04 is the input terminal 41 and the collector is the power supply terminal 4.
3 is connected. The collector of the transistor Q401 is connected to the output terminal 41. In the configuration of FIG. 12, it is assumed that the current mirrors of transistors Q41 and Q411 to Q41N are closed by a feedback loop via transistor Q403, and that N transistors Q411 to Q41N have the same emitter area as transistor Q401. , the input current I _i applied to the input terminal 41, I _i, flows (NI _i in total) each I _i to the transistor Q411~Q41N transistor Q401. On the other hand, the transistor Q421
401 and because the relation of the current mirror, the transistor Q421 is also because it uses of the same emitter area of the transistor Q401, the transistor Q421 flows even I _i. For this reason, the two transistors Q403 and Q404 whose emitters are connected in common have NI _i and I
_i will flow.

Next, the transistors Q401, Q402,
In the diode bridge circuit of Q404, the base-emitter voltages of the transistors are V _BE1 , V _BE2 , and V _BE , respectively.
_BE3 , V _BE4

[0089]

[ _Equation 11] V _BE1 + V _BE3 = V _BE4 + V _BE2 (11) holds. Further, each base-emitter voltage of the equation (11) is expressed as follows.

[0090]

(Equation 12)

[0091]

(Equation 13)

[0092]

[Equation 14]

[0093]

(Equation 15)

Here, V _T is the thermal voltage A _E is the emitter area of the transistor I _SO is the collector reverse direction saturation current I _O per unit area The collector current of the transistor Q 404, that is, the output current taken from the output terminal 42. Substituting the expressions (12) to (15) into the expression (11) and rearranging the expression gives the expression (16).

I _O = NI _i (16) That is, it shows that the current mirror ratio N: 1 of the transistors Q411 to Q41N and Q421 becomes N times the current gain, and is not related to the absolute value of the current mirror current. .

According to this principle, transistors Q401 to Q404 having the same emitter area constitute a diode bridge circuit, and two transistors Q403,
The potential difference ΔV between the emitters of Q404 (= V _BE3 −V _BE4 =
And V _T I _n N) is generated by adding the ΔV between the bases of the two transistors Q401, Q402 emitters commonly connected, the base-emitter voltage V _BE2 of the transistor Q402 is only MiKakeue ΔV increases It depends on what you did. Accordingly, the collector of the transistor Q402 which the ΔV is added can be obtained (16) the collector current of the transistor Q401 as type, i.e. the output current I _O of N times the input current I _i. As described above, according to the present embodiment, the diode bridge circuit operates at high speed (because of the diode connection, the base-emitter voltage of the transistor does not change, so that the parasitic capacitance of the transistor has little effect), and the output transistor also has By reducing the parasitic capacitance that limits the band with the minimum number,
High frequency characteristics can be improved.

[0097] Also, it can be set to link the input current I _i transistors Q403, Q404 current value, because it can equalize the current flowing in the opposite transistor of the diode bridge circuit, the input current I _i operates from 0
(Characteristics as shown in FIG. 17A) and the linearity of the input / output characteristics is also good.

In the above embodiment, the input current I _i
Current flows through the totem poles of the transistors Q404 and Q421.
Since the operation of 421 works in a direction to cancel, the output current I _O at a high frequency is limited. To improve the high frequency characteristics, a constant current is applied to the totem-pole transistor Q421 so that the transistors Q404 and Q42
1 cancels out, and the high-frequency characteristics are improved.

That is, another embodiment of the present invention for realizing this is shown in FIG. 16 differs from the embodiment of FIG. 15 in that transistors Q411 to Q41N,
A current mirror is formed by Q421 and Q431, and a constant current is applied to two transistors Q40 whose bases are connected in common.
3, Q404. Also in this case, if the current mirror ratio of the transistors Q411 to Q41N and Q421 is set to N: 1, the expression (16) is satisfied, and the current gain is N times.

In the embodiment of FIG. 16 described above, a constant current is passed through the two transistors Q403 and Q404 whose bases are commonly connected. Therefore, only a current of one of the current amplification factors of the transistors is changed from the input current I _i to the base. It is taken as the current ΔI, and the input / output characteristics are as shown by the straight line in FIG. The [Delta] I becomes dead zone, the input current I _i output current I _O can not be obtained and does not exceed [Delta] I. For this reason, as shown in FIG. 17A, the input current I _i is changed from 0 to the output current I _O.
FIG. 18 shows an embodiment of the present invention for obtaining the above.

That is, in FIG. 18, the transistor Q4
41, Q442 and Q443 are provided, and a current equal to the current amplification factor of the sum of the currents flowing through the two transistors Q403 and Q404 whose bases are connected in common is set to the transistor Q441.
(Use the same emitter area as the transistors Q403 and Q404), then the transistor Q
Input terminal 41 by the current mirror of 442 and Q443
To eliminate the dead zone ΔI by base current correction.

Although the embodiments of FIGS. 15, 16 and 18 described above have been described with a one-output current amplifier configuration, multiple outputs are also possible. In this case, since it can be realized only by increasing the number of output transistors by the number of multi-stages, the high frequency characteristics are not significantly impaired as compared with one output.

Further, by inserting a resistor on the emitter side of the two transistors whose emitters are commonly connected or the transistor of the current mirror circuit, there is an effect that the high frequency characteristics can be further improved. In this case, the setting of the resistance value is selected so that the voltage applied to the resistance is constant depending on the current ratio flowing through the transistor.

In order to obtain 1 / N as the current gain, it can be realized by changing the current mirror ratio of the current flowing through the two transistors whose bases are connected in common from N: 1 to 1: N.

Although the transistor used in the current amplifier has been described as npn, a current amplifier in which a source type output is obtained by substituting pnp is also possible. In FIG. 19, FIG.
An example in which Example 8 is replaced with pnp is shown. Also in this case, the same effect as in FIG. 18 can be obtained for the high frequency characteristics. In particular, the capacitor C401 inserted between the base of the transistor Q441 and the ground potential has the effect of suppressing the amount of base current correction feedback at high frequencies and flattening the frequency characteristics. Further, since the transition frequency f _T is lower than npn even in pnp even though it is a vertical transistor, the present invention provides
np is more effective.

Next, another embodiment of the present invention using the complementary transistor circuit will be specifically described with reference to FIGS.

FIG. 20 shows a video amplifier and a CRT display device using the same according to another embodiment of the present invention.

This embodiment is not a direct feedback type video amplifier but a direct feedback type video amplifier and a CRT display device using the same.

The video amplifier according to this embodiment comprises a buffered multiplexer 100, a current output type video gain controller 300, and a multiple output current mirror circuit 4.
00, a multi-output current mirror circuit amplifier 500, which is a complementary video amplifier circuit having an output of a CRT 700.
Is applied to the cathode.

First, referring to FIG. 20, the structure of the multiplexer with buffer 100 is as follows.
It comprises a differential current stage 1,212, a constant current circuit 213 for current bias on the common emitter side, a pair of pnp transistors 231 and 232 symmetrical thereto, and a constant current circuit 233 for current bias on the common emitter side. I have. The emitter output of the differential stage of the npn transistor is wired 23 to the base of the pnp transistor 231 of the next differential stage.
4 are connected. Similarly, the signal of another npn differential stage (not shown) is connected to the base of the other pnp transistor 232. The input of this circuit 100 is a terminal 201 and the output is a wiring 2 from the common emitter of the pnp differential stage.
35. The values of the constant current circuits 213 and 233 are set to almost the same value with good complementarity, for example, about 1 mA for both. The operation of the multiplexer with buffer 100 having the above configuration is as follows. When an input voltage signal is applied to the terminal 201 and the voltage of the control terminal 204 is lower than the potential of the input terminal 201, the transistor 212 is turned off and the input signal is transmitted to the next transistor 231 as an emitter follower of the transistor 211. Similarly, when the input of H.232 is cut off, the next stage also operates as an emitter follower, and the output is output from the signal line 235. That is, the equivalent circuit when this output is selected is, as shown in FIG. 21 (a), a low output impedance Z of the emitter follower.
_O (= expressed in kT / qI _E I _E = 1mA in ~ 26Ω)
And a high impedance Z _off ′ (the output impedance of the constant potential circuit and the cutoff leakage impedance of the cutoff transistor), the input signal acts as a buffer of high input impedance and low output impedance, and the signal has very little attenuation ( For example, it is usually less than 1%), and the circuit operates in a wide band.

Next, when the input signal is cut off, the voltage of the control input terminal 204 is made higher than the input, and the transistor 211 on the signal source side is turned off. Similarly, the next
The pnp stage also turns off the transistor 231. The equivalent circuit in this case is as shown in FIG. 21 (b), and the input cutoff impedance Z _off of the transistor is higher than the output impedance Z _{on of the} emitter even at high frequencies.
Because of the relation of _on ≪Z _off, the amount of attenuation at interruption is (Z
_{When off} << Z _on ) ² , it becomes extremely large, and when one concrete calculation example is shown, an extremely excellent video multiplexer of 55 dB can be realized even at 300 MHz. Further, since the first differential stage and the second differential stage respectively use complementary transistors of npn and pnp, the level shift between the input and output offsets each other including the temperature change, and hardly shifts. Also, since only two transistors are connected in series with the power supply voltage, a relatively large signal input range can be tolerated even at a low power supply voltage. These features do not exist in the conventional cascade-connected differential two-stage switch composed of transistors having the same polarity.

Next, the current output type video gain controller 300 will be described.

The video gain controller 300 shown in FIG. 20 is a so-called variable conductance type multiplying circuit composed of a differential stage in which collector electrodes of npn transistors 311 to 314 are cross-coupled as in the embodiment of the present invention shown in FIG. The main component is a linearized logarithmic bias circuit including transistors 331 and 332, a voltage / current conversion circuit 35, and a voltage divider circuit of resistors 333 and 334. The common emitters of the transistor pairs 311, 312 and 313 and 314 have transistors 315 and 316 and a resistor 32 respectively.
3, a voltage-current conversion circuit including constant current circuits 321 and 322 is connected. Diodes 318 and 319 (Early effect balancing diodes) are connected to one of the cross-connected transistor pairs, and the other is a pnp transistor 31 having a polarity complementary to the transistor of the multiplier circuit.
7, 401, 411 and the like are connected.

The voltage of the bias terminal 303 of the input signal voltage power supply conversion circuit is fixed to a value approximately at the middle of the input signal range. Therefore, the difference between the input signal voltage applied to the base of the transistor 315 and the bias voltage at the terminal 303 is converted by the resistor 323 into a current signal,
Cross-connected differential transistors 3 forming a multiplying circuit
11 to 314 are supplied. On the other hand, the differential transistor 31
Transistor 3 connected to the base side of 1-314
31 and 332 and the voltage / current conversion circuit 35 are linearization bias circuits as described above, and control input terminals 351 and 35
The current flowing through the differential transistor pair is changed in proportion to the voltage between the two. Therefore, the gain controller 300
The output current flowing through the transistor 320 on the load side is proportional to the base input voltage of the transistor 315, and changes linearly with the control voltage between the gain control terminals 351 and 352, thereby forming a gain controller.

One of the important points in the disclosed gain controller 300 is that an output signal is used as a current signal via a complementary pair of transistors 317. Therefore, the basic form of the multiplier applicable to the present invention can be effectively applied to other than the transistor conductance type. For example, a multiplier utilizing current distribution of a differential stage known as a gain addition type variable gain amplifier circuit can also enjoy the same advantage. Further, since the multiplier disclosed in the embodiment utilizes the dependency of the transconductance of the transistor on the emitter current bias amount, it is advantageous to use the current output form rather than the voltage output in terms of both accuracy and speed. is there. In addition, the current output has a larger dynamic range (S /
N ratio), and the current output has a great advantage in that it can operate at high speed because the influence of the charge and discharge of the parasitic capacitance due to the voltage change of the output node is small.

Further, the advantages of the complementary transistor circuit for the output stage will be described. The pnp transistor 317 inserted into the output of the video gain controller 300 is a reference transistor of the pnp type current mirror circuit 400. That is, the base current correction transistor 401
In the collector of each output transistor 411 to 41n of the current mirror circuit 400 having the
00 output current flows. That is, the current mirror circuit 400 has functions of current distribution and current amplification (including one-time amplification). Each current output from the current mirror circuit 400 remains a current signal, and the current mirror amplifier 500
Is input to and amplified. The current amplification factor is basically determined by the emitter size ratio of the input side transistors 511 to 51n and the output side transistors 521 to 52n, but in order to improve the current ratio accuracy and improve the linearity and high speed of the response speed. The emitters of the input / output transistors have emitter resistors 541 to 54n, which are in inverse proportion to the emitter size ratio,
551 to 55n are inserted, and base current correction transistors 531 to 53n are used. The output of the current mirror amplifier 500 is supplied as the emitter current of the transistor 71 via the terminals 571 to 57n.

The collector voltage of the transistor 71 is CRT700
Is applied as a contrast signal to the cathode 701 of
The CRT 700 becomes a color signal as a combination of RGB of these signals. Here, 761 is a voltage source, and 763 is a load resistance.

The current amplification by the complementary current mirror circuit as described above is a current operation, so that it is fast, and a large dynamic range can be obtained even under a low power supply voltage.
Further, since it is a current signal, it is not affected by potential fluctuations due to the ground impedance of the current mirror circuit. This is a great advantage especially in the high current output stage. In the case of using a complementary transistor, the circuit and connection can be simplified, so that it is essentially suitable for high speed operation and the size is small.

Next, an embodiment of a specific system application of the present invention will be described with reference to FIG. FIG. 22 is a block diagram of a video amplification system of a high definition CRT display device according to another embodiment of the present invention. In FIG. 22,
A dual input buffer 100, a video gain controller 300,
There are a current mirror 400 for signal distribution and a plurality of current mirror amplifiers 501 to 50n, which are cascaded as shown. Further, it includes a sampling switch 61, an amplifier 62, bias resistors R89 and R90, and the like. The reference numerals of the blocks of the respective functions are the same as those in FIG. 3 or 20 already described in detail, or the equivalents are denoted by the same reference numerals.

A plurality of current mirror amplifiers 501 to 50
The n output terminals are alternately arranged with the respective ground terminals, and they are combined outside the chip 80 into one output terminal and one ground terminal, respectively. The combined output lines of the current mirror amplifiers 501 to 50n are connected to the emitter of the high frequency power transistor 71. Also,
A forward bias power supply 762 of about several volts is applied to the base of the power transistor 71, and a high voltage power supply 761 for output is connected to the collector via a load resistor _RL . That is, the IC 80 and the power transistor 71 constitute a cascade amplifier for outputting a current driving voltage. The collector output of the power transistor 71 is led to the cathode of the CRT via a constant cathode bias power supply (not shown), and a feedback resistor 77 for determining a DC operating point.
The signal is supplied to the sampling input terminal 601 of the video IC 80 via the reference numeral 1772. This signal is sent to the sampling switch 61, the hold capacitor C _X2 , the amplifier 62,
Enter the input side of the amplifier via high resistance R89, R90,
Connected to provide negative feedback. A reference voltage is applied to the input terminal T63 of the sampling switch 61 so that the high voltage output of the amplifier has a desired value. An analog video interface signal as shown in the drawing is applied to the input terminal 202 of the video IC 80 via the AC coupling capacitor C _X1 . This signal voltage is usually generated by a video memory and a D / A converter (both not shown), and its amplitude is 1 V or less. Since a contrast signal voltage for driving a cathode electrode in a high-definition CRT needs to be about 40 V, an inverting voltage amplifier having a maximum gain of about 100 times is configured as a video amplifier. The impedance formed between the resistor and the resistance capacitor connected between the external terminals T21 and T22 of the video gain controller is the voltage-current conversion impedance of the video gain controller. Thus the impedance Z _X, the output V _O of the video amplifier and the resistance value of the load resistor R _L and R _L in FIG. 22
Similar to the embodiment in which for the input V _i, shown in Figure 1 (1)
The relationship is expressed by the formula. FIG. 23 is a detailed circuit diagram of FIG.

As shown in the circuit of the embodiment of FIG. 22, the current output terminals 571 to 57n of the video IC 80 are configured to output in pairs with the ground terminals 581 to 58n. Each ground terminal is connected to a common ground terminal 782 for each output circuit, as shown in the detailed circuit diagram of FIG. By doing so, the output current does not flow to the common line but to each ground line, and along with the effect of the current signal interface described above, the effect of impedance drop due to the output current is reduced, contributing to wideband and low noise operation. .

Another feature of the IC output stage from this point of view is shown in the package terminal arrangement diagram of FIG. As shown in FIG. 24A, the output terminal (O _i ) and the ground terminal (G _i ) of each current amplifier are alternately arranged adjacent to each other. The current flowing through each output terminal and the current flowing through each ground terminal have opposite polarities and are equal in magnitude. Therefore, a mutual inductance effect between each output terminal and each ground terminal operates in a package having dense and almost equal terminal lengths as shown in FIG. Therefore, the effective lead inductance of each terminal is greatly reduced.

For this reason, an unstable feedback effect due to a change in the ground potential in the IC can be eliminated, and a wideband signal can be output. Further, since the induction of the current flowing through the output lead cancels out, the noise generated by the external lead can be greatly reduced, and no other interference is caused.

In this embodiment, since a divided current output stage is provided, it is possible to cope with various high voltage output stages corresponding to high-speed operation.

When the split multi-output IC package as shown in FIG. 24 (a) is implemented on a printed board, the conductor pattern arrangement on the printed board side is also devised to reduce the lead inductance by the split multi-output. Is effective. FIG. 24B shows an example of such a conductor pattern arrangement on the printed board side.

In FIG. 24B, a solid line indicates a conductor pattern on a printed board, and a dotted line indicates an IC package including leads. That is, the output lead 5 of the IC package
The output conductor pattern 570 that collects 71 to 576 and the ground conductor pattern that collects the ground leads 581 to 586 face each other in a comb shape. The lead electrode of the IC package is bent in advance so that the tip is parallel to the conductor pattern as shown at 581 ', and the bent portion of the lead is superimposed on the comb-teeth shape of the conductor pattern, and is electrically connected with solder or the like. Joined to. Further, the inner output conductor pattern is guided to the back surface through a plurality of through-hole conductors (not shown), and forms a balanced low-impedance wiring with the ground-side conductor pattern. Such an in-line comb-shaped electrode is an embodiment suitable for shortening the lead length of the package and balancing the effective length.

FIGS. 25 to 27 show another embodiment of the output stage.

FIG. 25 shows a cascode amplifier which has already been described in connection with a series connection of a transistor 71 and a circuit comprising a resistor _RL with one of a plurality of current output amplifiers 501, and a buffer with the remaining 502 to 50n. Drive the amplifier. That is, the power transistor 751 is an emitter follower, and the power transistor 752 is a constant current bias source for the emitter follower. In such a configuration of FIG. 25, the output impedance is lowered by the emitter follower without increasing the total current consumption, thereby enabling high-speed load capacitance driving.

FIG. 26 shows an embodiment of the output stage configuration utilizing the present invention. In the embodiment of FIG. 26, the current amplifiers 502 to 50n, the power transistor 71, and the load resistance R
_L constitutes a cascade amplifier, and a current transformer 501 provides a pulse transformer 765 provided on the input side of the cascade amplifier.
Drive. The pulse transformer 765 includes a differentiating capacitor 767 on the secondary side, and forms a differentiating circuit together with the pulse transformer. The resistor 764 is a damping resistor of the circuit. The polarity of this differentiation is the polarity that accelerates the change. That is, when the current of each current amplifier changes in the increasing direction, the pulse transformer generates a positive voltage pulse having the polarity shown in the figure and makes the base voltage of the transistor 71 positive to accelerate the current flowing through the transistor 71. The current is accelerated in the decreasing direction for the same reason. Therefore, the band of the final stage amplifier can be made wider.

FIG. 27 shows another embodiment of the output stage configuration to which the present invention is applied. In FIG. 27, a primary side of a current amplifier 501 is connected between a power transistor 71 of a cascade amplifier and a load resistor _RL via a pulse transformer 765.
It is driven by. The polarity of the driving in this case is also selected so as to promote a change in the collector voltage of the transistor 765. By doing so, the differential gain increases and the band can be widened. Since such a method is a kind of peaking, the inductance of the pulse transformer is
In order to obtain an effect in a range where the band is decreasing, it is necessary to select an appropriate range depending on the transistor used and the capacity of the load.

As described above, through the embodiments of FIGS. 25 to 27,
It has been shown that the present invention can be applied to various high voltage output stages and their wide band. These are examples and there may be many variations. In response to these diversifications, IC
This is because the output stage of this section is configured as an open collector type current output type divided into a plurality of parts. That is, since the plurality of divided output stages in the present invention can drive a plurality of loads without mutual interference, various output forms are possible.

The complementary pair circuit according to another embodiment of the present invention can exhibit many desirable characteristics in application. One of them is to make the contrast signal and the brightness signal free from interference when adjusting the gain of the CRT video amplifier. The input / output characteristics of the four-quadrant multiplier used for the gain control of the video amplifier have a bias because the center value (equilibrium state) is 0 and the video amplifier output is a unipolar output. Reference level of the Results As shown in input-output characteristic diagram of Figure 28 (a), an output waveform corresponding to the gain 1,2 for the input v _i and alter the gain as v _O1, v _O2 output waveform Fluctuates by _Vb as shown in the figure. Changing the contrast gain in this way is not preferable because the brightness level also changes. Half the operating range (Fig. 28
If the input is limited to the right side of the dotted line in (a), the fluctuation can be eliminated, but the dynamic range is halved, which is a disadvantage.

Therefore, in the present invention, a bias generation circuit proportional to the gain is used as shown in FIG. In FIG. 29, in the circuit of the video gain controller 300,
A variable bias circuit 308 is provided. Bias circuit 308
Is a current mirror circuit using constant pnp transistors 381, 382, and the input side transistor 3
81 is inserted in series with the transistor 332, and the output side is inserted in parallel with the gain controller output. In this way, the variable bias circuit 308 can generate a variable gain current, the output of the gain controller 300 is biased according to the gain, and its characteristics are as shown in FIG. 28 (b). That is, the gain 1,2, since changes bias correction amount accordingly be varied as ..., output v _O1, v stable without change of the reference level as _O2 and wide input dynamic range Can work with

FIG. 30 shows another embodiment of the present invention. FIG. 30 shows that the current output of the gain controller 300 is pnp
Was converted to a differential in current differential circuit consisting of transistors 343 and 345 passes a differential current to the reference transistor 317 of the current mirror, thereby obtaining a signal current I _O from the output transistor 411. This differential output characteristic is shown in FIG.
Characteristics 2 of In FIG. 31, the horizontal axis represents the input signal voltage ΔV _i ,
The vertical axis represents the output current I _O and the parameters are the gain control voltages ΔV _C = 0, V ₁ and V ₂ of the gain controller 300, and the single end characteristic 1 and the differential characteristic 2 are shown in comparison. In the differential characteristics, the operating range of ΔV _i is halved, but the gain is doubled and the output current at ΔV _C = 0 (gain 0) becomes 0, so that the state corresponds to the black level of the video signal. By doing so, the object as shown in FIG. 29 above, that is, the fluctuation of the reference operating point when the gain changes can be prevented.

The operations of FIGS. 28 and 30 described above are facilitated by the current operation and the complementary transistor circuit employed in the present invention.

Although the various embodiments of the present invention have been described using bipolar transistors, the present invention can also be implemented using complementary JFETs or the like. Furthermore, high frequency p
It is also possible to use a vertical pnp or a lateral pnp as the np transistor as appropriate.

Further, as applications using the complementary transistor circuit according to the present invention, a high frequency laser driver, an ultrasonic driver, a line driver, a pulse amplifier,
A wide range of applications using amplifiers such as current output transmitters and constant current output circuits are conceivable.

[0138]

【The invention's effect】

(1) According to the present invention, the equivalent load on the amplifier output side can be reduced, and since most circuits operate in the current mode, high-speed, wide-band operation is possible. Specifically, the bandwidth of the video amplifier is 250 MHz to 300 MHz, and a high-definition CRT display device of 5 M pixels or more can be realized, and a band of 500 MHz is realized only by an IC driver.

(2) According to the present invention, since operation can be performed with a current signal, the dynamic range of the signal can be increased and the accuracy can be increased. According to the present invention, ±
Accuracy of 0.5% or less can be easily achieved.

(3) For the above reason, it is possible to operate with a low voltage power supply, reduce power consumption, and facilitate integration.

(4) According to the present invention, since the circuit scale is small and simple, the cost can be reduced and the reliability can be improved.

(5) According to the present invention, since the operation is performed by the current signal, the S / N ratio can be improved with respect to the fluctuation of the ground potential.

(6) For the same reason, it is easy to shift the level of addition and subtraction of a signal, and it is easy to correspond to a new function.

(7) By dividing the output stage of the present invention, the effective lead inductance of the terminal can be reduced, and the wide band of the high voltage output stage can be facilitated.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing input / output waveforms of a video signal.

FIG. 3 is a detailed circuit diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing an equivalent circuit of the multiplexer shown in FIG.

5 is a characteristic diagram showing the operating principle of the current amplifier circuit of FIG.

FIG. 6 is a circuit diagram illustrating the operation principle of a current amplifier circuit.

FIG. 7 is a circuit diagram showing another embodiment of the indirect feedback video amplifier.

8 is a circuit diagram of the indirect feedback type video amplifier shown in the embodiment of FIG.

9 is a circuit diagram of a sample hold circuit shown in the embodiment of FIG.

FIG. 10 is a circuit diagram showing another embodiment of the indirect feedback type video amplifier.

FIG. 11 is a circuit diagram showing another embodiment of an indirect feedback video amplifier.

FIG. 12 is a circuit diagram showing another embodiment of the indirect feedback type video amplifier.

13 is a circuit diagram of the multiplexer shown in the embodiment of FIG.

FIG. 14 is a circuit diagram showing another embodiment of the multiplexer.

FIG. 15 is a diagram illustrating another embodiment of the current amplifier circuit.

FIG. 16 is a diagram illustrating another embodiment of the current amplifier circuit.

FIG. 17 is a diagram for explaining another embodiment of the current amplifier circuit.

FIG. 18 is a diagram for explaining another embodiment of the current amplifier circuit.

FIG. 19 is a diagram for explaining another embodiment of the current amplifier circuit.

FIG. 20 is a circuit diagram showing another embodiment of the present invention.

FIG. 21 is a diagram showing an equivalent circuit of the multiplexer of FIG. 20;

FIG. 22 is a circuit block diagram showing another embodiment of the present invention.

23 is a detailed circuit diagram of the IC unit in FIG. 22.

24A and 24B are ICs showing one embodiment of the present invention.
FIG.

FIG. 25 is a circuit diagram showing a configuration of a cascade amplifier of the present invention.

FIG. 26 is a circuit diagram showing a configuration of a cascade amplifier of the present invention.

FIG. 27 is a circuit diagram showing a configuration of a cascade amplifier of the present invention.

FIG. 28 is an explanatory diagram of characteristics of the gain controller of the present invention.

FIG. 29 is a circuit diagram showing another embodiment of the gain controller.

FIG. 30 is a circuit diagram showing another embodiment of the gain controller.

FIG. 31 is a view for explaining the characteristics of FIG. 30;

[Explanation of reference numerals] 10 ... Buffered multiplexer, 20 ... V / I conversion circuit, 31 ... Gain controller, 40 ... Auxiliary current mirror amplifier, 51-54 ... Output stage current mirror amplifier, 61 ... Sampling switch, 62 ... Amplifier.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenkichi Yamashita 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory

Claims (1)

[Claims] 1. A low-voltage drive stage for inputting a plurality of drive signals for driving a load to generate a drive current for the load, and a high-voltage amplification for the drive current to supply the drive voltage to the load. And a high-voltage output stage, the low-voltage drive stage includes a buffered multiplexer for selecting one of a plurality of drive signals, and the buffered multiplexer includes a pair of npn transistors. A first differential stage, a constant current circuit for current bias provided on the common emitter side thereof, and a second differential stage composed of the first differential stage and a pair of target pnp transistors , A constant current circuit for current bias provided on the common emitter side thereof, and the emitter output of the first differential stage is connected to the base of one of the pnp transistors forming the second differential stage. But the other np transistor base - scan the output of another differential stage are connected respectively, base of one of the npn transistors constituting the first differential stage - enter the scan terminals and the other of the npn transistor base -
Is a control terminal and the common emitter of the second differential stage is an output terminal.