JPH08307061A - Multilayer wiring board for multichip module and its production - Google Patents

Abstract

PURPOSE: To produce a multilayer wiring board for multichip module comprising an insulation layer having high insulation resistance, low permittivity, low dielectric loss and high thermal conductivity, and a conductor layer having high conductivity, conveniently at low price, while reducing the total thickness of insulation layer and conductor layer after lamination. CONSTITUTION: The method for producing a multilayer wiring board comprises a step for coating a substrate 11 or a conductor layer 13 with silicon alkoxide solution and firing to form an insulation layer 12 of SiO2 , a step for making through holes 14 in the insulation layer 12, a step for coating the insulation layer 12 formed provided with through holes 14 or the substrate 11 with an organic compound solution and firing to form a conductor layer 13 of Au, and a step for forming a conductor layer 13 of Au, serving as a wiring part, according to a wiring pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board for high-density mounting and a method for manufacturing the same. For more details, please refer to Multi Chip Module-Deposition, MC
The present invention relates to a multilayer wiring board in which a thin film insulating layer and a conductor layer used in (MD) are laminated in multiple layers on a substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art MCM-D has been attracting attention as a technique for mounting electronic parts in a high density in order to make electronic devices lighter, thinner and shorter. Conventionally, as a multilayer wiring board for this type of MCM-D, an insulating layer made of an organic material such as polyimide having a low dielectric constant and a high signal propagation speed and a high insulation resistance, and a conductor made of Cu which is inexpensive and has a low sheet resistance value. It is known that a plurality of layers are laminated on a ceramic substrate. This multilayer wiring board is generally manufactured by the following method. As shown in FIG. 3A, first, a polyimide solution is spin-coated or roll-coated on the ceramic substrate 2 on which the wiring portion 1 is formed to form an insulating layer 3 made of polyimide, and then, shown in FIG. 3B. As shown in FIG. 3C, the through hole 4 is formed by photolithography, and Cu is coated by the sputtering method or the vapor deposition method, and then the wiring portion 5 based on the pattern is formed by photolithography.
As shown in FIG. 3D, the polyimide solution is coated again to form the insulating layer 6 made of polyimide, and the through holes 7 are formed. A multilayer wiring board is manufactured by repeating the steps shown in FIGS. 3 (c) and 3 (d). Although not shown, in the above manufacturing method, when a conductor layer made of Cu is directly laminated on an insulating layer made of polyimide, polyimide and C
Since the adhesion strength with u is not sufficient, a Cr layer is usually interposed between these layers.

[0003]

However, the above-mentioned multilayer wiring board has the following problems. The insulating layer made of polyimide requires a thickness of 10 to 20 μm in order to obtain a desired withstand voltage. Since the insulating layer is an organic material of polyimide, the thermal conductivity is low at 0.00037cal / s · cm · ° C or less,
The heat resistance temperature is not high at around 500 ° C. Therefore, when the LSI is mounted on the multilayer wiring, the heat generated from the LSI is poorly dissipated and the thermal reliability is poor. A Cr layer is required between the insulating layer made of polyimide and the conductor layer made of Cu, and the manufacturing process is complicated.

An object of the present invention is to provide an insulating layer having a high insulating property, a low dielectric constant, a low dielectric loss and a high thermal conductivity, and a conductor layer having a high conductivity, and after the insulating layer and the conductor layer are laminated, (EN) Provided is a multilayer wiring board for a multi-chip module, which has a relatively small total thickness, and can be simply and inexpensively manufactured, and a manufacturing method thereof.

[0005]

Means for Solving the Problems FIGS. 1 (e) and 2
As shown in (e), in the multilayer wiring board 10 for a multi-chip module of the present invention, an insulating layer 12 and a conductor layer 13 are laminated on a substrate 11, the insulating layer 12 is made of SiO ₂ , and the conductor layer 13 is It is characterized by being made of Au. FIG. 1 (a)
As shown in (e) to (e), the first manufacturing method of the present invention includes a step of forming an insulating layer 12 made of SiO ₂ by applying a silicon alkoxide solution on the conductor layer 13 and baking the same, and A step of forming a through hole 14 in the layer 12, and a step of forming a conductor layer 13 made of Au by coating an organic compound solution containing Au on the insulating layer 12 in which the through hole 14 is formed and baking the solution. And a step of forming a conductor layer 13 made of Au to be a wiring portion based on the wiring pattern. When forming multiple layers on the substrate 11, the steps shown in FIGS. 1B to 1E are repeated.

As shown in FIGS. 2 (a) to 2 (e), in the second production method of the present invention, a silicon alkoxide solution and an organometallic compound having a photosensitive ligand are mixed on the conductor layer 13. The step of applying the liquid to form the SiO ₂ precursor layer 12a, and the ultraviolet non-transmissive portion 15 in the portion to be the through hole 14.
a is formed on the first mask 15 by the SiO ₂ precursor layer 12
and the step of coating the first mask 15 with S
The step of irradiating the iO ₂ precursor layer 12a with ultraviolet rays, the step of developing the SiO ₂ precursor layer 12a irradiated with ultraviolet rays, the step of firing the developed SiO ₂ precursor layer 12a, and the through holes 14 on the conductor layer 13 A step of forming an insulating layer 12 made of SiO ₂ having a hole, and applying a mixed solution of an Au-containing organic compound solution and an organometallic compound having a photosensitive ligand on the insulating layer 12 having the through hole 14. To form the Au precursor layer 13a, and to cover the Au precursor layer 13a with the second mask 16 having the ultraviolet ray non-transmitting portion 16a corresponding to the wiring pattern.
The step of irradiating the Au precursor layer 13a covering the mask 16 with ultraviolet rays, the step of developing the Au precursor layer 13a irradiated with ultraviolet rays, the step of firing the developed Au precursor layer 13a, and the insulation having the through holes 14. And a step of forming a conductor layer 13 made of Au to be a wiring portion on the layer 12. When forming multiple layers on the substrate 11, FIG.
The steps shown in (e) are repeated.

The present invention will be described in detail below. Substrate 1 of the present invention
1 is an insulating ceramic substrate such as an Al ₂ O ₃ (alumina) substrate, an AlN (aluminum nitride) substrate, a SiC (silicon carbide) substrate, or a tungsten substrate, a molybdenum substrate,
It is selected from metal substrates such as copper substrates. In addition, S of the present invention
The insulating layer 12 made of iO ₂ is formed on the substrate 11 or the conductor layer 13
Formed on top. The thickness of the insulating layer 12 made of SiO ₂ is preferably 0.1 to 10.0 μm, and 1.0 to 5.0 μm.
μm is more preferred. If the thickness of the insulating layer 12 is less than 0.1 μm, the dielectric strength is poor, and if it exceeds 10.0 μm, SiO 2
₂ is easily cracked. In the first production method, a solution containing a silicon alkoxide such as ethyl silicate is applied by a method such as spin coating, dip coating or spray coating, a thin film is obtained by a sol-gel method, and then the thin film is baked to form the film. . The through hole 14 is formed by performing dry etching with ion plasma or the like or wet etching with hydrofluoric acid, a strong alkaline solution or the like on a predetermined portion of the insulating layer formed by the first manufacturing method. In the second production method, a mixed solution of the above-mentioned silicon alkoxide solution and an organometallic compound having a photosensitive ligand such as orthonitrobenzyl alcohol is applied and dried in the same manner as in the first production method to produce SiO ₂ After forming the precursor layer, covering the first mask, irradiating with ultraviolet rays and developing,
By baking, an insulating layer in which a through hole is formed in the ultraviolet ray non-transmissive portion of the first mask is obtained.

The conductor layer 13 of Au of the present invention is formed on the insulating layer 12 or the substrate 11. The thickness of the conductor layer 13 made of Au is preferably 0.01 to 1.0 μm, more preferably 0.2 to 0.5 μm. If the thickness of the conductor layer 13 is less than 0.01 μm, the sheet resistance value is high (the conductivity is low), and if it exceeds 1.0 μm, it is difficult for Au to become a conductor film. In the first manufacturing method, an Au-containing organic compound solution is applied by a method such as spin coating, dip coating, or spray coating, dried, and then baked. In the second production method, a mixed solution of the above-mentioned Au-containing organic compound solution and an organometallic compound having a photosensitive ligand such as orthonitrobenzyl alcohol is applied and dried in the same manner as in the first production method. To form a Au precursor layer, cover the second mask, irradiate with ultraviolet rays to develop, and then bake to obtain a conductor layer made of Au to be a wiring portion in the ultraviolet ray non-transmissive portion of the second mask. The Au contained in the organic compound solution is 15 in the solution.
It is preferably contained in an amount of ˜75 wt%. 20 to 50% by weight is more preferable. If the content of Au is less than 15% by weight, it is difficult to obtain a continuous and dense thin film, and if it exceeds 75% by weight, the adhesion to the insulating layer or the substrate becomes poor. In the organic compound solution of the present invention, Au is not in a powder state but forms a compound with an organic component and is in a liquid state, so that a continuous thin film having a thickness of 1 μm or less can be obtained. An organic substance such as α-terpineol or ethyl cellulose is added to this organic compound to form a solution. This organic substance imparts viscosity to the solution to enhance the coatability and has a function as a binder after firing.

[0009]

According to the manufacturing method of the present invention, both the insulating layer and the conductor layer can be formed by a wet process.
It is simple and can be manufactured at low cost, and defects such as pinholes are less likely to occur even if the layer thickness is thin, and the hole diameter of the through hole formed in the insulating layer can be reduced.

[0010]

EXAMPLES Next, the present invention will be explained based on examples. Example 1 First, as shown in FIG. 2A, the thickness is 1.0
The alumina sintered body 11 having a size of 50 mm was cut out into a square of 50 mm × 50 mm, and the surface thereof was polished. Then, the Au conductor layer 13 having a thickness of 0.3 μm was formed on the entire surface of the sintered body 11. Specifically, a commercially available organic compound paste containing 18% by weight of Au (manufactured by NE Chemcat, trade name: A-4615) is diluted with a thinner to form a solution, and the solution is spin-coated on the sintered body 11. Then, the conductor layer 13 was formed by applying, drying and baking at 120 ° C.

On the other hand, a silicon alkoxide solution having the following composition was added to ortho-nitrobenzyl alcohol (C ₆ H ₄ NO ₂ CH ₂
OH) was added 1 to 2 times by mole to prepare a mixed solution. Ethyl silicate _{(Si (OC 2 H 5)} 4) 34.8 % by weight ethyl alcohol (C ₂ H ₅ OH) 50.0 wt%, 0.3% HCl 6.0% by weight Isopropyl alcohol 9.2 2 wt% As shown in FIG. 2 (b), the mixed solution is applied onto the conductor layer 13 by the spin coating method to form the SiO ₂ precursor layer 12a. The glass mask 15 on which 15a is formed is S
The iO ₂ precursor layer 12a was coated. Subsequently, the SiO ₂ precursor layer 12a covering the mask 15 was irradiated with ultraviolet rays.
As a result, the portion other than the portion to be the through hole 14 was exposed and cured. S exposed to a developing solution in which 2-methoxyethanol and isopropyl alcohol were mixed in a weight ratio of 1: 1
After developing the iO ₂ precursor layer 12a, it was dried at 300 ° C. By repeating the process from the spin coating of the above mixed solution to the drying after development of the SiO ₂ precursor layer 12a five times, and then baking at 600 to 900 ° C.
As shown in (c), an insulating layer 12 made of SiO ₂ having a thickness of 3.0 μm having through holes 14 having a hole diameter of 10 to 20 μm was formed.

Next, a commercially available organic compound paste containing 18% by weight of Au (manufactured by NE Chemcat, trade name:
A-4615) was prepared ortho-nitrobenzyl alcohol _{(C 6 H 4 NO 2 CH} 2 OH) 1~2 moles added to mixed liquid to the solution diluted with a thinner. As shown in FIG. 2 (d),
The mixed solution is applied onto the insulating layer 12 having the through holes 14 by a spin coating method to form the Au precursor layer 13
After forming a, the Au precursor layer 13a was covered with the glass mask 16 in which the ultraviolet ray non-transmissive portion 16a was formed in accordance with the wiring pattern. Subsequently, the Au precursor layer 13a covering the mask 16 was irradiated with ultraviolet rays. As a result, the wiring portion was exposed and cured. After developing the Au precursor layer 13a exposed with a developing solution in which 2-methoxyethanol and isopropyl alcohol are mixed in a weight ratio of 1: 1, the Au precursor layer 13a is dried at 120 ° C. and baked at 500 to 900 ° C.
As shown in (e), a conductor layer 13 made of Au having a thickness of 0.3 μm was formed. Hereinafter, the steps shown in FIGS. 2B to 2E are repeated, and the conductor layer-insulating layer-conductor layer-insulating layer-
A multi-layer wiring board 10 for a multi-chip module having five conductor layers was obtained.

Comparative Example 1 On the same sintered body 2 as in Example 1, Cu was first sputtered to form a wiring portion 1 having a thickness of 1.0 μm, as shown in FIG. Then, a polyimide solution was spin-coated to cover the wiring portion 1 and the sintered body 2, dried, and baked at 400 ° C. in a nitrogen atmosphere to form an insulating layer 3 made of polyimide having a thickness of 15.0 μm. . Next, as shown in FIG. 3B, through holes 4 having a hole diameter of 20 to 100 μm were formed by photolithography, and then Cr was sputtered to form a Cr layer (not shown). Subsequently, as shown in FIG. 3C, after Cu was sputtered, a wiring portion 5 having a thickness of 1.0 μm was formed based on the pattern by photolithography. As shown in FIG. 3D, a polyimide solution is coated again to form an insulating layer 6 made of polyimide having a thickness of 15.0 μm, and a Cr layer is formed. Then, through holes 7 are formed in the same manner as in FIG. 3B. Was formed. FIG. 3C and FIG.
The step shown in (d) was repeated to obtain a multi-layer wiring board 8 for a multi-chip module consisting of five layers of conductor layer-insulating layer-conductor layer-insulating layer-conductor layer.

<Evaluation> In order to compare the performances of the multilayer wiring boards for multichip modules of Example 1 and Comparative Example 1, a comparative test was performed on the dielectric strength, dielectric constant, dielectric loss and thermal conductivity of the multilayer wiring boards. . Table 1 shows the results.

[0015]

[Table 1]

As is clear from Table 1, the multilayer wiring board 10 of Example 1 has a higher insulating property, a lower dielectric constant, a lower dielectric loss and a higher insulating layer than the multilayer wiring board 8 of Comparative Example 1. It was found to have thermal conductivity. Further, the total thickness of the insulating layer and the conductor layer of Example 1 after being laminated is about one fifth of that of Comparative Example 1.
Met.

[0017]

As described above, as compared with the conventional multilayer wiring board made of Cu / polyimide, the Au / Si of the present invention is used.
The multilayer wiring board made of O ₂ has the following features. The insulating layer made of SiO ₂ may have a thickness of about 1/20 of the conventional thickness in order to obtain a desired withstand voltage, and thus the hole diameter of the through hole may be small. Since the insulating layer is an inorganic material of SiO ₂ , the thermal conductivity is as high as 0.0045 cal / s · cm · ° C, and the heat resistance temperature is as high as about 700 ° C. Therefore, the LSI is
Even when the IC is mounted, the heat dissipation from the LSI is good and the thermal reliability is excellent. Even if the insulating layer is SiO ₂ , the dielectric constant is as low as that of polyimide, and the conductive layer made of Au has a sheet resistance value as low as that of Cu, so that the signal propagation speed is high. A Cr layer is not required between the insulating layer and the conductor layer as in the prior art, and all film formation can be performed by a wet process, so that the manufacturing process is simple and inexpensive.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a first multilayer wiring board for a multi-chip module of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a second multilayer wiring board for a multi-chip module of the present invention.

FIG. 3 is a diagram showing a manufacturing process of a conventional multilayer wiring board for a multichip module.

[Explanation of symbols]

10 multichip multilayer wiring board 11 substrate 12 made of SiO ₂ insulating layer 12a SiO ₂ precursor layer 13 conductive layer made of Au 13a Au precursor layer 14 through holes 15 UV first mask 15a opaque areas 16 second mask module 16a UV non-transmissive part

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Nakabayashi 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Central Research Laboratory, Mitsubishi Materials Corporation

Claims (5)

[Claims] 1. A multi-layer wiring board for a multi-chip module comprising an insulating layer (12) and a conductor layer (13) laminated on a substrate (11), wherein the insulating layer (12) is made of SiO _2. A multilayer wiring board for a multichip module, wherein the layer (13) is made of Au. _{2. The} insulating layer (12) made of SiO ₂ has a thickness of 0.1 to 10.0 μm and a conductor layer (1) made of Au.
The multilayer wiring board for a multichip module according to claim 1, wherein the thickness of 3) is 0.01 to 1.0 μm. 3. A method for manufacturing a multi-layer wiring board for a multi-chip module, comprising laminating an insulating layer (12) and a conductor layer (13) on a substrate (11), wherein the substrate (11) or the conductor layer (13) is provided. A step of forming an insulating layer (12) made of SiO ₂ by applying a silicon alkoxide solution on the top and baking the step; forming a through hole (14) in the insulating layer (12); A step of forming a conductor layer (13) made of Au by applying an organic compound solution containing Au on the insulating layer (12) having the layer formed thereon or on the substrate (11) and baking the solution; Conductor layer made of Au that becomes the wiring part based on
A method of manufacturing a multilayer wiring board for a multi-chip module, including the step of forming (13). 4. The method for manufacturing a multilayer wiring board for a multi-chip module according to claim 2, wherein the through holes (14) are formed by dry etching or wet etching. 5. A method for manufacturing a multi-layer wiring board for a multi-chip module, comprising laminating an insulating layer (12) and a conductor layer (13) on a substrate (11), wherein the substrate (11) or the conductor layer (13). A step of forming a SiO ₂ precursor layer (12a) by applying a mixed solution of a silicon alkoxide solution and an organometallic compound having a photosensitive ligand on top of it, and exposing the portion to be the through hole (14) to ultraviolet light The first mask (15) having the transparent portion (15a) is formed on the SiO ₂ precursor layer (12a).
And a step of irradiating the SiO ₂ precursor layer (12a) covering the first mask (15) with ultraviolet rays, and a step of developing the SiO ₂ precursor layer (12a) irradiated with the ultraviolet rays. The substrate is obtained by baking the developed SiO ₂ precursor layer (12a).
S having through hole (14) on (11) or on conductor layer (13)
forming an insulating layer made of iO ₂ (12), said insulating layer having a through hole (14) (12) or on said substrate (11) an organic compound of Au-containing on the solution and the light-sensitive ligand Forming a Au precursor layer (13a) by applying a mixed liquid with an organometallic compound having a second mask (16) having an ultraviolet ray non-transmitting portion (16a) formed corresponding to the wiring pattern. Coating the Au precursor layer (13a), irradiating the Au precursor layer (13a) coated with the second mask (16) with ultraviolet light, and irradiating the Au precursor layer (13a) with ultraviolet light ) Is developed, and the developed Au precursor layer (13a) is baked to form a wiring portion on the insulating layer (12) having the through hole (14) or the substrate (11). A method of manufacturing a multilayer wiring board for a multi-chip module, comprising the step of forming a conductor layer (13).