JPH08298332A - Manufacture of photovoltaic device - Google Patents

Manufacture of photovoltaic device

Info

Publication number
JPH08298332A
JPH08298332A JP7102596A JP10259695A JPH08298332A JP H08298332 A JPH08298332 A JP H08298332A JP 7102596 A JP7102596 A JP 7102596A JP 10259695 A JP10259695 A JP 10259695A JP H08298332 A JPH08298332 A JP H08298332A
Authority
JP
Japan
Prior art keywords
film
insulating layer
layer
amorphous silicon
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7102596A
Other languages
Japanese (ja)
Other versions
JP3281760B2 (en
Inventor
Norihiro Terada
典裕 寺田
Yasuki Harada
康樹 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10259695A priority Critical patent/JP3281760B2/en
Publication of JPH08298332A publication Critical patent/JPH08298332A/en
Application granted granted Critical
Publication of JP3281760B2 publication Critical patent/JP3281760B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

PURPOSE: To prevent constituent elements diffusing from an insulating layer to semiconductor, abate the influence of partial defect of a semiconductor layer, and improve photovoltaic characteristics, by forming the insulating layer after the semiconductor layer is formed, when a photovoltaic device having unevenness on the light incidence side is manufactured. CONSTITUTION: After unevenness is formed on the surface of an N-type polycrystalline silicon film 1 (a), an I-type amorphous silicon layer 2 and a P-type amorphous silicon layer 3 are continuously formed on the polycrystalline silicon film 1 by using a plasma CVD method (b), and an insulating layer 7 composed of an SiO2 film is formed on the amorphous silicon layer 3 (c). A surface electrode 4 composed of an ITO film is formed on the insulating layer 7 (d). Finally a collecting electrode 5 composed of a Ti/Ag film is formed on the front electrode 4, and a rear electrode 6 is formed on the other flat surface of the polycrystalline silicon film 1 (e). An insulating layer composed of SiO2 or SiN may be formed by oxidizing or nitriding a part of the P-type amorphous silicon layer 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体層を積層してな
る光起電力装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a photovoltaic device in which semiconductor layers are laminated.

【0002】[0002]

【従来の技術】光起電力装置において、照射光を効率良
く利用できるように光路長を長くして吸収量を多くすべ
く、光入射側表面を凹凸化させることにより光閉じ込め
効果を利用することが行われている。図6は、このよう
な従来の光起電力装置の構造図である。図6において、
51は表面に凹凸を有するn型の多結晶シリコン膜であ
り、多結晶シリコン膜51上に、i型の非晶質シリコン層
52及びp型の非晶質シリコン層53がこの順に積層されて
いる。非晶質シリコン層53上には、光入射側の表面電極
54及び集電極55が形成され、多結晶シリコン膜51の平坦
な方の表面には裏面電極56が形成されている。
2. Description of the Related Art In a photovoltaic device, the light confinement effect is utilized by making the surface on the light incident side uneven so as to lengthen the optical path and increase the absorption amount so that the irradiation light can be used efficiently. Is being done. FIG. 6 is a structural diagram of such a conventional photovoltaic device. In FIG.
Reference numeral 51 is an n-type polycrystalline silicon film having irregularities on the surface. An i-type amorphous silicon layer is formed on the polycrystalline silicon film 51.
52 and a p-type amorphous silicon layer 53 are laminated in this order. On the amorphous silicon layer 53, a light-incident side surface electrode
A collector electrode 55 and a collector electrode 55 are formed, and a back surface electrode 56 is formed on the flat surface of the polycrystalline silicon film 51.

【0003】確かに、このように光入射側に凹凸形状を
採用することにより取り出される電流は増加するが、こ
の多結晶シリコン膜51の凹部または凸部には薄膜の半導
体層が形成されにくく、多結晶シリコン膜51のような凹
凸化させた半導体の表面に薄膜の半導体層を均一に積層
することは難しい。従って、形成すべき半導体薄膜が部
分的に欠損(図6のA部分)または薄くなることが避け
られず、この結果、却って光起電力特性が劣化するとい
う問題があった。
Certainly, although the current taken out is increased by adopting the concave-convex shape on the light incident side as described above, it is difficult to form a thin semiconductor layer on the concave or convex portion of the polycrystalline silicon film 51. It is difficult to uniformly deposit a thin semiconductor layer on the surface of an uneven semiconductor such as the polycrystalline silicon film 51. Therefore, it is unavoidable that the semiconductor thin film to be formed is partially defective (portion A in FIG. 6) or thin, and as a result, there is a problem that the photovoltaic characteristics are rather deteriorated.

【0004】このような問題を解決する手段として、ガ
ラス上の凹凸透明電極上に予め絶縁層を形成し、この上
に導電型が異なる複数の非晶質薄膜半導体層(例えばp
in非晶質シリコン積層体)を形成した非晶質光起電力
装置が考案されている(特公平5−74951 号公報)。こ
の光起電力装置では、透明電極上に絶縁層を形成するこ
とにより、透明電極の凹凸面の凹凸状態を緩和して、該
透明電極上に非晶質半導体層が均一に積層されやすくす
ると共に、この絶縁層上に積層された非晶質薄膜半導体
層を凸部が突き抜けることを防止し、その凹凸形状によ
る光起電力特性の向上を確保できるようにしている。
As a means for solving such a problem, an insulating layer is formed in advance on a concavo-convex transparent electrode on glass, and a plurality of amorphous thin film semiconductor layers having different conductivity types (for example, p.
An amorphous photovoltaic device having an in-amorphous silicon laminated body has been devised (Japanese Patent Publication No. 5-74951). In this photovoltaic device, by forming an insulating layer on the transparent electrode, the uneven state of the uneven surface of the transparent electrode is relaxed, and the amorphous semiconductor layer is easily laminated evenly on the transparent electrode. The convex portion is prevented from penetrating the amorphous thin film semiconductor layer laminated on the insulating layer, and the improvement of the photovoltaic characteristic due to the concave and convex shape can be ensured.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、特公平
5−74951 号公報に開示された光起電力装置では、絶縁
層,非晶質薄膜半導体層の順に形成するので、先に形成
された絶縁層が、非晶質薄膜半導体層の形成時に熱及び
プラズマにさらされるために、絶縁層の構成元素が非晶
質薄膜半導体層中に拡散し、その膜特性が劣化して光起
電力特性が低下するという問題点が残されていた。
However, in the photovoltaic device disclosed in Japanese Patent Publication No. 5-74951, the insulating layer and the amorphous thin film semiconductor layer are formed in this order. However, when the amorphous thin film semiconductor layer is formed, it is exposed to heat and plasma, so that the constituent elements of the insulating layer diffuse into the amorphous thin film semiconductor layer, and the film characteristics deteriorate and the photovoltaic characteristics decrease. There was a problem of doing.

【0006】本発明は斯かる事情に鑑みてなされたもの
であり、薄膜半導体層を形成した後に絶縁層を形成する
ことにより、薄膜半導体層の部分的欠損に起因する光起
電力特性の劣化を防止すると共に、絶縁層の構成元素の
拡散に伴う光起電力特性の低下を防止できる光起電力装
置の製造方法を提供することを目的とする。
The present invention has been made in view of such circumstances, and by forming an insulating layer after forming a thin film semiconductor layer, deterioration of photovoltaic characteristics due to a partial defect of the thin film semiconductor layer is prevented. It is an object of the present invention to provide a method for manufacturing a photovoltaic device, which is capable of preventing the deterioration of photovoltaic characteristics due to diffusion of constituent elements of the insulating layer.

【0007】[0007]

【課題を解決するための手段】本願に係る第1発明の光
起電力装置の製造方法は、表面に凹凸が存在する半導体
上に、1または複数の半導体薄膜を積層してなり、前記
半導体及び半導体薄膜への光照射により起電力を生じる
光起電力装置を製造する方法において、前記半導体薄膜
の上に絶縁層を積層形成する工程を有することを特徴と
する。
According to a first aspect of the present invention, there is provided a method for manufacturing a photovoltaic device, which comprises laminating one or a plurality of semiconductor thin films on a semiconductor having unevenness on the surface. A method of manufacturing a photovoltaic device that generates an electromotive force by irradiating a semiconductor thin film with light, comprising the step of forming an insulating layer on the semiconductor thin film.

【0008】本願に係る第2発明の光起電力装置の製造
方法は、表面に凹凸が存在する半導体上に、1または複
数の半導体薄膜を積層してなり、前記半導体及び半導体
薄膜への光照射により起電力を生じる光起電力装置を製
造する方法において、前記半導体薄膜の上部を絶縁化し
て絶縁層を形成する工程を有することを特徴とする。
In the method for manufacturing a photovoltaic device according to the second aspect of the present invention, one or a plurality of semiconductor thin films are laminated on a semiconductor having unevenness on the surface, and the semiconductor and the semiconductor thin film are irradiated with light. A method of manufacturing a photovoltaic device that generates an electromotive force according to claim 1, comprising the step of insulating the upper portion of the semiconductor thin film to form an insulating layer.

【0009】[0009]

【作用】第1発明では、表面に凹凸が存在する半導体上
に半導体薄膜,絶縁層をこの順に積層形成する。また、
第2発明では、表面に凹凸が存在する半導体上に半導体
薄膜を積層形成し、その半導体薄膜の上部を酸化処理ま
たは窒化処理により絶縁層に変える。このようにする
と、半導体薄膜の形成時にその内部に絶縁層の構成元素
が拡散するという従来の問題点を解決し、光起電力特性
の低下を防ぐ。また、もし半導体薄膜の欠損が生じて
も、絶縁層は凹凸化された光入射側の表面に形成されて
いるので、その欠損部分において、半導体層/絶縁層/
電極構造のMIS型太陽電池を形成し、半導体薄膜の欠
損に伴う光起電力特性の低下を補償する。
In the first aspect of the invention, the semiconductor thin film and the insulating layer are laminated in this order on the semiconductor having unevenness on the surface. Also,
In the second invention, a semiconductor thin film is laminated on a semiconductor having unevenness on the surface, and the upper portion of the semiconductor thin film is converted into an insulating layer by oxidation treatment or nitriding treatment. This solves the conventional problem that the constituent elements of the insulating layer diffuse inside the semiconductor thin film when it is formed, and prevents the deterioration of the photovoltaic characteristics. Further, even if the semiconductor thin film is damaged, the insulating layer is formed on the uneven surface of the light incident side. Therefore, in the defective part, the semiconductor layer / insulating layer /
An MIS type solar cell having an electrode structure is formed to compensate for a decrease in photovoltaic characteristics due to a defect in a semiconductor thin film.

【0010】[0010]

【実施例】以下、本発明をその実施例を示す図面に基づ
いて具体的に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments.

【0011】多結晶シリコン上に非晶質シリコンを形成
したヘテロ接合光起電力装置において、poly-Si(n型)
/a-Si(i型)/a-Si(p型)構造のHIT(Heteroju
nction with Intrinsic Thin-layer)型の光起電力装置
について、本発明の実施例を説明する。
In a heterojunction photovoltaic device in which amorphous silicon is formed on polycrystalline silicon, poly-Si (n-type)
/ A-Si (i type) / a-Si (p type) HIT (Heteroju
An embodiment of the present invention will be described with respect to a photovoltaic device of the nction with Intrinsic Thin-layer type.

【0012】図1は、本発明の製造方法にて製造したこ
のようなHIT型の光起電力装置の構造図である。図1
において、1は表面に凹凸を有するn型の多結晶シリコ
ン膜(膜厚: 300μm)であり、多結晶シリコン膜1上
に、i型の非晶質シリコン層2(膜厚:10〜200 Å)及
びp型の非晶質シリコン層3(膜厚:50〜200 Å)がこ
の順に積層されている。非晶質シリコン層3上には、S
iO2 膜からなる絶縁層7(膜厚:5〜50Å)が形成さ
れている。また、絶縁層7上には、ITO膜からなる表
面電極4(膜厚:500 〜1500Å)及びTi/Ag膜から
なる集電極5(幅5μm以下×厚さ5μm)が形成さ
れ、多結晶シリコン膜1の平坦な方の表面にはAl膜か
らなる裏面電極6(厚さ2μm以下)が形成されてい
る。なお、積層すべき非晶質シリコン層2,3が成膜さ
れずに欠損している部分(B部分)が存在している。
FIG. 1 is a structural diagram of such a HIT type photovoltaic device manufactured by the manufacturing method of the present invention. FIG.
In FIG. 1, 1 is an n-type polycrystalline silicon film (thickness: 300 μm) having irregularities on the surface, and an i-type amorphous silicon layer 2 (thickness: 10 to 200 Å) on the polycrystalline silicon film 1. ) And a p-type amorphous silicon layer 3 (film thickness: 50 to 200 Å) are laminated in this order. On the amorphous silicon layer 3, S
An insulating layer 7 (film thickness: 5 to 50Å) made of an iO 2 film is formed. On the insulating layer 7, a surface electrode 4 made of an ITO film (film thickness: 500 to 1500Å) and a collector electrode 5 made of a Ti / Ag film (width 5 μm or less × thickness 5 μm) are formed. A back electrode 6 (thickness of 2 μm or less) made of an Al film is formed on the flat surface of the film 1. It should be noted that there is a portion (B portion) where the amorphous silicon layers 2 and 3 to be laminated are not formed and are missing.

【0013】次に、このような構成の光起電力装置の製
造方法について説明する。
Next, a method of manufacturing the photovoltaic device having such a structure will be described.

【0014】図2は、その製造方法の第1例の工程を示
す断面図である。まず、n型の多結晶シリコン膜1を洗
浄した後、水酸化ナトリウム水溶液を用いた面方位性エ
ッチングにより、ピッチ及び高さが10μm程度の凹凸を
多結晶シリコン膜1の一方の表面に形成する(図2
(a))。次に、プラズマCVDにより、多結晶シリコ
ン膜1の凹凸表面上に、i型の非晶質シリコン層2及び
p型の非晶質シリコン層3を連続的に形成する(図2
(b))。この際、部分的に非晶質シリコン層2,3が
形成されず、欠損部分(C部分)が生じる。なお、この
ときのプラズマCVDによる形成条件は、以下の通りで
ある。 i型の非晶質シリコン層2 原料ガス:SiH4 ,成膜温度: 120℃,圧力: 0.2T
orr,パワー:30mW/cm2 p型の非晶質シリコン層3 原料ガス:B2 6 :SiH4 :H2 = 0.1:5:100
,成膜温度: 120℃,圧力: 0.2Torr,パワー:3
0mW/cm2
FIG. 2 is a sectional view showing the steps of the first example of the manufacturing method. First, after cleaning the n-type polycrystalline silicon film 1, unevenness having a pitch and a height of about 10 μm is formed on one surface of the polycrystalline silicon film 1 by plane orientation etching using an aqueous solution of sodium hydroxide. (Fig. 2
(A)). Next, the i-type amorphous silicon layer 2 and the p-type amorphous silicon layer 3 are continuously formed on the uneven surface of the polycrystalline silicon film 1 by plasma CVD (FIG. 2).
(B)). At this time, the amorphous silicon layers 2 and 3 are not partially formed, and a defective portion (C portion) is generated. The formation conditions by plasma CVD at this time are as follows. i-type amorphous silicon layer 2 source gas: SiH 4 , film forming temperature: 120 ° C., pressure: 0.2T
orr, power: 30 mW / cm 2 p-type amorphous silicon layer 3 source gas: B 2 H 6 : SiH 4 : H 2 = 0.1: 5: 100
, Film formation temperature: 120 ℃, Pressure: 0.2 Torr, Power: 3
0 mW / cm 2

【0015】次に、プラズマCVDにより、非晶質シリ
コン層3上にSiO2 膜からなる絶縁層7を形成する
(図2(c))。次いで、スパッタ法にて、ITO膜か
らなる表面電極4を絶縁層7上に形成する(図2
(d))。最後に、表面電極4上にTi/Ag膜からな
る集電極5を、多結晶シリコン膜1の他方の平坦な表面
にAl膜からなる裏面電極6を、何れも蒸着により形成
する(図2(e))。
Next, an insulating layer 7 made of a SiO 2 film is formed on the amorphous silicon layer 3 by plasma CVD (FIG. 2 (c)). Then, the surface electrode 4 made of an ITO film is formed on the insulating layer 7 by the sputtering method (FIG. 2).
(D)). Finally, a collector electrode 5 made of a Ti / Ag film is formed on the surface electrode 4 and a back electrode 6 made of an Al film is formed on the other flat surface of the polycrystalline silicon film 1 by vapor deposition (see FIG. 2 ( e)).

【0016】図3は、その製造方法の第2例の工程を示
す断面図である。まず、n型の多結晶シリコン膜1を洗
浄した後、第1例と同様の手法にて、その一方の表面に
ピッチ及び高さが10μm程度の凹凸を形成する(図3
(a))。次に、プラズマCVDにより、多結晶シリコ
ン膜1の凹凸表面上に、i型の非晶質シリコン層2及び
p型の非晶質シリコン層3を連続的に形成する(図3
(b))。なお、このときのプラズマCVDによる形成
条件は、第1例と同様である。この際、非晶質シリコン
層2,3の成膜が不十分であって他の領域よりもその膜
厚が薄くなる部分(D部分)が部分的に生じる。
FIG. 3 is a sectional view showing the steps of the second example of the manufacturing method. First, after cleaning the n-type polycrystalline silicon film 1, unevenness having a pitch and a height of about 10 μm is formed on one surface of the n-type polycrystalline silicon film 1 by the same method as in the first example (FIG. 3).
(A)). Next, the i-type amorphous silicon layer 2 and the p-type amorphous silicon layer 3 are continuously formed on the uneven surface of the polycrystalline silicon film 1 by plasma CVD (FIG. 3).
(B)). The formation conditions by plasma CVD at this time are the same as those in the first example. At this time, the amorphous silicon layers 2 and 3 are insufficiently formed and a portion (D portion) where the film thickness is smaller than other regions partially occurs.

【0017】次に、硝酸中にこの中間体を浸漬させ、形
成した非晶質シリコン層3の表層側の一部を酸化させる
ことにより絶縁化して、SiO2 膜からなる絶縁層7を
形成する(図3(c))。また、非晶質シリコン層2,
3の成膜が不十分である部分では、両非晶質シリコン層
2,3が酸化されて絶縁層7(SiO2 膜)となる。こ
こで形成される絶縁層7の膜厚は、硝酸の濃度及び温度
, 浸漬時間により決定される。一例として、本実施例で
は、HNO3 :50g/H2 O:1リットル、50℃で1分
間浸すこととし、これにより厚さ20ÅのSiO2 膜を形
成した。なお、硝酸によるシリコンの酸化反応は以下の
通りである。 Si+4HNO3 →SiO2 +4NO2 +2H2
Next, this intermediate is immersed in nitric acid, and a part of the formed amorphous silicon layer 3 on the surface layer side is oxidized to be insulated to form an insulating layer 7 made of a SiO 2 film. (FIG.3 (c)). In addition, the amorphous silicon layer 2,
In the portion where the film formation of 3 is insufficient, both amorphous silicon layers 2 and 3 are oxidized to become the insulating layer 7 (SiO 2 film). The thickness of the insulating layer 7 formed here depends on the concentration of nitric acid and the temperature.
Therefore, it is determined by the immersion time. As an example, in this embodiment, HNO 3 : 50 g / H 2 O: 1 liter was immersed for 1 minute at 50 ° C., thereby forming a SiO 2 film having a thickness of 20 Å. The oxidation reaction of silicon with nitric acid is as follows. Si + 4HNO 3 → SiO 2 + 4NO 2 + 2H 2 O

【0018】次いで、上述の第1例と同様に、スパッタ
法にて、ITO膜からなる表面電極4を絶縁層7上に形
成した後(図3(d))、表面電極4上にTi/Ag膜
からなる集電極5を、多結晶シリコン膜1の他方の平坦
な表面にAl膜からなる裏面電極6を、何れも蒸着によ
り形成する(図3(e))。
Then, similarly to the above-mentioned first example, after the surface electrode 4 made of an ITO film is formed on the insulating layer 7 by the sputtering method (FIG. 3 (d)), Ti / on the surface electrode 4 is formed. A collector electrode 5 made of an Ag film and a back electrode 6 made of an Al film are both formed on the other flat surface of the polycrystalline silicon film 1 by vapor deposition (FIG. 3 (e)).

【0019】上述した実施例において、多結晶シリコン
に代えて単結晶シリコンを用いても良い。また、シリコ
ンの他にゲルマニウムでも良い。また、非晶質シリコン
の代わりにゲルマニウム,シリコンゲルマニウムまたは
シリコンカーボンでも良い。更に、非晶質の代わりに微
結晶を用いてもよい。テクスチャ化は上述したエッチン
グによる場合の他に、切削治具による機械的な加工処理
を行っても良い。
In the above-described embodiments, single crystal silicon may be used instead of polycrystalline silicon. Further, germanium may be used instead of silicon. Further, germanium, silicon germanium, or silicon carbon may be used instead of amorphous silicon. Further, fine crystals may be used instead of amorphous. The texturing may be performed by mechanical processing using a cutting jig, in addition to the above-described etching.

【0020】絶縁層7としては、上述したSiO2 のよ
うな酸化物の他に、SiNのような窒化物またはSiC
のような炭化物も有効である。また、絶縁層7の形成方
法としては、上述した例の他に、プラズマによる非晶質
シリコンの酸化,窒化という処理法も考えられる。
As the insulating layer 7, in addition to the above-mentioned oxide such as SiO 2 , a nitride such as SiN or SiC.
Carbides such as are also effective. Further, as a method of forming the insulating layer 7, in addition to the above-described example, a treatment method of oxidizing and nitriding amorphous silicon by plasma can be considered.

【0021】表面電極4には、上述のITOの他に、Z
nO,SnO2 なども使用可能であり、形成方法は、ス
パッタ法以外にCVD法もある。また、集電極5の形成
方法として、上述の蒸着以外にスパッタ法も可能であ
る。
For the surface electrode 4, in addition to the above-mentioned ITO, Z
nO, SnO 2 or the like can be used, and the forming method includes a CVD method other than the sputtering method. Further, as a method of forming the collecting electrode 5, a sputtering method other than the above vapor deposition is also possible.

【0022】次に、図1に示す構成の本発明の光起電力
装置(以下、本発明例という)と、前述した図6に示す
構成の従来の光起電力装置(以下、従来例という)との
光起電力特性を下記表1に示す。なお、従来例は絶縁層
7(SiO2 膜)が存在しない点だけが異なっており、
他の部分の構成は本発明例と全く同一である。
Next, the photovoltaic device of the present invention having the structure shown in FIG. 1 (hereinafter referred to as the present invention example) and the conventional photovoltaic device having the structure shown in FIG. 6 described above (hereinafter referred to as the conventional example). The photovoltaic characteristics of and are shown in Table 1 below. The conventional example is different only in that the insulating layer 7 (SiO 2 film) does not exist,
The configuration of the other parts is exactly the same as the example of the present invention.

【0023】[0023]

【表1】 [Table 1]

【0024】また、本発明例の効果及び絶縁層7(Si
2 膜)の最適膜厚を検証するために、本発明例におけ
る絶縁層7(SiO2 膜)の膜厚と光起電力特性との関
係を図4に示す。
The effect of the present invention and the insulating layer 7 (Si
In order to verify the optimum film thickness of the O 2 film), FIG. 4 shows the relationship between the film thickness of the insulating layer 7 (SiO 2 film) and the photovoltaic characteristic in the example of the present invention.

【0025】表1,図4の結果から分かるように、絶縁
層7を挿入することにより、光起電力特性の開放電圧V
OC及び短絡電流ISCが向上している。多結晶シリコン上
に形成される非晶質シリコンが下地の凹凸のために部分
的に成膜されていないところが存在すると、従来例で
は、その欠損部分の影響により光起電力特性の低下を招
いていた。本発明例の構造では、その欠損部分(図1の
B部分)に絶縁層7を挟んだMIS型光起電力装置が形
成され、光起電力特性の低下を補償できる。MIS型光
起電力装置においては、絶縁層の膜厚がその光起電力特
性に大きく影響を及ぼす。図4より、絶縁層の膜厚が20
Åのときに変換効率ηが最も高く、5〜50Åの範囲の場
合に、絶縁層が存在しない従来例に比べて光起電力特性
が向上している。これは、MIS型光起電力装置の開放
電圧VOCは絶縁層の膜厚とともに向上するが、膜厚が厚
くなると短絡電流ISCが低下する傾向を持つためであ
る。
As can be seen from the results in Table 1 and FIG. 4, by inserting the insulating layer 7, the open circuit voltage V of the photovoltaic characteristic is
OC and short circuit current I SC are improved. If the amorphous silicon formed on the polycrystalline silicon is not partially formed due to the unevenness of the underlying layer, in the conventional example, the effect of the defective portion causes the deterioration of the photovoltaic characteristics. It was In the structure of the example of the present invention, the MIS type photovoltaic device in which the insulating layer 7 is sandwiched is formed in the defective portion (B portion in FIG. 1), and the deterioration of the photovoltaic characteristic can be compensated. In the MIS type photovoltaic device, the film thickness of the insulating layer has a great influence on its photovoltaic characteristics. From Fig. 4, the thickness of the insulating layer is 20
In case of Å, the conversion efficiency η is the highest, and in the case of 5 to 50Å, the photovoltaic characteristic is improved as compared with the conventional example in which the insulating layer does not exist. This is because the open circuit voltage V OC of the MIS type photovoltaic device increases with the film thickness of the insulating layer, but the short circuit current I SC tends to decrease as the film thickness increases.

【0026】次に、非晶質シリコン光起電力装置への本
発明の適用例について説明する。図5は、このような光
起電力装置の構造図である。図5において、11は表面に
凹凸が形成された基板である。基板11上には、n型の非
晶質シリコン層12(膜厚: 500Å),i型の非晶質シリ
コン層13(膜厚:6000Å),p型の非晶質シリコン層14
(膜厚: 100Å)がこの順に積層形成されている。ま
た、非晶質シリコン層14上には、SiO2 膜からなる絶
縁層15, ITO膜からなる光入射側電極としての表面電
極16及びTi/Ag膜からなる集電極17が形成され、が
この順に形成されている。
Next, an application example of the present invention to an amorphous silicon photovoltaic device will be described. FIG. 5 is a structural diagram of such a photovoltaic device. In FIG. 5, reference numeral 11 is a substrate having irregularities formed on its surface. On the substrate 11, an n-type amorphous silicon layer 12 (film thickness: 500Å), an i-type amorphous silicon layer 13 (film thickness: 6000Å), a p-type amorphous silicon layer 14
(Film thickness: 100Å) is laminated in this order. On the amorphous silicon layer 14, an insulating layer 15 made of a SiO 2 film, a surface electrode 16 made of an ITO film as a light incident side electrode, and a collector electrode 17 made of a Ti / Ag film are formed. Formed in order.

【0027】次に、図5に示す構成の光起電力装置の製
造方法について、簡単に説明する。基板11上に、プラズ
マCVD法により、n型の非晶質シリコン層12,i型の
非晶質シリコン層13,p型の非晶質シリコン層14を連続
的に形成する。この際のプラズマCVDによる形成条件
は、以下の通りである。 n型の非晶質シリコン層12 原料ガス:PH3 :SiH4 =1:10,成膜温度: 120
℃,圧力: 0.2Torr,パワー:30mW/cm2 i型の非晶質シリコン層13 原料ガス:SiH4 ,成膜温度: 200℃,圧力: 0.2T
orr,パワー:30mW/cm2 p型の非晶質シリコン層14 前述の非晶質シリコン層3と同じ
Next, a method of manufacturing the photovoltaic device having the structure shown in FIG. 5 will be briefly described. An n-type amorphous silicon layer 12, an i-type amorphous silicon layer 13, and a p-type amorphous silicon layer 14 are successively formed on the substrate 11 by the plasma CVD method. The formation conditions by plasma CVD at this time are as follows. n-type amorphous silicon layer 12 source gas: PH 3 : SiH 4 = 1: 10, film formation temperature: 120
° C, pressure: 0.2 Torr, power: 30 mW / cm 2 i-type amorphous silicon layer 13 source gas: SiH 4 , deposition temperature: 200 ° C, pressure: 0.2 T
orr, power: 30 mW / cm 2 p-type amorphous silicon layer 14 same as the above-mentioned amorphous silicon layer 3

【0028】その後、上述した実施例と同様に、硝酸中
に浸漬させて、非晶質シリコン層14の酸化によって絶縁
層15を形成する。そして、表面電極16をスパッタ法にて
形成し、集電極17を蒸着により形成する。
After that, as in the above-mentioned embodiment, the insulating layer 15 is formed by immersing it in nitric acid and oxidizing the amorphous silicon layer 14. Then, the surface electrode 16 is formed by a sputtering method, and the collecting electrode 17 is formed by vapor deposition.

【0029】絶縁層としてSiO2 膜を形成した後に、
そのSiO2 膜を半導体層のプロセス温度下にさらすこ
とは、SiO2 膜の元素の拡散を活性化させ、この元素
の混入によって半導体層の特性の低下を招くことにな
る。しかしながら、本実施例でも、半導体層を形成した
後に絶縁層となるSiO2 膜を形成しているので、この
ような問題は発生しない。
After forming a SiO 2 film as an insulating layer,
Exposing the SiO 2 film to the process temperature of the semiconductor layer activates diffusion of an element of the SiO 2 film, and mixing of this element causes deterioration of the characteristics of the semiconductor layer. However, even in the present embodiment, since the SiO 2 film serving as the insulating layer is formed after the semiconductor layer is formed, such a problem does not occur.

【0030】ここで比較のために、図5に示すような非
晶質シリコン光起電力装置において、SiO2 膜の絶縁
層の形成後に 200℃で1時間アニールした場合と、Si
2膜の絶縁層の形成後にそのまま室温で放置した場合
とで、何れもITO膜の表面電極を形成して、2種類の
光起電力装置を製造し、それぞれの光起電力特性を測定
した。その測定結果を下記表2に示す。アニール処理を
行った場合には光起電力特性が低下している。
For comparison, an amorphous silicon photovoltaic device as shown in FIG. 5 was annealed at 200 ° C. for 1 hour after forming an insulating layer of SiO 2 film, and Si was used.
Two types of photovoltaic devices were manufactured by forming a surface electrode of an ITO film in both cases where the insulating layer of the O 2 film was formed and then allowed to stand at room temperature, and the respective photovoltaic properties were measured. . The measurement results are shown in Table 2 below. When the annealing treatment is performed, the photovoltaic characteristics are deteriorated.

【0031】[0031]

【表2】 [Table 2]

【0032】なお、この実施例において、非晶質シリコ
ンの代わりにゲルマニウム,シリコンゲルマニウム,シ
リコンカーボンでも良い。また、非晶質の代わりに微結
晶を用いても良い。
In this embodiment, germanium, silicon germanium, or silicon carbon may be used instead of amorphous silicon. Further, fine crystals may be used instead of amorphous.

【0033】絶縁層の形成後に非晶質半導体をプラズマ
CVDにて形成する場合には、熱に加えてプラズマによ
る表面エネルギも付与されるので、絶縁層の構成元素の
拡散は更に活性化されることが予想される。従って、本
発明のように、半導体層の形成後に絶縁層を形成する方
法では、製造される光起電力装置の特性の向上を図れ
る。
When the amorphous semiconductor is formed by plasma CVD after forming the insulating layer, the surface energy of the plasma is applied in addition to the heat, so that the diffusion of the constituent elements of the insulating layer is further activated. It is expected that. Therefore, according to the method of forming the insulating layer after the formation of the semiconductor layer as in the present invention, the characteristics of the manufactured photovoltaic device can be improved.

【0034】[0034]

【発明の効果】以上のように本発明では半導体薄膜を形
成した後に、絶縁層を成膜するか、または、半導体薄膜
の一部を酸化,窒化等により絶縁層化して絶縁層を形成
するかしたので、結晶系基板の表面に薄膜半導体層を成
膜して形成するHIT構造のような成膜型の接合光起電
力装置、及び、凹凸を形成した非晶質半導体層の表面に
さらに非晶質半導体を形成して接合とした光起電力装置
等の光起電力装置について、半導体薄膜中に絶縁層の構
成元素が拡散して光起電力特性を低下させるという従来
の問題点を解決することが可能となり、光起電力特性を
向上させた光起電力装置を製造することができる。
As described above, according to the present invention, an insulating layer is formed after forming a semiconductor thin film, or a part of the semiconductor thin film is formed into an insulating layer by oxidation, nitriding or the like to form the insulating layer. As a result, a film-type junction photovoltaic device such as a HIT structure in which a thin film semiconductor layer is formed on the surface of a crystalline substrate, and a non-recessed amorphous semiconductor layer is formed on the surface of the amorphous semiconductor layer. In a photovoltaic device such as a photovoltaic device in which a crystalline semiconductor is formed and joined, a conventional problem that a constituent element of an insulating layer diffuses in a semiconductor thin film and deteriorates photovoltaic characteristics is solved. As a result, a photovoltaic device having improved photovoltaic characteristics can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明により製造された光起電力装置の構造図
である。
FIG. 1 is a structural diagram of a photovoltaic device manufactured according to the present invention.

【図2】本発明の製造方法の工程を示す断面図である。FIG. 2 is a cross-sectional view showing steps of the manufacturing method of the present invention.

【図3】本発明の製造方法の工程を示す断面図である。FIG. 3 is a cross-sectional view showing the steps of the manufacturing method of the present invention.

【図4】絶縁層の膜厚と光起電力特性との関係を示すグ
ラフである。
FIG. 4 is a graph showing the relationship between the film thickness of an insulating layer and photovoltaic characteristics.

【図5】本発明により製造された光起電力装置の構造図
である。
FIG. 5 is a structural diagram of a photovoltaic device manufactured according to the present invention.

【図6】従来の方法により製造された光起電力装置の構
造図である。
FIG. 6 is a structural diagram of a photovoltaic device manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

1 多結晶シリコン膜(n型) 2 非晶質シリコン層(i型) 3 非晶質シリコン層(p型) 4 表面電極 5 集電極 6 裏面電極 7 絶縁層 11 基板 12 非晶質シリコン層(n型) 13 非晶質シリコン層(i型) 14 非晶質シリコン層(p型) 15 絶縁層 16 表面電極 17 集電極 DESCRIPTION OF SYMBOLS 1 Polycrystalline silicon film (n type) 2 Amorphous silicon layer (i type) 3 Amorphous silicon layer (p type) 4 Front surface electrode 5 Collection electrode 6 Back surface electrode 7 Insulating layer 11 Substrate 12 Amorphous silicon layer ( n type) 13 amorphous silicon layer (i type) 14 amorphous silicon layer (p type) 15 insulating layer 16 surface electrode 17 collector electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 表面に凹凸が存在する半導体上に、1ま
たは複数の半導体薄膜を積層してなり、前記半導体及び
半導体薄膜への光照射により起電力を生じる光起電力装
置を製造する方法において、前記半導体薄膜の上に絶縁
層を積層形成する工程を有することを特徴とする光起電
力装置の製造方法。
1. A method of manufacturing a photovoltaic device, comprising one or a plurality of semiconductor thin films laminated on a semiconductor having an uneven surface, wherein the semiconductor and the semiconductor thin film generate an electromotive force by light irradiation. A method for manufacturing a photovoltaic device, comprising a step of forming an insulating layer on the semiconductor thin film.
【請求項2】 表面に凹凸が存在する半導体上に、1ま
たは複数の半導体薄膜を積層してなり、前記半導体及び
半導体薄膜への光照射により起電力を生じる光起電力装
置を製造する方法において、前記半導体薄膜の上部を絶
縁化して絶縁層を形成する工程を有することを特徴とす
る光起電力装置の製造方法。
2. A method for manufacturing a photovoltaic device, comprising one or a plurality of semiconductor thin films laminated on a semiconductor having an uneven surface, wherein the semiconductor and the semiconductor thin film generate an electromotive force by light irradiation. A method for manufacturing a photovoltaic device, comprising the step of insulating the upper part of the semiconductor thin film to form an insulating layer.
JP10259695A 1995-04-26 1995-04-26 Method for manufacturing photovoltaic device Expired - Fee Related JP3281760B2 (en)

Priority Applications (1)

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JP10259695A JP3281760B2 (en) 1995-04-26 1995-04-26 Method for manufacturing photovoltaic device

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Application Number Priority Date Filing Date Title
JP10259695A JP3281760B2 (en) 1995-04-26 1995-04-26 Method for manufacturing photovoltaic device

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Publication Number Publication Date
JPH08298332A true JPH08298332A (en) 1996-11-12
JP3281760B2 JP3281760B2 (en) 2002-05-13

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Country Status (1)

Country Link
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