JPH08293544A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor substrate which is provided with a flat surface and can be less dispersed in thickness. CONSTITUTION: A first silicon substrate 1 provided with grooves 3 and a second silicon substrate 4 uniform in thickness are joined direct together by pasting, then the surface of the first substrate 1 is removed as thick as a prescribed amount to make the grooves 3 exposed. A silicon oxide film 6 is formed on the inner side of the grooves 3. A polycrystalline silicon 8 is deposited direct on the surface of the first silicon substrate 1 to be filled into the grooves 3. The polycrystalline silicon 8 is ground as far as prescribed to flatten its surface, and furthermore the polycrystalline silicon 8 is polished as much as a prescribed amount to make the surface of the first silicon substrate 1 exposed. The silicon oxide film 6 formed on the side wall of the groove 3 is removed as thick as a desired depth from the surface of the substrate 1. The surface of the substrate 1 and the surface of the polycrystalline silicon 8 inside the grooves 3 are polished at the same time to make the surface of the groove 3 flat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, it is suitable for manufacturing a semiconductor substrate having an SOI (Silicon On Insulor) structure.

[0002]

2. Description of the Related Art A semiconductor substrate (S
As a method of manufacturing the OI structure), there is a bonding method by direct bonding of silicon substrates. This is because after bonding the silicon substrate through the oxide film (buried oxide film),
This is a method of manufacturing by grinding and polishing until the thickness from the buried oxide film to the surface (polished surface) becomes a desired thickness. The SOI structure has different circuits or elements (MOS,
Bipolar element, power element, etc.), circuit unit, CMO
Since it is possible to perform insulation isolation for each S well unit or for each device unit, it is possible to simultaneously form these different devices and the like on the same chip, which not only makes the chip multifunctional and downsized but also improves reliability. Can be improved.

As a method of partially forming a buried oxide film by using a silicon substrate bonding technique, there is a method disclosed in Japanese Patent Laid-Open No. 96350/1990. This technique will be described with reference to FIGS. 43 to 49.

First, as shown in FIG. 43, two silicon substrates 41 and 42 are bonded together to form a bonded substrate 43. At this time, the substrate on which the element is formed is the first silicon substrate 41, and the substrate supporting the first silicon substrate 41 is the second silicon substrate 42. Also, the bonded substrate stack 4
3, grooves 44 and 45 are formed, and grooves 44 and 45 are formed.
A silicon oxide film 46 is formed on the inner surface of the substrate and between the substrates 41 and 42. The width of the groove 44 is 90 μm
Has a depth of 20 μm, and the groove 45 has a lateral width of 2 μm and a depth of 15 μm. Then, as shown in FIG.
Silicon region separated by the silicon oxide film 46 (SOI
When the layer 47) has a thickness of 10 μm, first, grinding is performed as shown in FIG. 44, and further polishing is performed as shown in FIG. At this time, if the grooves 44 and 45 are exposed by grinding, the grooves 44 and 45 are chipped. Therefore, the grooves 44 and 45 must not be exposed on the entire surface of the substrate in the grinding process. Therefore, as shown in FIG. 44, the grinding is finished at a position above the grooves 44 and 45. The depth of the grooves 44 and 45 is RIE.
When a groove is formed by (reactive ion etching), the wider the width, the deeper the groove becomes. Therefore, the widest groove is the reference for the grinding process (in the case shown in FIG. 43, the groove 44 having a width of 90 μm corresponds to this). Correspondence). Processing accuracy of grinding,
Due to the variation in the depth of the groove and the variation in the thickness of the silicon substrate 42, in order to prevent the groove from being exposed during grinding, the substrate thickness after processing is set to a value obtained by adding a margin to the sum of the depth of the groove and the thickness of the silicon substrate 42. It must be processed so that
Generally, the processing is performed with a margin of at least 5 μm.

In the polishing process shown in FIG. 45, the groove having the smallest groove width (corresponding to the groove 45 having a width of 2 μm in FIG. 43) must be completely exposed. Therefore, the thickness to be removed by polishing is the sum of the thickness on the groove (margin; 5 μm) and the difference in depth (5 μm) due to the difference in groove width. It is necessary to add a margin for processing (for example, a margin of 5 μm). Therefore, when the margin is 5 μm, the polishing allowance is 15 μm, and since the normal polishing allowance is 4 to 8 μm, the polishing allowance is more than twice that. In the polishing process, the larger the stock removal, the worse the processing accuracy. Therefore, FIG.
5, as indicated by t7 and t8 (<t7), the thickness variation of the silicon substrate 41 (SOI layer 47) after polishing the bonded substrate 43 having the groove therein is large.

After this, as shown in FIG. 46, a silicon oxide film 48 is formed on the surface of the substrate by thermal oxidation or the like, and then polycrystalline silicon 49 is deposited by the LPCVD method to form the grooves 44 and 45 in the polycrystalline silicon film. 47, the polycrystalline silicon 4 deposited on the substrate surface by using the silicon oxide film 48 on the substrate surface as a stopper, as shown in FIG.
9 is removed by polishing. Then, as shown in FIG. 48, after removing the silicon oxide film 48 functioning as a stopper, as shown in FIG. 49, polishing is performed again to flatten the substrate surface.

[0007]

In the flattening polishing shown in FIG. 49, the polycrystalline silicon 49 in the grooves 44 and 45 which are convex at a height equal to the removed oxide film thickness is flattened by polishing. The silicon substrate 41 (element formation region) is also polished at this time. Therefore, flattening polishing is polishing with high chemical action to suppress damage (crystal defects) and distortion caused by polishing (polishing under the same conditions as the final polishing that is performed at the end of ordinary silicon substrate manufacturing). There is a need to do. However, the polishing rate of the oxide film is significantly slower than that of silicon due to polishing with a high chemical action, and as a result, the SOI region is shown in FIG. 49 due to the presence of the silicon oxide film 46 on the sidewalls of the grooves 44 and 45. Such polishing sagging occurs. This polishing sag has grooves 44, 4
5 depends on the density of the pattern, and becomes larger as the pattern area becomes sparse. Although polishing sag does not easily occur in the dense pattern region, this is because the silicon oxide film 46 on the sidewalls of the trenches 44 and 45 is dense, so that the silicon substrate 41 is not polished in the dense region. As described above, the thickness variation of the silicon substrate 41 (SOI layer 47) in the substrate after flattening and polishing is worse than the state after polishing in which the grooves 44 and 45 are exposed due to the difference in the amount of polishing due to the polishing sag and the density of the pattern. Become. Further, there is a problem that a step is formed on the surface of the groove due to the difference in polishing rate between the oxide film and silicon.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor substrate in which the surface of the substrate is flat and the thickness variation can be reduced.

[0009]

According to a first aspect of the present invention, there is provided a first step of forming a groove in which an insulating film is formed on a side wall of a surface of a silicon substrate and which is filled with polycrystalline silicon. A second step of removing the insulating film on the sidewall of the groove from the surface of the silicon substrate to a desired depth, and polishing the surface of the silicon substrate and the surface of polycrystalline silicon in the groove at the same time to flatten the surface of the groove portion. The gist is a method of manufacturing a semiconductor substrate including a third step.

According to a second aspect of the invention, in the first step in the first aspect of the invention, the first silicon substrate having a groove and the second silicon substrate having a small thickness variation are directly bonded to each other. After that, a predetermined amount of the surface of the first silicon substrate is removed to expose the groove, and polycrystalline silicon is directly deposited on the surface of the first silicon substrate.
A method for manufacturing a semiconductor substrate, which comprises the steps of grinding a predetermined amount of the polycrystalline silicon to flatten the surface of the polycrystalline silicon and further polishing the polycrystalline silicon by a predetermined amount to expose the surface of the first silicon substrate. The summary will be given.

According to a third aspect of the invention, a semiconductor in which the depth of the insulating film removed in the second step in the first aspect of the invention is equal to the thickness of the silicon substrate removed by polishing in the third step. The gist of the invention is a method of manufacturing a substrate.

[0012]

According to the invention of claim 1, a groove is formed in the surface of the silicon substrate by the first step. An insulating film is formed on the side wall of this groove, and the inside thereof is filled with polycrystalline silicon. By the second step, the insulating film on the side wall of the groove is removed from the surface of the silicon substrate to a desired depth. In the third step, the surface of the silicon substrate and the surface of the polycrystalline silicon in the groove are simultaneously polished to flatten the surface of the groove. At this time, the polishing is performed on the silicon substrate and the polycrystalline silicon without polishing the insulating film, and the thickness variation due to the polishing sag due to the existence of the insulating film is eliminated. Therefore, the variation in the thickness of the substrate can be suppressed to be small, and the groove region on the surface of the substrate can be flattened.

According to the invention of claim 2, in addition to the effect of the invention of claim 1, in the first step, the first silicon substrate having the groove and the second silicon substrate having a small thickness variation are directly bonded. Are bonded together to form a bonded substrate. Further, the surface of the first silicon substrate is removed by a predetermined amount to expose the groove. Then, the polycrystalline silicon is directly deposited on the surface of the first silicon substrate, and the polycrystalline silicon is ground by a predetermined amount to flatten the surface of the polycrystalline silicon. At this time, variation in thickness of the bonded substrate is reduced. More specifically, since the thickness variation of the second silicon substrate in the bonded substrate is small, the thickness variation of the first silicon substrate, that is, the thickness variation of the silicon region that is insulated and separated by the insulating film is reduced. Further, the polycrystalline silicon is polished by a predetermined amount to expose the surface of the first silicon substrate. At this time, the polishing rates of the polycrystalline silicon and the silicon substrate (single crystal silicon) are almost equal, and the variation in the thickness of the substrate after polishing is small. More specifically, there is little variation in the thickness of the silicon region that is insulated and separated by the insulating film.

According to the third aspect, in addition to the function of the first aspect, the depth of the insulating film removed in the second step becomes equal to the thickness of the silicon substrate removed by polishing in the third step. Therefore, the surface of the groove including the insulating film can be flattened.

[0015]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

1 to 11 show the cross-sectional structure of the main part of the dielectric isolation substrate of this embodiment in the manufacturing process order. This embodiment will be described in the order of manufacturing steps.

First, as shown in FIG. 1, a first silicon substrate 1 having at least one surface mirror-polished is prepared. Then, a part of the mirror surface la of the first silicon substrate 1 is selectively etched by chemical etching or RIE to form a recess 2 having a depth of 0.05 to 2.0 μm. further,
As shown in FIG. 2, the recess 2 in the first silicon substrate 1
An annular groove 3 in the peripheral portion (side wall portion of the recess 2) on the bottom surface of the
It is formed by chemical etching or RIE. The groove 3 is formed in two types, one having a large width and a small depth and the other having a small depth.

On the other hand, as shown in FIG. 3, a second silicon substrate 4 is prepared. At least one surface of the second silicon substrate 4 is mirror-polished to have a small thickness variation (for example, parallelism of 1 μm or less). Then, the first silicon substrate 1 and the second silicon substrate 4 are immersed in, for example, a hydrofluoric acid solution having a concentration of 49%, then immersed in pure water, and further dried by spin or the like to remove the first silicon substrate 1 The mirror surface la and the mirror surface 4a of the second silicon substrate 4 are brought into contact with each other to bring them into close contact with each other by hydrogen bond of the silanol group adsorbed on the substrate surface.

Then, as shown in FIG. 4, dry O ₂ , wet O ₂ , or H _{2 is} applied to the silicon substrates 1 and 4.
900 ° C or higher in an oxidizing atmosphere such as a / O ₂ mixed combustion gas,
Two silicon substrates 1 and 4 after heat treatment for 1 hour or more
Are directly bonded and integrated to form a bonded substrate 5. At the same time, the oxidizing atmosphere gas is introduced through the groove 3 and the silicon oxide film 6 is formed on the surface of the recess 2 of the first silicon substrate 1 and the cavity formed by the groove 3 and the second silicon substrate 4.
To form. Through the above steps, a bonded substrate (bonding substrate) 5 in which the silicon oxide film 6 is embedded inside the substrate is formed.

Subsequently, the first silicon substrate 1 is ground from the surface lb side, and as shown in FIG. 5, the first silicon substrate 1 is removed by a predetermined amount. At this time, grinding is performed so that the groove 3 (silicon oxide film 6) is not exposed on the entire surface of the substrate. Further, as shown in FIG. 6, the groove 3 is exposed on the entire surface of the substrate by polishing. At this time, the SOI layer 7 partitioned by the groove 3 is formed, and the thickness of the SOI layer 7 is made thicker than the final aim value (target value). The thickness is determined by the polishing allowance of two polishing operations after the polycrystalline silicon deposition described later. After the polishing process, the thicknesses t1 and t of the silicon substrate 1 (SOI layer 7) are also
2 varies (t2 <t1 in FIG. 6).

Next, as shown in FIG. 7, polycrystalline silicon 8 is deposited on the mirror-polished surface of the first silicon substrate 1 where the groove 3 is exposed by the LPCVD method or the like, and the inside of the groove 3 is filled with the polycrystalline silicon 8. Fill with. The thickness of the polycrystalline silicon 8 deposited at this time is determined by the width of the groove 3 and the depth of the groove 3. In the subsequent grinding step, the larger the machining allowance in grinding is, the easier the processing is. The larger the thickness variation of 7, the larger the stock removal in grinding must be. Therefore, it is desirable to deposit 10 μm or more.

Subsequently, as shown in FIG. 8, the polycrystalline silicon 8 is ground with the other surface of the bonded substrate 5 as a reference. At this time, it is desirable that only the polycrystalline silicon 8 is ground and the processing accuracy is 1 μm or less in parallelism. By this grinding, the thickness variation of the bonded substrate stack 5 is reduced.

That is, as shown in FIG. 6, the first after the groove is exposed.
Although the thickness of the silicon substrate 1 (SOI layer 7) varies within the substrate, the polycrystalline silicon 8 is directly formed on the first silicon substrate 1 and in the groove 3 without forming an oxide film as a polishing stopper on the substrate surface. Is deposited, and the polycrystalline silicon 8 is ground to remove the unevenness corresponding to the pattern of the grooves 3 on the surface of the polycrystalline silicon 8 to flatten the surface, whereby the thickness variation of the bonded substrate 5 is reduced. In addition, this grinding process is done so that it is as parallel as possible with the other surface (back surface) of the substrate as a reference, but its parallelism (difference between maximum and minimum values of substrate thickness) is highly accurate. If a grinding machine capable of processing is used, it can be reduced to 1 μm or less. Second silicon substrate 4
If the parallelism of the substrate is 1 μm or less, the thickness of the polycrystalline silicon on the surface of the substrate after grinding is the first silicon substrate 1 (S
The area where the OI layer 7) is thick (the area on the left side of FIG. 8) is thin,
On the contrary, the thin area (the area on the right side of FIG. 8) becomes thicker.

Next, as shown in FIG. 9, the ground polycrystalline silicon surface is polished to expose the first silicon substrate 1 on the entire surface of the substrate. In this polishing, polycrystalline silicon 8
The first silicon substrate 1 starts to be exposed from the thinnest region, and the thickest region of the polycrystalline silicon 8 is finally exposed. That is, since the polishing process is performed with the back surface of the substrate as a reference as in the grinding process, the first silicon substrate 1
The amount of polishing of the first silicon substrate 1 in the thick region is large (the amount of polishing the polycrystalline silicon 8 is small), and the amount of polishing in the thin region is small (the amount of polishing the polycrystalline silicon 8 is large). When the first silicon substrate 1 is exposed on the entire surface of the substrate, the thickness variation of the first silicon substrate 1 (SOI layer 7) becomes small. This is because the polishing rates of the polycrystalline silicon 8 and the first silicon substrate 1 (single crystal silicon) are almost equal. Further, the polishing amount of 5 μm or less is sufficient, and the processing accuracy obtained by grinding is less deteriorated. In this polishing, the oxide film 6 on the side wall of the groove is also simultaneously polished after the first silicon substrate 1 is exposed. Therefore, if the polishing having the mechanical action is higher than the polishing having the high chemical action, the variation is further reduced. .

Further, as shown in FIG. 10, the silicon oxide film 6 formed on the side wall of the trench 3 filled with the polycrystalline silicon 8 is removed with, for example, a hydrofluoric acid solution. This amount of removal is equal to or greater than the depth of the processing strain generated in the first silicon substrate 1 by the above-described polishing having a high mechanical action, and is preferably equal to the thickness removed by the flattening polishing performed later, for example, from the surface. 0.5 μm.

Next, as shown in FIG. 11, polishing with high chemical action (planarization polishing) is performed to remove polishing strain (variation in substrate thickness) and to flatten the groove. The polishing allowance at this time is at least the depth removed by the etching in the previous step.

That is, when the polishing having a high mechanical action is performed in the above-described polishing, the step in the groove region is small and almost flat, but polishing strain (damage) remains on the polishing surface of the first silicon substrate 1. . Therefore, the residual strain must be removed by polishing with a high chemical action.
However, as described above, uniform polishing is impossible due to the presence of the sidewall oxide film 6 in the groove. Therefore, as shown in FIG. 10, only the sidewall oxide film 6 is removed from the substrate surface by etching to a desired depth with a hydrofluoric acid solution or the like. By performing this process before the flattening polishing, the polishing is performed on the first silicon substrate 1 and the polycrystalline silicon 8 without polishing the oxide film. Therefore, it is possible to eliminate the problem of variation in thickness due to difference in polishing amount due to polishing sag or sparse and dense patterns. It is most desirable to make the depth of the sidewall oxide film 6 removed by etching equal to the thickness of the first silicon substrate 1 removed by planarization polishing. In this case, the upper surface of the sidewall oxide film 8 can also function as a polishing stopper (particularly, a region where the groove pattern is dense). Further, by making the depth of the oxide film 6 to be removed equal to the thickness of the silicon substrate 1 to be removed by polishing, the surface of the groove portion including the oxide film 6 can be flattened.

As described above, in this embodiment, as shown in FIG. 9, the silicon oxide film 6 (insulating film) is formed on the side wall on the surface of the bonded substrate 5 as a silicon substrate, and the polycrystalline silicon 8 is provided inside. Forming a groove 3 filled with (first step), removing the silicon oxide film 6 on the side wall of the groove 3 from the surface of the bonded substrate 5 to a desired depth (second step), and then the surface of the bonded substrate 5 Then, the surface of the polycrystalline silicon 8 in the groove 3 was simultaneously polished to flatten the surface of the groove (third step). In this third step, the polishing is performed on the bonded substrate 5 and the polycrystalline silicon 8 without polishing the silicon oxide film 6, so that the thickness variation due to the polishing sag due to the presence of the silicon oxide film 6 is eliminated and the thickness variation of the substrate is eliminated. Can be kept small, and the groove region on the substrate surface can be made flat.

Particularly, since the depth of the silicon oxide film 6 removed in the second step is made equal to the thickness of the bonded substrate 5 removed by polishing in the third step, the surface of the groove portion including the silicon oxide film 6 is removed. Planarization can be achieved.

In the first step, the first silicon substrate 1 having the groove 3 and the second silicon substrate 4 having a small thickness variation are directly bonded to each other, and then the surface of the first silicon substrate 1 is removed. Remove a predetermined amount to expose the groove 3,
The polycrystalline silicon 8 is directly formed on the surface of the first silicon substrate 1.
And a step of grinding the polycrystalline silicon 8 by a predetermined amount to flatten the surface of the polycrystalline silicon 8 and further polishing the polycrystalline silicon 8 by a predetermined amount to expose the surface of the first silicon substrate 1. I decided. Therefore, in the flattening grinding and polishing of the surface of the polycrystalline silicon 8, since the thickness variation of the second silicon substrate 4 in the bonded substrate stack 5 is small, the thickness variation of the first silicon substrate 1, that is, the oxidation. SO isolated by the silicon film 6
It is possible to reduce the thickness variation of the I layer 7 (silicon region). Further, in polishing the polycrystalline silicon 8, the polishing rates of the polycrystalline silicon 8 and the first silicon substrate 1 (single crystal silicon) are almost equal, and the variation in the thickness of the substrate after polishing (more specifically, the SOI layer 7) The thickness variation can be reduced.

As the insulating film, a nitride film may be used instead of the oxide film. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.

12 to 19 show the cross-sectional structure of the main part of the dielectric isolation substrate of this embodiment in the manufacturing process order. This embodiment will be described in the order of manufacturing steps.

First, as shown in FIG. 12, a part of the mirror surface 9a of the first silicon substrate 9 having at least one surface mirror-polished is selectively etched by chemical etching or RIE to form a groove 10. After that, a silicon oxide film 11 is formed on the mirror surface 9a and the side wall (surface) of the groove 10 by thermal oxidation.

On the other hand, as shown in FIG. 13, a second silicon substrate 12 is prepared. The second silicon substrate 12 is a substrate having a small thickness variation in which at least one surface is mirror-polished (for example, parallelism is 1 μm or less). And the first
The mirror surface 9a of the silicon substrate 9 and the mirror surface 12a of the second silicon substrate 12 are joined to form a bonded substrate 13.
An oxide film may be formed on the second silicon substrate 12 before bonding.

The subsequent steps (FIGS. 14 to 19) are the same as those in FIGS. 6 to 11 of the first embodiment. That is, as shown in FIG. 14, the first silicon substrate 9 is ground from the front surface 9b side, and then polished, and then, as shown in FIG.
Form the layer 14. At this time, variations in the thickness of the SOI layer 14 (indicated by t3 and t4 in FIG. 14) occur. Further, as shown in FIG. 15, polycrystalline silicon 15 is deposited by the LPCVD method or the like, and the inside of the groove 10 is filled with the polycrystalline silicon 15. Further, as shown in FIG.
The polycrystalline silicon 15 is ground, and subsequently, as shown in FIG. 17, the first silicon substrate 9 is exposed on the entire surface of the substrate by polishing. Further, as shown in FIG. 18, a predetermined amount of the silicon oxide film 11 formed on the side wall of the groove 10 is removed with, for example, a hydrofluoric acid solution, and polishing with high chemical action (planarization polishing) is performed as shown in FIG. By doing so, polishing strain is removed and the groove is flattened. (Third Embodiment) Next, the third embodiment will be described focusing on the differences from the first embodiment.

20 to 30 show the cross-sectional structure of the main part of the dielectric isolation substrate of this embodiment in the manufacturing process order. This embodiment will be described in the order of manufacturing steps.

First, as shown in FIG. 20, the mirror surface 16 of the first silicon substrate 16 having at least one surface mirror-polished.
Grooves 17 are formed by selectively etching part of a by chemical etching or RIE. On the other hand, FIG.
As shown in FIG. 1, the second silicon substrate 18 is prepared. The second silicon substrate 18 is a substrate having a small thickness variation in which at least one surface is mirror-polished (for example, parallelism is 1 μm or less). The mirror surface 18 of the second silicon substrate 18
A silicon oxide film 19 is formed on a by thermal oxidation, and then the surface on which the silicon oxide film 19 is formed and the mirror surface 16a of the first silicon substrate 16 are bonded to each other to form a bonded substrate 20.

Further, as shown in FIG. 22, the silicon oxide film 1 is formed by exposing the groove 17 by grinding and then polishing.
The SOI layer 21 divided by the groove 17 is formed on the substrate 9. At this time, variations in thickness of the SOI layer 21 (see FIG.
2 indicates t5 and t6). After that, as shown in FIG. 23, the inner wall of the groove 17 and the first silicon substrate 1
A silicon oxide film 22 is formed on the surface of 6 by thermal oxidation. Then, the polycrystalline silicon 2 is formed on the silicon oxide film 22.
3 is deposited and the groove 17 is filled.

Next, as shown in FIG. 24, the silicon oxide film 22 formed on the surface of the first silicon substrate 16 functions as a stopper to leave the polycrystalline silicon 23 in the groove 17 on the substrate surface. The deposited polycrystalline silicon 23 is removed by polishing. Furthermore, as shown in FIG.
The silicon oxide film 23 on the surface of the first silicon substrate 16 functioning as a stopper is removed, and then polycrystalline silicon 24 is deposited again as shown in FIG.

The subsequent steps (FIGS. 27 to 30) are the same as those in FIGS. 8 to 11 of the first embodiment. That is, as shown in FIG. 27, the polycrystalline silicon 24 is ground with the other surface of the bonded substrate 20 as a reference to reduce the thickness variation of the bonded substrate 20. Then, as shown in FIG. 28, the ground polycrystalline silicon surface is polished to expose the first silicon substrate 16 on the entire surface of the substrate and expose the groove portion on the surface to form the thickness of the SOI layer 21 (first silicon substrate 16). Reduce the variation. Furthermore, as shown in FIG.
For example, a predetermined amount of the silicon oxide film 22 formed on the side wall of the groove 17 is removed with a hydrofluoric acid solution, and as shown in FIG. 30, polishing with a high chemical action (planarization polishing) is performed to remove polishing strains and groove portions. Is flattened. (Fourth Embodiment) Next, the fourth embodiment will be described focusing on the differences from the first embodiment.

31 to 36 show the cross-sectional structure of the main part of the dielectric isolation substrate of this embodiment in the manufacturing process order. This embodiment will be described in the order of manufacturing steps.

First, as shown in FIG. 31, a first silicon substrate 25 on which a semiconductor element is formed and a second silicon substrate 26 supporting the first silicon substrate 25 are prepared, and a silicon oxide film 27 is provided therebetween. Two silicon substrates 25, 26
Stick together. With respect to the bonded substrate (dielectric isolation substrate) 28 manufactured in this way, as shown in FIG. 32, a groove 29 reaching from the mirror surface 28a to the silicon oxide film 27.
Are selectively etched by chemical etching or RIE. After that, a silicon oxide film 30 is formed on the mirror surface 28a of the bonded substrate 28 and the inner wall of the groove 29 by a method such as thermal oxidation.

Subsequently, as shown in FIG. 33, polycrystalline silicon 31 is deposited on the silicon oxide film 30 and the groove 29 is filled with the polycrystalline silicon 31. Further, as shown in FIG. 34, the silicon oxide film 30 formed on the mirror surface 28a of the bonded substrate 28 by polishing functions as a stopper to remove the polycrystalline silicon 31 deposited on the substrate surface.

Next, as shown in FIG. 35, the silicon oxide film 30 on the surface of the bonded substrate stack 28 functioning as a stopper is removed by etching with a hydrofluoric acid solution, for example. In this step, the silicon oxide film 30 on the sidewall of the groove 29 is also removed from the surface of the substrate 28 to a desired depth. It is desirable to make this depth equal to the stock removal of the flattening polishing step of the next step.

Further, as shown in FIG. 36, the bonded substrate 28 and the polycrystalline silicon 31 in the groove 29 are simultaneously polished with a high chemical action to flatten the groove portion on the substrate surface. (Fifth Embodiment) Next, the fifth embodiment will be described focusing on the differences from the fourth embodiment.

37 to 42 show the cross-sectional structure of the main part of the silicon substrate in the manufacturing process order of this embodiment. This embodiment will be described in the order of manufacturing steps.

First, as shown in FIG. 37, a silicon substrate 32 is prepared, and as shown in FIG. 38, a groove 33 is formed by selectively etching the groove 33 from the mirror surface 32a by chemical etching or RIE. After that, a silicon oxide film 34 is formed on the mirror surface 32a of the silicon substrate 32 and the inner wall of the groove 33 by a method such as thermal oxidation.

Subsequently, as shown in FIG. 39, polycrystalline silicon 35 is deposited and trench 33 is filled with polycrystalline silicon 35. Furthermore, as shown in FIG.
The polycrystalline silicon film 35 deposited on the substrate surface is removed by causing the silicon oxide film 34 formed on the mirror surface 32a of No. 3 to function as a stopper.

Next, as shown in FIG. 41, the silicon oxide film 34 functioning as a stopper is removed by etching with a hydrofluoric acid solution, for example. In this step, the silicon oxide film 34 on the sidewall of the groove 33 is also removed from the surface of the substrate 32 to a desired depth. It is desirable to make this depth equal to the stock removal of the flattening polishing step of the next step.

Further, as shown in FIG. 42, the groove 33 is flattened by polishing having a high chemical action.

[0051]

According to the first aspect of the invention, the surface of the substrate is flat and the variation in thickness can be reduced.

According to the invention of claim 2, claim 1
In addition to the effect of the invention described in (1), the surface of the silicon region that is insulated and separated by the insulating film is flat and the thickness variation can be reduced.

According to the invention of claim 3, claim 1
In addition to the effect of the invention described in (1), the surface of the groove including the insulating film can be flattened.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor substrate according to a first embodiment.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the first embodiment.

FIG. 12 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 13 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 14 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 15 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 17 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the second embodiment.

FIG. 20 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 22 is a sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 23 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 24 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 26 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 27 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 28 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 29 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 30 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the third embodiment.

FIG. 31 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 32 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 33 is a sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 34 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 35 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 36 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fourth embodiment.

FIG. 37 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 38 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 39 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 40 is a sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 41 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 42 is a cross-sectional view showing the method of manufacturing the semiconductor substrate of the fifth embodiment.

FIG. 43 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 44 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 45 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 46 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 47 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 48 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

FIG. 49 is a cross-sectional view showing the conventional method of manufacturing a semiconductor substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st silicon substrate, 3 ... groove | channel, 4 ... 2nd silicon substrate, 5 ... bonded substrate, 6 ... silicon oxide film as an insulating film, 8 ... polycrystalline silicon, 9 ... 1st silicon substrate,
10 ... Groove, 11 ... Silicon oxide film as insulating film, 12
... second silicon substrate, 13 ... bonded substrate, 15 ... polycrystalline silicon, 16 ... first silicon substrate, 17 ... groove, 1
8 ... 2nd silicon substrate, 20 ... Laminated substrate, 22 ...
Silicon oxide film as insulating film, 24 ... Polycrystalline silicon, 28 ... Bonded substrate, 29 ... Groove, 30 ... Silicon oxide film as insulating film, 31 ... Polycrystalline silicon, 32 ...
Silicon substrate, 33 ... Groove, 34 ... Silicon oxide film as insulating film, 35 ... Polycrystalline silicon

Claims (3)

[Claims] 1. A first step of forming a groove in which an insulating film is formed on a side wall of a surface of a silicon substrate and which is filled with polycrystalline silicon, and an insulating film on a side wall of the groove is formed from a surface of the silicon substrate. A semiconductor comprising: a second step of removing to a desired depth; and a third step of simultaneously polishing the surface of the silicon substrate and the surface of the polycrystalline silicon in the groove to flatten the surface of the groove. Substrate manufacturing method. 2. In the first step, a first silicon substrate having a groove and a second silicon substrate having a small thickness variation are directly bonded to each other, and then a predetermined amount of the surface of the first silicon substrate is removed. The groove is exposed, and polycrystalline silicon is directly deposited on the surface of the first silicon substrate.
2. The method according to claim 1, further comprising grinding a predetermined amount of the polycrystalline silicon to flatten the surface of the polycrystalline silicon, and further polishing the polycrystalline silicon by a predetermined amount to expose the surface of the first silicon substrate. Manufacturing method of semiconductor substrate. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the depth of the insulating film removed in the second step is equal to the thickness of the silicon substrate removed by the polishing in the third step.