JPH1174343A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable flat formation without unevenness caused on a surface of a trench-type element separation region, by performing thermal treatment on a first insulation film formed in a trench to make it highly dense, and by performing thermal treatment on a second insulation film embedded in a recess corresponding to the trench to make it highly dense. SOLUTION: In forming an element separation region 10, after a trench is filled with a silicon oxide film 6, thermal treatment is performed, thereby making the silicon oxide film 6 highly dense. In addition, after another silicon oxide film 8 is formed on the silicon oxide film 6 and a butting part 7 is completely filled, thermal treatment is performed on the silicon oxide film 8 to make it highly dense. Therefore, a laminated state in the vicinity of the butting part 7 where filling in the trench 4 is insufficient can be made to be highly dense. Further, filling of the two silicon oxide film layers 6, 8 in the vicinity of the butting part 7 can be more rigid. Thus, a semiconductor device with electric characteristics improved can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for fixing an element formation region on a semiconductor substrate in a semiconductor device.
In particular, an element isolation structure by a trench element isolation method, for example, STI (Shallow Trench Isola)
The present invention relates to a semiconductor device having an element isolation structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art The so-called LOCOS method is generally widely known as a technique for electrically isolating elements formed on a semiconductor substrate to fix an element formation region. However, the LOCOS method has a problem in that a parasitic device is formed by an inversion layer generated below the field oxide film. To prevent this, the field oxide film needs to be thickened, but at the same time, the "bird's beak" formed at the element isolation end hinders miniaturization of the element formation region, and as a result, LSI
Has become a major obstacle to the high integration of semiconductor devices.

Several element isolation techniques have been proposed to improve the disadvantages of the LOCOS method. Part 1
One known example is an STI element isolation structure using a trench element isolation method. This element isolation structure fixes an element formation region by embedding an insulating film such as an oxide film in a trench formed in a semiconductor substrate made of silicon, for example. In such an STI element isolation structure, the width of the element isolation region for fixing the element can be made extremely small, and the depth direction can be sufficiently secured, so that the element isolation area can be significantly reduced. At present, it is possible to form an element isolation region composed of a trench having a width of about 1 μm and a depth of about several μm.

The formation of an element isolation region by such a trench type element isolation method is generally performed as follows.

First, a thermal oxide film is formed on a p-type semiconductor substrate (for example, a silicon substrate), and a low-pressure C
A silicon nitride film is formed by a VD method. Next, by photolithography and subsequent dry etching,
The silicon nitride film and the thermal oxide film corresponding to the element isolation region are selectively removed. Next, dry etching is performed using the remaining silicon nitride film as a mask, a region corresponding to the element isolation region is removed to a predetermined depth on the semiconductor substrate, and a trench is formed. Next, after a thermal oxide film is formed on the bottom and side walls of the trench by thermal oxidation, a thick silicon oxide film is deposited on the entire surface including the inside of the trench by the CVD method. After that, the chemical mechanical polishing method (hereinafter referred to as “CMP method”)
Abbreviated. ), The silicon oxide film is polished and removed until the silicon nitride film is exposed, the silicon nitride film is removed by wet etching with hot phosphoric acid, and the thermal oxide film is removed by wet etching with a fluorine solution or dry etching. In this manner, an element isolation region slightly protruding from the surface of the semiconductor substrate is formed while leaving the silicon oxide film in the trench.

In the above-described conventional process, since the silicon oxide film buried in the trench is formed along the side wall of the trench, a "joint portion (recess)" of the silicon oxide film is formed at the center of the trench. Will be done. That is, in this portion, a slight gap is formed because the surfaces of the silicon oxide films stacked on the sidewalls on both sides of the trench are in close contact with each other. by this,
The silicon oxide film in the vicinity of the joint is in an incompletely stacked state, and the density at this portion is lower than the density of other normally stacked silicon oxide films. Therefore, when the silicon oxide film is removed by etching, the etching rate is increased only in the vicinity of the joint. Furthermore, during wet etching when removing the silicon nitride film or etching or cleaning in a later step, etching proceeds rapidly in a portion corresponding to the joint portion due to the difference in the etching rate, A recess is formed. This causes a problem that the field inversion voltage decreases.

As described above, the problem that the joint (recess) is formed in the filled insulating film at the center position in the width direction of the trench (the direction parallel to the semiconductor substrate) is that the trench is formed on the semiconductor substrate. In a semiconductor device using a process of stacking and embedding an insulating film therein,
Always happens. Several prior arts using such a process have been proposed so far. For example, Japanese Patent Application Laid-Open Nos. Hei 3-203349, Hei 3-153030, Hei 6-68332, and Heisei 80-161
632, JP-A-1-134947 and the like.

For example, in Japanese Unexamined Patent Publication No. Hei 3-203349, after a trench formed on a semiconductor substrate is filled with a silicon oxide film, a BPCG film or the like is formed on the entire surface including a concave portion formed on the surface of the silicon oxide film. Laminate the glass layer,
A method of flattening the surface of a glass layer by performing a reflow process is disclosed.

However, even when the surface of the glass layer is flattened by this method, the region near the concave portion formed on the surface of the silicon oxide film is incompletely laminated, as in the prior art known hitherto. It is still a state. Therefore, when a glass layer, a silicon nitride film, or the like is removed by etching in a subsequent step, the etching proceeds in a region near the concave portion formed on the surface of the silicon oxide film at a higher speed than the peripheral region. As described above, a concave portion is formed, which causes a problem that the field inversion voltage is reduced.

Further, when the silicon nitride film is removed by wet etching using hot phosphoric acid or the like as in the above-described prior art, since this wet etching is isotropic etching, it is parallel to the surface of the semiconductor substrate. Etching also proceeds in the direction. For this reason, the surface of the silicon oxide film fixing the element formation region slightly projecting from the semiconductor substrate and the side surface of the element isolation end are simultaneously removed,
At the element isolation end, a portion (deleted portion) cut out in the width direction of the trench is formed. As a result, there is a problem that the leakage current of the parasitic device increases due to the presence of the defective portion.

According to the technique disclosed in Japanese Patent Application Laid-Open No. 6-69332, when an insulating film in which such an STI element isolation structure is embedded is etched to a predetermined amount, an oxide film formed on a semiconductor substrate is etched. It functions as a stopper at the time of etching by the reactive ion etching (RIE) method. Then, the entire surface is sacrificed after the etching, and all oxide films including the oxide film in the trench are removed to a predetermined amount, thereby forming the STI element isolation structure.

[0012]

However, in forming such an STI element isolation structure, if the silicon oxide film filling the trench is removed by the CMP method, the following problems have occurred.

The silicon oxide film is polished by the CMP method until the silicon nitride film is exposed. However, there is a large variation in the polishing rate due to the pattern dependency, and the polishing rate selection ratio of the silicon oxide film to the silicon nitride film as a stopper is reduced. Since it could not be made larger, the function as a stopper could not be sufficiently achieved. Therefore, it is very difficult to stop the chemical mechanical polishing when the silicon nitride film is exposed, and the silicon oxide film partially remains in a specific pattern region, or the silicon nitride film is polished more than necessary in another pattern region. Therefore, it is not easy to flatten the surface of the element isolation region while leaving the intended silicon oxide film in the trench. As described above, due to the fact that the position of the surface of the element isolation region is not constant, there is a problem that formation failure occurs when a pattern is formed on an upper layer in this step, and the electrical characteristics of the element deteriorate.

When the STI element isolation structure is formed by the method disclosed in Japanese Patent Application Laid-Open No. 6-69332, the laminated film to be removed by etching is not flattened first,
Also, since the surface position is not determined, if the surface of the insulating film protrudes from the semiconductor substrate after the etching of the easily oxidized film, the amount of protrusion cannot be controlled, and the position of the surface cannot be controlled by etching after sacrificial oxidation. There were limits to controlling

Further, when the surface of the element isolation region and the surface of the semiconductor substrate are made flush with each other by the etching after the sacrificial oxidation, a depression is easily formed at the end of the element isolation region, thereby causing the leakage of the parasitic transistor. There was also a problem that the current increased.

The present invention has been made in order to solve such a problem, and a main object of the present invention is to make it possible to form a trench type element isolation region flat without causing irregularities on its surface. It is another object of the present invention to provide a semiconductor device capable of contributing to improvement in electrical characteristics and a method for manufacturing the same.

Another object of the present invention is to eliminate excessive or insufficient polishing by reliably stopping removal by polishing when removing a stacked film filling the trench in the formation of a trench type element isolation structure. In addition, it is an object of the present invention to provide a semiconductor device capable of accurately determining the position of the surface of an element isolation region by removing a desired amount of the surface of the stacked film, and a method of manufacturing the same.

[0018]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a heat-resistant insulating film on a semiconductor substrate;
A second step of patterning the heat-resistant insulating film; and a third step of selectively removing a surface of the semiconductor substrate according to the shape of the heat-resistant insulating film to form a trench in the semiconductor substrate. A fourth step of forming a first insulating film on the entire surface of the semiconductor substrate including the trench, and a fifth step of performing heat treatment on the semiconductor substrate to increase the density of the first insulating film. A step of forming a second insulating film on the first insulating film so as to fill a recess formed in a region corresponding to the trench on the first insulating film; and A seventh step of performing heat treatment on the substrate to increase the density of the second insulating film, and an eighth step of removing the first insulating film and the second insulating film until the heat-resistant insulating film is exposed. Removing the heat-resistant insulating film exposed on the surface And a ninth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, each of the first insulating film and the second insulating film is a silicon oxide film.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the first insulating film and the second insulating film are removed by a chemical mechanical polishing method in the eighth step.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the heat-resistant insulating film is used as a stopper in a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, before the first step, the method further includes a tenth step of forming a pad insulating film on the semiconductor substrate, In the step, the heat-resistant insulating film is formed between the semiconductor substrate and the semiconductor substrate via the pad insulating film. In the third step, the pad insulating film is formed together with the semiconductor substrate according to the shape of the heat-resistant insulating film. Selectively remove.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the heat-resistant insulating film is removed by anisotropic etching in the ninth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, between the third step and the fourth step,
A third surface area extends from the bottom to the side wall of the trench.
And an eleventh step of forming the insulating film.

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a heat-resistant insulating film on a semiconductor substrate, a second step of patterning the heat-resistant insulating film, A third step of selectively removing a surface of the semiconductor substrate according to a shape to form a trench in the semiconductor substrate, and forming a first step on the entire surface of the semiconductor substrate including the trench.
A fourth step of forming the insulating film, a fifth step of removing the first insulating film until the heat-resistant insulating film is exposed, and a sixth step of removing the heat-resistant insulating film. A seventh step of forming a second insulating film on the entire surface of the semiconductor substrate so as to fill the uneven portion formed in the region corresponding to the trench on the first insulating film; The second insulating film is formed on the first insulating film so as to make the surface of the film flat.
An eighth step of removing and leaving only on the insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, each of the first insulating film and the second insulating film is a silicon oxide film.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the first insulating film is removed by a chemical mechanical polishing method in the fifth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the heat-resistant insulating film is used as a stopper in a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the method further comprises, before the first step, a ninth step of forming a pad insulating film on the semiconductor substrate, In the step, the heat-resistant insulating film is formed between the semiconductor substrate and the semiconductor substrate via the pad insulating film. In the third step, the pad insulating film is formed together with the semiconductor substrate according to the shape of the heat-resistant insulating film. Selectively remove.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the heat-resistant insulating film is removed by anisotropic etching in the sixth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, between the third step and the fourth step,
A third surface area extends from the bottom to the side wall of the trench.
And a tenth step of forming the insulating film.

According to the method of manufacturing a semiconductor device of the present invention, a first step of forming a heat-resistant insulating film on a semiconductor substrate, a second step of patterning the heat-resistant insulating film, A third step of selectively removing a surface of the semiconductor substrate according to a shape to form a first trench in the semiconductor substrate; and forming the heat-resistant insulating film so as to cover an inner wall surface of the first trench. Forming a first insulating film thereon;
Forming a second trench narrower than the first trench
Forming a oxidizable film having a higher polishing rate selectivity than the first insulating film on the first insulating film so as to fill the second trench; Removing the oxidizing film until the first insulating film is exposed;
A sixth step of leaving the easily oxidizable film only in the trench, and thermally oxidizing the easily oxidizable film left in the second trench, and forming a first film on an upper surface region of the easily oxidizable film. A seventh step of forming a thermal oxide film, an eighth step of removing the first insulating film and a part of the first thermal oxide film exposed on the surface, A ninth step of thermally oxidizing the remaining oxidizable film again to form a second thermal oxide film on an upper surface region of the oxidizable film, and forming the heat-resistant insulating film exposed on the surface. And a tenth step of removing.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the oxidizable film is a polysilicon film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the first insulating film is a silicon oxide film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the method further includes, before the first step, an eleventh step of forming a pad insulating film on the semiconductor substrate. After the step of, further comprising a twelfth step of removing the pad insulating film, the first step of forming the heat-resistant insulating film between the semiconductor substrate via the pad insulating film, In the second step, the pad insulating film is patterned together with the heat-resistant insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the oxidizable film is removed by a chemical mechanical polishing method in the sixth step.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the first insulating film is used as a stopper in a chemical mechanical polishing method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, a polishing rate selection ratio of the oxidizable film to the first insulating film is set to 20 times or more.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, the thickness of the first thermal oxide film is set to be larger than the thickness of the first insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, between the third step and the fourth step,
The method further includes a thirteenth step of forming a second insulating film in a surface region from a bottom surface to a side wall of the first trench.

A semiconductor device according to the present invention includes a semiconductor substrate having a trench formed therein, wherein the trench has a first insulating film densified by heat treatment and a second insulating film also densified by heat treatment. The element isolation insulating film is filled with the film and has an integral structure as a whole.

In one embodiment of the semiconductor device of the present invention, each of the first insulating film and the second insulating film is a silicon oxide film.

In one embodiment of the semiconductor device of the present invention, a pair of sources formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate are provided. And a gate electrode formed on a region between the pair of source / drain regions via an insulating film.

A semiconductor device according to the present invention includes a semiconductor substrate having a trench formed therein, the trench including a first insulating film constituting a main part of an element isolation structure formed on the semiconductor substrate by the trench. The first insulating film is filled with a second insulating film formed so as to bury the uneven portion formed on the first insulating film during the process and to flatten the upper surface of the first insulating film.

In one embodiment of the semiconductor device of the present invention, each of the first insulating film and the second insulating film is a silicon oxide film.

In one embodiment of the semiconductor device of the present invention, a pair of sources formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate are provided. And a gate electrode formed on a region between the pair of source / drain regions via an insulating film.

A semiconductor device according to the present invention is formed so as to cover a semiconductor substrate having a trench formed therein and a bottom surface and a side wall of the trench, and an upper surface of an end portion of a portion formed on a side wall of the trench is formed of the semiconductor substrate. A first insulating film protruding from the surface of the substrate; and an oxidizable material filled in the trench so as to be surrounded by the first insulating film and having a higher polishing rate selectivity than the first insulating film. A film and a thermal oxide film formed on an upper surface region of the easily oxidizable film.

In one embodiment of the semiconductor device of the present invention, the oxidizable film is a polysilicon film.

In one embodiment of the semiconductor device according to the present invention, the first insulating film is a silicon oxide film.

In one embodiment of the semiconductor device of the present invention, a polishing rate selection ratio of the oxidizable film to the first insulating film is set to be 20 times or more.

In one embodiment of the semiconductor device of the present invention, a pair of sources formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate are provided. And a gate electrode formed on a region between the pair of source / drain regions via an insulating film.

[0052]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an nMOS transistor as a first embodiment of a semiconductor device according to the present invention in a schematic sectional view.

In FIG. 1, 1 is a p-type semiconductor substrate (a p-type silicon substrate in this embodiment), 9 is an element isolation oxide film,
13 is a gate oxide film, 14 is a gate electrode, 16 is a diffusion region of a low concentration n-type impurity, 18 is a sidewall insulating film (a silicon oxide film in the present embodiment), and 19 is a high concentration n-type functioning as a source / drain region. An impurity diffusion region, 20 indicates an interlayer insulating film (BPSG film in this embodiment), and 23 indicates a metal wiring (aluminum wiring in this embodiment).

Hereinafter, the semiconductor device of the first embodiment (nM
A method for manufacturing the OS transistor will be described with reference to FIGS.

First, as shown in FIG. 4A, the surface of a p-type semiconductor substrate (p-type silicon substrate) 1 is thermally oxidized to form a thermal oxide film 2 (bat insulating film) having a thickness of about 30 nm. ,
Further, on this thermal oxide film 2, a thickness of 20 mm is formed by a low pressure CVD method.
A silicon nitride film 3 (heat-resistant insulating film) of about 0 nm is formed.

Next, as shown in FIG. 4B, by photolithography and subsequent dry etching, p
The silicon nitride film 3 and the thermal oxide film 2 are removed so as to expose a region corresponding to the element isolation region on the silicon substrate 1.

Next, as shown in FIG. 4C, the p-type silicon substrate 1 is removed by anisotropic etching using the silicon nitride film 3 as a mask to form a trench 4 (groove).
The trench 4 is formed so as to have a depth of about 400 nm and a taper angle of the side wall of about 80 °. Next, a thermal oxide film 5 having a thickness of about 20 nm is formed from the bottom surface to the side wall of the trench 4 by thermal oxidation. This thermal oxide film 5 is formed to remove a damaged layer formed on the inner wall surface of the trench 4 by anisotropic etching.

Next, as shown in FIG. 4D, a silicon oxide film 6 having a thickness of about 400 nm is formed on the entire surface of the p-type silicon substrate 1 including the trench 4 by the CVD method.
Since this silicon oxide film 6 is formed along the bottom and side walls in trench 4, a V-shaped joint portion 7 is formed on silicon oxide film 6 in a region corresponding to the central position in the width direction of trench 4. It is formed. Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of 900 ° C. for 80 minutes to increase the density of the silicon oxide film 6.

Next, as shown in FIG. 5A, a 400 nm-thickness is formed by the CVD method so as to bury the joint 7.
An about m silicon oxide film 8 is formed. Thereafter, similarly, heat treatment is performed at 900 ° C. for 90 minutes in a nitrogen atmosphere to increase the density of the silicon oxide film 8.

As described above, first, a silicon oxide film 6 is formed and heat treatment is performed to stabilize the silicon oxide film 6 in a high-density state. By forming the film 8 and performing a heat treatment, the filling state of the two silicon oxide films 6 and 8 in the region near the joint portion 7 can be made uniform. As a result, the thermal oxide film 5, the silicon oxide film 6, and the silicon oxide film 8 substantially form an oxide film having an integral structure.

Next, as shown in FIG. 5B, the oxide film having the integrated structure is polished and removed by a CMP method until the silicon nitride film 3 is exposed, and an element isolation oxide film 9 is formed. At this time, the silicon nitride film 3 functions as a stopper for the CMP method. Further, the surface of the element isolation oxide film 9 can be projected from the surface of the p-type silicon substrate 1 by the thickness of the remaining silicon nitride film 3 and thermal oxide film 2.

Next, as shown in FIG. 5C, the silicon nitride film 3 is removed by anisotropic dry etching, and the thermal oxide film 2 is further removed by dry etching or wet etching with hydrogen fluoride. As a result, an element isolation region 10 is formed while leaving the element isolation oxide film 9 only in the trench 4. The element formation region is fixed by the element isolation region 10.

Next, as shown in FIG. 5D, a thermal oxide film 11 is formed on the element formation region (the region other than the element isolation region 10) by a thermal oxidation treatment. A polycrystalline silicon film (polysilicon film) 12 is formed covering the film 9 while adding impurities such as phosphorus (P) by a low-pressure CVD method.

Next, as shown in FIG. 6A, the polysilicon film 12 and the thermal oxide film 11 are patterned by photolithography and subsequent dry etching to form a gate oxide film 13 and a gate electrode 14. The gate part 15 is formed.

Next, as shown in FIG. 6B, arsenic (As), which is an n-type impurity, is ion-implanted at a low concentration using the element isolation region 10 and the gate portion 15 as a mask. A diffusion region 16 is formed.

Next, as shown in FIG.
After a silicon oxide film is formed on the entire surface by the method D, a sidewall insulating film (silicon oxide film) 18 is formed on the side surface of the gate unit 15 by photolithography and subsequent anisotropic dry etching.

Next, as shown in FIG. 6D, arsenic (As) or phosphorus (P) which is an n-type impurity is used by using the element isolation region 10, the gate portion 15, and the side wall insulating film 18 as a mask.
Is ion-implanted at a high concentration to form a high-concentration impurity diffusion region 19.
To form Thereafter, heat treatment is performed to activate the impurities in the low concentration impurity diffusion region 16 and the high concentration impurity diffusion region 19.

Next, as shown in FIG. 7A, a BPSG film 20, which is an interlayer insulating film, is deposited thick by CVD over the entire surface, and then a reflow process is performed. Then, contact holes 21 and 22 are formed so as to reach the high-concentration impurity diffusion region 19 (source / drain region) and the gate electrode 14, respectively.

Finally, as shown in FIG. 7B, an aluminum wiring 23 is deposited by a sputtering method to fill the contact holes 21 and 22, and is patterned on the BPSG film 20 as shown in FIG. The nMOS transistor is completed.

According to the semiconductor device (nMOS transistor) of the first embodiment configured as described above, when forming the element isolation region 10, the trench 4 is filled with the silicon oxide film 6 and then heat treatment is performed. Thereby, the density of the silicon oxide film 6 can be increased, and the stacked state near the joint portion 7 where the filling in the trench 4 is insufficient can be increased. Further, after a further silicon oxide film 8 is formed on the silicon oxide film 6 to completely embed the joint portion 7, the silicon oxide film 8 is also subjected to a heat treatment to increase the density. The filling of the two silicon oxide films 6 and 8 in the vicinity of the eye portion 7 can be made stronger.

As a result, as compared with the case where the inside of the trench 4 is filled with only one silicon oxide film without performing the heat treatment as in the prior art, the integrated erosion by the subsequent etching process is strengthened. An element isolation oxide film 9 having a structure can be formed.

Since the element isolation oxide film 9 can have substantially the same etching rate in the entire region, an etching step for removing the silicon nitride film 3 or a subsequent etching step for patterning when forming the gate portion 15 are performed. In this case, there is no inconvenience that the etching at the center or the end of the element isolation region 10 proceeds faster than the etching at the peripheral region. Therefore, it is possible to prevent the formation of a concave portion due to such inconvenience as seen in the related art.

Further, at the end of the element isolation region,
By performing the removal of the silicon nitride film 3 by anisotropic etching, it is possible to prevent the formation of a defective portion due to the removal of the side wall 25 by etching. As a result, it is possible to suppress a decrease in the field inversion voltage or an increase in the leak current of the parasitic device due to the unevenness of the surface of the element isolation region 10.

FIG. 2 is a schematic sectional view showing the structure of an nMOS transistor as a second embodiment of the semiconductor device according to the present invention.

In FIG. 2, the same reference numerals (13, 14, 16, 18, 19, 20) as those used in FIG.
And 23) represent the same components. Further, in FIG. 2, 31 is a p-type semiconductor substrate (p-type silicon substrate in the present embodiment), and 36 and 38 are silicon oxide films, respectively. Here, the first silicon oxide film 36 forms a main part of the element isolation oxide film, and the second silicon oxide film 38
Are formed to replenish the defective portions and the like formed on the first silicon oxide film 36.

Hereinafter, the semiconductor device of the second embodiment (nM
A method for manufacturing the OS transistor will be described with reference to FIGS.

First, as shown in FIG. 8A, the surface of a p-type semiconductor substrate (p-type silicon substrate) 31 is thermally oxidized to form a thermal oxide film 32 (bat insulating film) having a thickness of about 30 nm. Further, a silicon nitride film 33 (heat resistant insulating film) having a thickness of about 200 nm is formed on the thermal oxide film 32 by a low pressure CVD method.

Next, as shown in FIG. 8B, by photolithography and subsequent dry etching, p
Silicon nitride film 33 and thermal oxide film 32 so as to expose a region corresponding to the element isolation region on type silicon substrate 31.
Is removed.

Next, as shown in FIG. 8C, the p-type silicon substrate 31 is removed by anisotropic etching using the silicon nitride film 33 as a mask, and a trench 34 is formed.
The trench 34 is formed to have a depth of about 400 nm and a side wall taper angle of about 80 °. Further, a thermal oxide film 35 having a thickness of about 20 nm is formed from the bottom surface to the side wall of the trench 34 by thermal oxidation. This thermal oxide film 35 corresponds to the thermal oxide film 5 (FIG. 4) in the first embodiment.
(See (c))) to remove the damaged layer formed on the inner wall surface of the trench by anisotropic etching.

Next, as shown in FIG. 8D, a silicon oxide film 36 having a thickness of about 800 nm is formed on the entire surface of the p-type silicon substrate 31 including the trench 34 by the CVD method. Since the silicon oxide film 36 is formed along the bottom surface and the side wall in the trench 34, a V-shaped joint portion 37 is formed on the silicon oxide film 36 in a region corresponding to the center of the trench 34 in the width direction. It is formed. In the vicinity of the joint portion 37 of the silicon oxide film 36, the surfaces of the silicon oxide films 36 formed on both side walls of the trench 34 do not completely and integrally adhere to each other. turn into.

Next, as shown in FIG. 9A, the silicon oxide film 36 is polished and removed by CMP until the silicon nitride film 33 is exposed. At this time, the silicon nitride film 3
Reference numeral 3 functions as a stopper for the CMP method.

Next, as shown in FIG. 9B, wet etching with hot phosphoric acid is performed to
Is removed. At this time, since the region where the joint portion 37 of the silicon oxide film 36 is formed is incompletely filled as described above, the etching progresses faster than the peripheral portion. Therefore, at the time of this wet etching, the silicon oxide film 36 near the joint portion 37 is removed at the same time as the silicon nitride film 33, so that the concave portion 41 is formed. Also, since this wet etching is etching in the same direction, the p-type silicon substrate 3
Etching also proceeds in a direction parallel to the surface of the element 1, and a defect 39 is also formed at the end of the element isolation region 40.

Next, as shown in FIG. 9C, the entire surface of the p-type silicon substrate 31 including the element isolation region 40 is
A silicon oxide film 38 of about 00 nm is formed. As a result, the concave portion 41 and the defective portion 39 formed on the element isolation region 40 are filled with the silicon oxide film 38.

Next, as shown in FIG. 9D, the silicon oxide film 38 and the thermal oxide film 32 are removed by etching until the p-type silicon substrate 31 is exposed, thereby forming an element isolation region 40 as shown. I do. This element isolation region 40 fixes the element formation region.

Thereafter, through the same manufacturing steps (FIGS. 5D to 7A) as in the first embodiment described above, the nMOS transistor of this embodiment (see FIG. 2) is completed.

According to the semiconductor device (nMOS transistor) of the second embodiment thus configured, the silicon nitride film 33 is formed on the silicon oxide film 36 by wet etching with hot phosphoric acid when the silicon nitride film 33 is removed. Recess 4
1 and a defective portion 39, and a silicon oxide film 38 thereon.
Can be embedded.

As a result, it is possible to solve the problems such as a decrease in the field inversion voltage and an increase in the leak current of the parasitic device caused by the presence of the concave portion 41 and the defective portion 39.

FIG. 3 is a schematic sectional view showing the structure of an nMOS transistor as a third embodiment of the semiconductor device according to the present invention.

In FIG. 3, 51 is a p-type semiconductor substrate (p-type silicon substrate in this embodiment), 57 is an insulating film (thermal oxide film in this embodiment), 58 is an insulating film (silicon oxide film in this embodiment) ), 60 is an easily oxidized film (polysilicon film in this embodiment), 62 is a thermal oxide film, 64 is a gate oxide film, 65 is a polysilicon film functioning as a gate electrode,
67 and 68 are diffusion regions of an n-type impurity functioning as a source region and a drain region, respectively, 69 is an interlayer insulating film (BPSG film in this embodiment), 70, 71 and 72 are contact holes, and 73 is a metal wiring (this embodiment). In the embodiment, aluminum wiring is shown.

The semiconductor device of the third embodiment (nM
OS (transistor) manufacturing method with reference to FIGS.
This will be described with reference to FIGS. 12D and 12E.

First, as shown in FIG. 10A, the surface of a p-type semiconductor substrate (p-type silicon substrate) 51 is thermally oxidized to form a thermal oxide film 52 (pad insulating film) having a thickness of about 50 nm. Further, a silicon nitride film 53 (heat resistant insulating film) is formed on the thermal oxide film 52 by a low pressure CVD method.

Next, as shown in FIG. 10B, a photoresist 54 having an opening 55 is formed on the silicon nitride film 63 by using ordinary photolithography. At this time, the width of the opening 55 is suitably about 300 nm.

Next, as shown in FIG. 10C, dry etching is performed using the photoresist 54 as a mask.
The surface of the silicon nitride film 53, the thermal oxide film 52, and the surface of the p-type silicon substrate 51 are selectively removed from the upper layer to the lower layer to form a trench 56 having a depth of about 400 nm.

Next, as shown in FIG. 10D, after removing the photoresist 54, the surface region from the bottom surface to the side wall of the trench 56 is thermally oxidized to form a thermal oxide film 57 having a thickness of about 50 nm. Form. This thermal oxide film 57 is formed by etching similarly to the thermal oxide film 5 (see FIG. 4C) in the first embodiment and the thermal oxide film 35 (see FIG. 8C) in the second embodiment. This is for removing a damaged layer formed on the inner wall surface of the trench.

Next, as shown in FIG. 10E, a silicon oxide film (insulating film) 58 having a thickness of about 100 nm is formed on the bottom and side walls of the trench 56 and on the silicon nitride film 53 by low-pressure CVD. I do. Due to the formation of silicon oxide film 58, trench 5 has a thickness twice as large as its thickness.
The width of 6 is reduced, and a second trench 59 is formed.

Next, as shown in FIG. 11A, a polysilicon film (oxidizable film) 60 is formed over the entire surface by a low-pressure CVD method, and the trench 59 is completely filled and the polysilicon film 60 is formed on the silicon oxide film 58. The layers are stacked at a thickness of about 150 nm.

Next, as shown in FIG.
The polysilicon film 60 is polished and removed until the silicon oxide film 58 is exposed. As a result, the polysilicon film 60 is left only in the trench 59.

At this time, the polysilicon film 60 is easily polished by the CMP method, and when the silicon oxide film 58 is exposed, the polishing rate selection ratio of the silicon oxide film 58 to the polysilicon film 60 is set to be small. Stops virtually. Therefore, by using the silicon oxide film 58 having a low polishing rate as a stopper in the CMP method,
Even when various patterns are mixed, the polishing stop position can be accurately determined.

According to the experimental results of the present inventors, if the polishing rate selection ratio of the polysilicon film 60 to the silicon oxide film 58 is less than 20 times, it is difficult to clarify the polishing end point. It is desirable to set the polishing rate selection ratio to 20 times or more.

Next, as shown in FIG. 11C, the exposed surface area of the polysilicon film 60 in the trench 59 is subjected to a thermal oxidation treatment to thereby form a thermal oxide film 61 having a thickness larger than that of the silicon oxide film 58. To form The appropriate thickness of the thermal oxide film 61 is specifically about 200 nm. The thermal oxide film 61 and the silicon oxide film 58 constitute a substantially homogeneous film having an equivalent etching rate in the surface region.

Next, as shown in FIG. 11D, the thermal oxide film 61 and the silicon oxide film 58 exposed on the surface are removed by wet etching using fluorine. As described above, since the silicon oxide film 58 and the thermal oxide film 61 are uniform insulating films, the silicon oxide film 58 is removed until the silicon nitride film 53 is exposed. The oxide film 61 is also removed with a uniform thickness, so that the surface position can be determined with high accuracy.

Since the thermal oxide film 61 is formed thicker than the silicon oxide film 58 as described above, the polysilicon film 60 is covered with the thermal oxide film 61 until this wet etching is completed. In addition, the disadvantage that the polysilicon film 60 is scraped can be avoided.

Next, as shown in FIG. 11E, a thermal oxidation process is again performed on the surface of the polysilicon
A thermal oxide film 62 of about 00 nm is formed.

Next, as shown in FIG. 12A, the entire silicon nitride film 53 exposed on the surface is removed by wet etching using hot phosphoric acid, followed by thermal oxidation using fluorine. By removing the film 52, an element isolation region 63 having a trench element isolation structure as illustrated is formed.

Next, as shown in FIG. 12B, after the p-type silicon substrate 51 is thermally oxidized to form a gate oxide film 64, an impurity such as phosphorus (P) is added to the entire surface by low-pressure CVD. Then, a polysilicon film 65 is formed.

Next, as shown in FIG. 12C, by photolithography and subsequent dry etching,
The polysilicon film 65 and the gate oxide film 64 are removed by etching while leaving the gate portion 66.

Next, as shown in FIG. 12D, phosphorus (P) or arsenic (As), which is an n-type impurity, is accelerated at an energy of about 60 to 100 keV using the element isolation region 63 and the gate 66 as a mask. , Dose amount 5 × 10 ^{14 to} 5 ×
Ions are implanted into the p-type silicon substrate 51 at about 10 ¹⁴ / cm ² , and then diffused by heat treatment at about 900 ° C. to form the source region 67 and the drain region 68 of the nMOS transistor. .

Finally, as shown in FIG. 12E, a BPSG film (interlayer insulating film) 69 is thickly deposited over the entire surface by a CVD method, and then a reflow process is performed. Then, contact holes 70, 71, and 72 are formed to reach the polysilicon film 65 functioning as a gate electrode and the source and drain regions 68, respectively. After this,
Aluminum wiring 73 is deposited by a sputtering method to fill the contact holes 70, 71 and 72, and BPSG
By performing patterning on the film 69, the nMO
The S transistor is completed.

According to the semiconductor device (nMOS transistor) of the third embodiment configured as described above, the polishing rate selection ratio is higher on the silicon oxide film 58 filling the trench 56 than on the silicon oxide film 58. By forming the polysilicon film 60 having a large thickness and further removing the polysilicon film 60 by the CMP method, the polysilicon film 60 can be easily removed without causing polishing failure. Further, when the polysilicon film 60 is completely removed, the silicon oxide film 58 having a smaller polishing rate selection ratio than the polysilicon film 60 is exposed, so that the polishing can be reliably stopped at this point. Therefore, defective polishing can be minimized.

The polysilicon film 6 exposed after polishing is
By performing a thermal oxidation process on the surface region of the silicon oxide film 58 to form a thermal oxide film 61 with a thickness greater than that of the silicon oxide film 58, the polysilicon film is etched until the silicon oxide film 58 is completely removed. The surface of 60 can be covered (that is, protected) by the thermal oxide film 61. Therefore, unnecessary etching of the polysilicon film 60 can be prevented.

Further, during this etching, the thermal oxide film 6
Since 1 is an insulating film of the same quality as the silicon oxide film 58, it is removed together with the silicon oxide film 58 with a uniform thickness. As described above, the silicon oxide film 58 and the thermal oxide film 61
Since the polishing is accurately performed by the MP method, the surface of the element isolation region 63 can be formed with high accuracy. Therefore, it is possible to stably form a pattern on the element isolation region 63, and it is possible to minimize pattern formation defects.

[0112]

According to the present invention, the upper surface of the trench type element isolation structure can be formed to a desired shape with high accuracy. Therefore, a semiconductor device with improved electrical characteristics and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a configuration of an nMOS transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating a configuration of an nMOS transistor according to a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view illustrating a configuration of an nMOS transistor according to a third embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a schematic cross-sectional view showing a method for manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the nMOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a schematic cross-sectional view showing a method of manufacturing an nMOS transistor according to a second embodiment of the present invention in the order of steps.

FIG. 9 is a schematic cross-sectional view showing a method of manufacturing an nMOS transistor according to a second embodiment of the present invention in the order of steps.

FIG. 10 is a schematic cross-sectional view showing a method of manufacturing an nMOS transistor according to a third embodiment of the present invention in the order of steps.

FIG. 11 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to a third embodiment of the present invention in the order of steps.

FIG. 12 is a schematic cross-sectional view showing a method for manufacturing an nMOS transistor according to a third embodiment of the present invention in the order of steps.

[Explanation of symbols]

1,31,51 p-type semiconductor substrate 2,5,11,32,35,52,57,61,62
Thermal oxide film 3,33,53,63 Silicon nitride film 4,34,56,59 Trench (groove) 6,8,36,38,58 Silicon oxide film 7,37 Joint part 9 Element isolation oxide film 10,40 , 63 Device isolation region 12, 60, 65 Polycrystalline silicon film 13, 64 Gate oxide film 14, 65 Gate electrode 15, 66 Gate part 16 Low concentration n-type impurity diffusion region 18 Side wall insulating film 19 High concentration n-type impurity Diffusion region 20, 69 Interlayer insulating film 21, 22, 70, 71, 72 Contact hole 23, 73 Metal wiring 39 Defect 41 Depressed portion 54 Photoresist 55 Opening 67, 68 N-type impurity diffusion region

Claims (34)

[Claims] A first step of forming a heat-resistant insulating film on a semiconductor substrate; a second step of patterning the heat-resistant insulating film; A third step of selectively removing a surface and forming a trench in the semiconductor substrate; a fourth step of forming a first insulating film on the entire surface of the semiconductor substrate including the trench; A fifth step of performing heat treatment to increase the density of the first insulating film, and the first insulating film so as to fill a concave portion formed in a region corresponding to the trench on the first insulating film. Second on
A sixth step of forming a second insulating film by performing a heat treatment on the semiconductor substrate to increase the density of the second insulating film; and a first step until the heat-resistant insulating film is exposed. A method of manufacturing a semiconductor device, comprising: an eighth step of removing an insulating film and the second insulating film; and a ninth step of removing the heat-resistant insulating film exposed on the surface. 2. The method according to claim 1, wherein each of the first insulating film and the second insulating film is a silicon oxide film. 3. The method according to claim 1, wherein in the eighth step, the first insulating film and the second insulating film are removed by a chemical mechanical polishing method. 4. The method according to claim 3, wherein the heat-resistant insulating film is used as a stopper in a chemical mechanical polishing method. 5. The method according to claim 1, further comprising a step of forming a pad insulating film on the semiconductor substrate before the first step.
In the first step, the heat-resistant insulating film is formed between the semiconductor substrate and the semiconductor substrate via the pad insulating film, and in the third step, the heat-resistant insulating film is formed together with the semiconductor substrate according to the shape of the heat-resistant insulating film. 2. The method according to claim 1, wherein the pad insulating film is selectively removed. 6. The method according to claim 1, wherein the heat-resistant insulating film is removed by anisotropic etching in the ninth step. 7. The method according to claim 7, further comprising, between the third step and the fourth step, an eleventh step of forming a third insulating film in a surface region from a bottom surface to a side wall of the trench. The method for manufacturing a semiconductor device according to claim 1. 8. A first step of forming a heat-resistant insulating film on a semiconductor substrate, a second step of patterning the heat-resistant insulating film, and a step of patterning the semiconductor substrate according to the shape of the heat-resistant insulating film. A third step of selectively removing a surface and forming a trench in the semiconductor substrate; a fourth step of forming a first insulating film on the entire surface of the semiconductor substrate including the trench; A fifth step of removing the first insulating film until the film is exposed; a sixth step of removing the heat-resistant insulating film; and forming a region on the first insulating film corresponding to the trench. A seventh step of forming a second insulating film over the entire surface of the semiconductor substrate so as to fill the formed uneven portion; and forming the second insulating film so as to flatten the surface of the first insulating film. Eighth to be removed leaving only on the first insulating film
And a method of manufacturing a semiconductor device. 9. The method according to claim 8, wherein each of the first insulating film and the second insulating film is a silicon oxide film. 10. The method according to claim 8, wherein in the fifth step, the first insulating film is removed by a chemical mechanical polishing method. 11. The method according to claim 10, wherein the heat-resistant insulating film is used as a stopper in a chemical mechanical polishing method. 12. The method according to claim 12, further comprising: before the first step, forming a pad insulating film on the semiconductor substrate.
In the first step, the heat-resistant insulating film is formed between the semiconductor substrate and the semiconductor substrate via the pad insulating film, and in the third step, the heat-resistant insulating film is formed together with the semiconductor substrate according to the shape of the heat-resistant insulating film. 9. The method according to claim 8, wherein the pad insulating film is selectively removed. 13. The method according to claim 8, wherein the heat-resistant insulating film is removed by anisotropic etching in the sixth step. 14. The method according to claim 10, further comprising a tenth step of forming a third insulating film in a surface region from a bottom surface to a side wall of the trench between the third step and the fourth step. The method of manufacturing a semiconductor device according to claim 8. 15. A first step of forming a heat-resistant insulating film on a semiconductor substrate, a second step of patterning the heat-resistant insulating film, and a step of patterning the semiconductor substrate according to the shape of the heat-resistant insulating film. A third step of selectively removing a surface and forming a first trench in the semiconductor substrate; and forming a first insulating film on the heat-resistant insulating film so as to cover an inner wall surface of the first trench. Forming a second trench that is narrower than the first trench; and forming the second trench on the first insulating film so as to fill the second trench. A fifth step of forming an oxidizable film having a high polishing rate selectivity; and removing the oxidizable film until the first insulating film is exposed, and removing the oxidizable film only in the second trench. A sixth step of leaving a film; and the easy oxidation remaining in the second trench. A seventh step of thermally oxidizing the conductive film to form a first thermal oxide film in an upper surface region of the easily oxidizable film; a first insulating film exposed on the surface; An eighth step of partially removing the oxide film; and thermally oxidizing the oxidizable film remaining in the second trench again to form a second thermal oxide film on an upper surface region of the oxidizable film. A ninth step of removing the heat-resistant insulating film exposed on the surface;
And a method of manufacturing a semiconductor device. 16. The method according to claim 15, wherein the easily oxidizable film is a polysilicon film. 17. The method according to claim 15, wherein the first insulating film is a silicon oxide film. 18. The semiconductor device according to claim 18, further comprising an eleventh step of forming a pad insulating film on the semiconductor substrate before the first step, and removing the pad insulating film after the tenth step The method further includes the step of: forming the heat-resistant insulating film between the semiconductor substrate and the semiconductor substrate via the pad insulating film in the first step; and forming the pad together with the heat-resistant insulating film in the second step. The method according to claim 15, wherein the insulating film is patterned. 19. The method according to claim 15, wherein the oxidizable film is removed by a chemical mechanical polishing method in the sixth step. 20. The method according to claim 19, wherein the first insulating film is used as a stopper in a chemical mechanical polishing method. 21. The method according to claim 15, wherein a polishing rate selection ratio of the oxidizable film to the first insulating film is set to 20 times or more. 22. The film thickness of the first thermal oxide film is the first thermal oxide film.
16. The method according to claim 15, wherein the thickness of the insulating film is set to be larger than the thickness of the insulating film. 23. Between the third step and the fourth step, further comprising a thirteenth step of forming a second insulating film in a surface region from a bottom surface to a side wall of the first trench. The method for manufacturing a semiconductor device according to claim 15, wherein: 24. A semiconductor substrate having a trench formed therein, wherein the trench is filled with a first insulating film densified by heat treatment and a second insulating film also densified by heat treatment. A semiconductor device comprising an element isolation insulating film having an integral structure as a whole. 25. The semiconductor device according to claim 24, wherein each of said first insulating film and said second insulating film is a silicon oxide film. 26. A pair of source / drain regions formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate, and the pair of sources. 25. The semiconductor device according to claim 24, further comprising: a gate electrode formed on a region between the drain / drain regions via an insulating film. 27. A semiconductor substrate having a trench formed therein, wherein the trench is a first insulating film forming a main part of an element isolation structure formed on the semiconductor substrate by the trench, A semiconductor which is filled with a second insulating film formed so as to bury an uneven portion formed on the first insulating film and to flatten an upper surface of the first insulating film. apparatus. 28. The semiconductor device according to claim 27, wherein each of said first insulating film and said second insulating film is a silicon oxide film. 29. A pair of source / drain regions formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate, and the pair of sources. 28. The semiconductor device according to claim 27, further comprising: a gate electrode formed on a region between the drain / drain regions via an insulating film. 30. A semiconductor substrate in which a trench is formed, and a top surface of an end portion of a portion formed on a side wall of the trench is formed to cover a bottom surface and a side wall of the trench, and protrudes from a surface of the semiconductor substrate. A first insulating film, an oxidizable film filled in the trench so as to be surrounded by the first insulating film, and having a higher polishing rate selectivity than the first insulating film; A thermal oxide film formed in an upper surface region of the oxide film. 31. The semiconductor device according to claim 30, wherein said easily oxidizable film is a polysilicon film. 32. The semiconductor device according to claim 30, wherein said first insulating film is a silicon oxide film. 33. The semiconductor device according to claim 30, wherein a polishing rate selection ratio of the oxidizable film to the first insulating film is set to 20 times or more. 34. A pair of source / drain regions formed on an element formation region defined by an element isolation region formed by the trench and having a conductivity type opposite to that of the semiconductor substrate, and the pair of sources. 31. The semiconductor device according to claim 30, further comprising a gate electrode formed on a region between the drain / drain regions via an insulating film.