JPH0574926A - Manufacturing method for semiconductor substrate - Google Patents

Abstract

PURPOSE:To bury and fill thermally oxidized silicon in a proper manner when an element isolating layer within a semiconductor substrate is formed. CONSTITUTION:The manufacturing method for a semiconductor substrate is composed of the steps of: forming recesses 3 in a mirror surface 1a of a first semiconductor substrate 1, and forming oxygen introducing grooves 4 which are deeper than the recess, and communicate with the recess; etching the periphery of a mirror surface 2a of a second semiconductor substrate 2, which is to be joined to the first semiconductor substrate, to a predetermined width and depth, resulting in a stepped profile, and the second substrate has a terrace structure; joining the first substrate to the second substrate by heating processes, wherein the mirror surface 1a and the mirror surface 2 have been adhered to each other before the heating processes; and filling and burying a thermally oxidized silicon in a cavity 5 by introducing oxidizing atmospheric gas into the cavity formed between the recess of the first semiconductor substrate and second semiconductor substrate of the joined substrate through the oxygen introducing groove, and by heating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate having a dielectric embedded layer selectively formed inside the substrate.

[0002]

2. Description of the Related Art A dielectric isolation method has been attracting attention as an element isolation method in a semiconductor integrated circuit. As one example, a direct bonding technique for a silicon substrate and oxide film growth by thermal oxidation are used to form a dielectric embedded layer inside the substrate. As a method, a method of filling and burying thermally oxidized silicon has been proposed (for example, JP-A-61-42154).

According to this method, as shown in FIG. 7, a first semiconductor substrate 1 having a groove 4 for introducing oxygen and a shallow recess 3 communicating with the groove 4 is formed on the surface (FIG. 7A), 2 After directly bonding the semiconductor substrate 2 (FIG. 7B) (FIG.
(C)), the groove 4 is heat-treated in an oxidizing gas atmosphere.
This is a method of burying thermal silicon oxide by supplying gas into the concave portion 3 along with, and it is possible to selectively form a region electrically insulated and separated by thermal silicon oxide.

[0004]

In the above conventional method, chemical etching is unsuitable as a method for forming the recess 3 and the groove 4 on the surface of the first semiconductor substrate 1 because the outer diameter of the groove 4 is relatively large. Therefore, it is formed by dry etching such as reactive ion etching or plasma etching. However, in this case, the substrate needs to be held by the electrodes from the back surface so as to wrap the outer peripheral portion (chuck), so that it is difficult to etch the end portion of the substrate and the groove 4 may not be formed up to the outer peripheral edge of the substrate.

When the semiconductor substrates 1 and 2 are bonded in this state, the groove 4 is buried in the bonded substrate as shown in FIG. 7C and does not open to the outside air. Therefore, the groove 4 does not function as an oxygen introduction path, and oxygen is not sufficiently supplied to the recessed portion 3 in the bonded substrate. Therefore, the growth of thermally oxidized silicon is insufficient and the substrate cannot be completely filled. is there.

Therefore, the present invention can supply sufficient oxygen to the inside of the substrate even when the oxygen introduction groove cannot be opened to the end face of the substrate due to the restriction of the device such as the chuck of the wafer, and the thermal oxide silicon is used. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate, which can satisfactorily embed and fill the semiconductor substrate.

[0007]

In order to solve the above-mentioned problems, in the present invention, at least one is mirror-polished first
A step of forming a concave portion on the mirror surface of the semiconductor substrate and forming an oxygen introduction groove deeper than the concave portion communicating with the concave portion; and a second semiconductor substrate having at least one bonded to the concave groove mirror-polished.
Alternatively, the step of forming a terrace structure by etching the peripheral edge portion of the first semiconductor substrate to a predetermined width and depth to form a terrace structure, and bringing the mirror surface of the first semiconductor substrate and the mirror surface of the second semiconductor substrate into close contact with each other. And a step of joining by heat treatment, and the recess and the second portion of the first semiconductor substrate of the joined substrate.
In the cavity formed with the semiconductor substrate, an oxidizing atmosphere gas is introduced through the oxygen introducing groove, and heat treatment is performed to fill and bury the thermally-oxidized silicon in the cavity, thereby selectively insulating and separating. A semiconductor substrate having a region is manufactured.

Alternatively, by using a second semiconductor substrate having at least one of which is mirror-polished and having a diameter smaller than that of the first semiconductor substrate, and bonding the first semiconductor substrate having the recess and the oxygen introducing groove to each other, the bonding is performed. A substrate may be made.

[0009]

The mirror surface of the second semiconductor substrate having a step of a predetermined width and depth formed at the peripheral edge is one size smaller than the mirror surface of the first semiconductor substrate to be bonded thereto, and when both are bonded in this state,
The outer peripheral portion of the first semiconductor substrate is not joined. Therefore, even when the oxygen introducing groove is not opened at the edge of the first semiconductor substrate, the oxygen introducing groove is not buried in the bonding substrate but is opened to the outside air.

This is the same as in the case where the terrace structure is formed by etching the peripheral portion of the first semiconductor substrate in which the oxygen introduction groove and the recess are formed instead of the second semiconductor substrate. By etching, the oxygen introducing groove is opened at the edge of the step portion and is not closed by joining. The same is true when a second semiconductor substrate having a diameter slightly smaller than the mirror surface of the first semiconductor substrate is used, and the oxygen introduction groove can ensure communication with the outside air.

If the heat treatment is performed in such a state, a sufficient oxidizing gas can be introduced into the inside of the bonded substrate through the oxygen introduction groove opened to the outside air, the oxidation reaction proceeds well, and the cavity Thermal oxide silicon can be completely embedded and filled in the inside.

[0012]

Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. 1 (a)-(c), 2 (d), (e),
3 (f) to (j), 4 (k), and (l) are cross-sectional views showing the manufacturing process of the semiconductor substrate, FIGS. 1 (a ') to (c'), 2 (d '), and (d). e ′), FIG. 3 (h ′), (i ′), FIG.
(L ') is a plan view.

First, as shown in FIGS. 1A and 1A ', a part of the mirror surface 1a of the first semiconductor substrate 1 whose at least one surface is mirror-polished is subjected to reactive ion etching (hereinafter referred to as RIE) or chemical etching. By selective etching or the like, the recess 3 having a depth of 0.2 to 2 μm is formed by selective etching.

Next, as shown in FIGS. 1 (b) and 1 (b '),
An oxygen introduction groove 4 extending along the periphery of the recess 3 or so as to intersect the recess 3 is formed by RIE or plasma etching. Here, the shape of the oxygen introducing groove 4 is appropriately determined in consideration of the shape of the recess 3 and the substrate size. The width and depth of the oxygen introducing groove 4 are set to values larger than the depth of the recess 3. Note that the recess 3 and the oxygen introducing groove 4 may not be formed so as to open at the edge of the substrate due to the above-mentioned restrictions of the apparatus.

Next, as shown in FIG. 1C, a mask 21 for selective etching is formed by a masking tape, a resist or the like on the mirror surface 2a of the second semiconductor substrate 2 having at least one surface mirror-polished. The mask 21 has a diameter slightly smaller than that of the substrate 2 as shown in FIG.
The oxygen introduction groove 4 of the first semiconductor substrate 1 may be of any size and shape that can be opened to the outside air after bonding.

2 (d) and 2 (d '),
The peripheral edge of the substrate 2 is selectively etched by chemical etching or RIE to form a step 22 on the peripheral edge to form a terrace structure. It is desirable that the step 22 has a depth equal to or greater than the depth of the oxygen introducing groove 4.

Thereafter, these substrates 1 and 2 are respectively
For example, boiling trichlene, ultrasonic cleaning with acetone, NH ₄ O
_{H: H 2 0 2: H} 2 O = 1: 1: removal of organic matter with a mixture of _{4, HCl: H 2 0 2} : H 2 O = 1: 1: Removal of metal contamination due to a mixture of 4, and Sufficient cleaning is performed by sequentially performing cleaning with pure water.

Further, after removing the natural oxide film on the surface using a mixed solution of HF: H ₂ O = 1: 50 or the like, for example, H ₂
10 to 3 on the substrate surface by a mixed solution of SO ₄ : H ₂ 0 ₂ = 3: 1, or by thermal oxidation, oxygen plasma irradiation, etc.
An oxide layer of about 0Å is formed, and hydrophilicity is added to the layer, which is then washed with pure water. Next, after drying with dry nitrogen or the like to control the amount of water adsorbed on the substrate surface, the two substrates 1 and 2 are
The mirror surfaces 1a and 2a of No. 1 are made to face each other and are closely attached. As a result, the two substrates 1 and 2 are firmly bonded by the hydrogen bond of the silanol groups formed on the surface and the water molecules adsorbed on the surface. Further, the bonded substrates 1 and 2 are dried in a vacuum of 10 Torr or less. At this time, in order to compensate the warpage of the substrates 1 and ^2, a load of 30 g weight / cm ² or less may be applied.

Thereafter, the substrates 1 and 2 are subjected to a heat treatment at 800 ° C. or higher for 1 hour or longer in an atmosphere of an inert gas such as nitrogen or argon or in an oxidizing atmosphere, whereby a dehydration condensation reaction occurs on the adhesive surface. Occurs and silicon (S
i) and oxygen (O) are bonded (Si-O-Si), and oxygen diffuses into the substrate to bond Si atomic groups (Si-Si), as shown in Fig. 2 (e). Then, a bonded substrate is formed by directly bonding the two substrates 1 and 2. Note that FIG. 2 (e) shows an AA ′ cross section and a BB ′ cross section of (e ′), respectively.

However, at this time, the recess 3 is not joined, and the cavity 5 is formed by the recess 3 and the mirror surface 2a of the second semiconductor substrate 2 (section AA '). Also, the oxygen introduction groove 4
Even if it does not reach the edge of the substrate 1, it is opened to the outside due to the step 22 formed in the peripheral portion of the second semiconductor substrate 2 (section BB ′).

Next, as shown in FIG. 3 (f), this integrated bonded substrate is, for example, dry O ₂ , wet O ₂ , H ₂ , O.
_{2 In} an oxidizing atmosphere such as mixed combustion gas, 900 ° C or higher,
Heat treatment is performed for 1 hour or more. As a result, the oxidizing gas is introduced into the cavity 5 inside the bonded substrate via the oxygen introduction groove 4 opening to the outside, and the surface of the cavity is oxidized to grow the thermal silicon oxide 6. However, this oxidation step needs to be performed for a minimum time until the cavity 5 formed by the recess 3 and the surface of the second semiconductor substrate 2 is completely buried and filled by the growth of the thermally oxidized silicon 6 from both surfaces. is there. Through the above steps, the thermal silicon oxide 6 can be completely buried and filled in the bonded substrate as a dielectric buried layer.

Next, in the step of FIG. 3G, lapping and polishing are performed from the unbonded surface of the second semiconductor substrate 2 until the desired thickness of the insulating separation layer is obtained, and then the polished surface 2b thereof. A mask 23 for selectively etching the peripheral portion of the first semiconductor substrate 1 is provided on the top.
Formed by masking tape, resist, etc. (Fig. 3
(H)). This mask 23 is equal to or less than the mask 21 (see FIG. 1C) used for forming the step 22 on the mirror surface 2a of the second semiconductor substrate 2 as shown in FIG. To the size of. After that, FIG.
In the steps (i) and (i ′), the peripheral portion 24 of the second semiconductor substrate 2 is selectively etched and removed by chemical etching or RIE. As a result, the substrate 2 peripheral portion 2
4 can be prevented from chipping and peeling.

The selective etching step is (g)
If the thickness of the second semiconductor substrate 2 after the lapping step is smaller than the etching depth of the peripheral edge selective etching in the terrace structure forming step of FIG. 2D, that is, the peripheral edge portion of the substrate 2 by lapping. If 24 is removed, it need not be performed.

Next, in FIG. 3J, in order to form an element isolation region, an element isolation groove 25 having a width of 0.3 μm or more and a depth reaching the thermal oxide silicon 6 is formed in the second semiconductor substrate 2. Are formed by chemical etching, RIE or dicing. Here, the alignment at the time of forming the groove 25 is performed by the oxygen introduction groove 4 formed in the first semiconductor substrate 1.
Since the end of is open to the outside air (Fig. 3 (i ')),
With this as a reference, it can be performed accurately.

Thereafter, in order to form an insulating layer on the side surface of the groove 25, for example, dry O ₂ , wet O ₂ , H ₂ , O _{2 is used.}
900 ° C or higher in an oxidizing atmosphere such as mixed combustion gas, 1
Heat treatment is performed for a time or more to form a thermally oxidized silicon layer 26 having a thickness of 0.3 μm or more.

Further, as shown in FIG. 4 (k), polycrystalline silicon 27 is deposited by, for example, the CVD method, and the groove 25 is formed.
Fill in. However, the filling material at this time may be an insulator such as an oxide or a silicon nitride instead of polycrystalline silicon,
The filling method may be sputtering, vapor deposition, SOG, or the like. Further, groove 25 may not be completely filled with polycrystalline silicon 27 as long as the opening on the surface is closed, and a cavity may remain. After that, the polycrystalline silicon 27 on the surface and the surface layer 26a of the thermally oxidized silicon layer 26 are removed by, for example, lap polishing or etching back, and the surface is planarized (FIGS. 4 (l) and (l ')).

According to the present embodiment, the communication between the oxygen introducing groove 4 and the outside air can be ensured by the above steps, so that FIG.
As shown in (l), a semiconductor having a region 7 which is completely insulated from the other regions by the thermally oxidized silicon 6 embedded in the substrate, the thermally oxidized silicon layer 26 and the polycrystalline silicon 27 on the side surface. A substrate can be obtained.

By the way, in the conventional method shown in FIG. 7, after thermal oxidation, the first semiconductor substrate 1 is polished to a position where the groove 4 is exposed (shown by a chain line in FIG. 8A), and Elements are formed on the surface of the first semiconductor substrate 1.
Also, there are damages and strains due to processing when forming the grooves 4, and these serve as nuclei, and crystal defects 8 such as oxidation-induced stacking faults (OSF) due to thermal oxidation at the time of embedding the thermal oxide silicon 6 occur. These are concentrated on the semiconductor substrate 1 side (FIG. 8).
(B)). That is, many defects 8 are present on the element formation surface, which may lead to deterioration of element characteristics such as deterioration of lifetime and increase of junction leak current. On the other hand, in this embodiment, since the second semiconductor substrate 2 having no processing strain before joining is used as the element forming surface, crystal defects on the element forming surface can be significantly reduced and the element characteristics are improved.

In the conventional method, as shown in FIG. 9, when an element is formed with the groove 4 included therein without polishing until the groove 4 is exposed, it is directly bonded to the buried region of the thermal oxide silicon 6. Although the boundaries between the regions are not known, mask alignment becomes difficult in the photolithography process when forming the trenches 14 for element isolation, but in the present embodiment, a terrace structure in which the peripheral edge of the substrate is selectively etched is used to introduce oxygen. Since the groove 4 is exposed, the alignment can be easily performed. In addition, since the peripheral portion of a normal wafer is chamfered (beveled), as shown in FIG. 10, when the substrate 1 is polished to the vicinity of the bonding surface 15, chipping or peeling 16 is likely to occur at the end of the wafer. Since the peripheral portion of the substrate on the bonding surface side is removed by etching when the terrace structure is formed, chipping or peeling does not occur even if polishing is performed up to the vicinity of the bonding surface.

[0030]

Second Embodiment FIG. 5 shows another embodiment of the present invention. In the first embodiment, the peripheral edge of the wafer of the second semiconductor substrate 2 is selectively etched to form the terrace structure. However, in the present embodiment, as shown in FIG. 5A, the recess 3 and the oxygen introduction groove are formed. After the mask 11 is formed on the surface of the first semiconductor substrate 1 on which the step 4 is formed, the peripheral portion of the mask 11 is selectively etched to form the step 1
2 to form a terrace structure (FIG. 5B). Even if the oxygen introducing groove 4 is not formed up to the edge due to the step 12, the oxygen introducing groove 4 opens to the outside air (see FIG. 5B.
´)). Then, after bonding to the unprocessed second semiconductor substrate 2 (FIG. 5C), the inside of the cavity 5 is filled and filled with thermal oxide silicon 6 by thermal oxidation treatment.

Then, in the step of FIG. 5D, the first semiconductor substrate 1 side is polished to a desired thickness to expose the oxygen introducing groove 4 on the surface. After that, the peripheral edge portion of the first semiconductor substrate 1 may be selectively etched in order to prevent peeling and chipping of the edge portion of the substrate. Next, as shown in FIG. 5E, the exposed oxygen introduction groove 4 is filled with polycrystalline silicon 13, and the insulating isolation region 7 is formed.
To form.

Also in this embodiment, the thermal silicon oxide 6 can be buried well. Further, since the oxygen introducing groove 4 is exposed, it is not necessary to newly form a groove for element isolation.

[0033]

Third Embodiment FIG. 6 shows still another embodiment of the present invention.
In Examples 1 and 2 described above, the oxygen introduction groove was opened to the outside air by selectively etching the peripheral portion of the substrate to form the terrace structure, but in this Example, as shown in FIG. The second semiconductor substrate 2 is formed to have a diameter smaller than that of the first semiconductor substrate 1. When this second semiconductor substrate 2 is directly bonded to the first semiconductor substrate 1 in which the recess 3 and the oxygen introducing groove 4 are formed (FIG. 6B), the outer peripheral portion of the first semiconductor substrate 1 is exposed. As shown in (b '), the oxygen introducing groove 4 opens to the outside air.

Thereafter, in the same manner as in the first embodiment described above, the thermal oxidation treatment is used to embed and fill the thermal silicon oxide 6 in the cavity 5 (FIG. 6 (c)) and polish it from the second semiconductor substrate 2 side. After having a desired thickness, a mask 23 is formed on the polished surface of the second semiconductor substrate 2 to prevent chipping and peeling of the substrate edge (FIG. 6D), and the peripheral edge of the substrate is selectively etched. (FIG. 6 (e)). Then, after forming the trench 25 for element isolation, a thermally oxidized silicon layer 26 is formed on the side surface of the trench and the trench 25 is filled with polycrystalline silicon 27 (FIG. 6F).

Also by the method of this embodiment, the oxygen introduction groove can be opened to the outside air, and the thermal silicon oxide 6 can be buried well. Further, the alignment at the time of forming the groove for element isolation can be performed with high precision as in the first embodiment.

[0036]

As described above, when the method of the present invention is adopted, even when the oxygen introduction groove cannot be formed even at the end portion of the substrate due to the limitation of the device such as the chuck of the wafer, the oxygen is not formed at the time of joining the semiconductor substrates. Since the introduction groove is not buried and functions well as an oxygen introduction path, sufficient oxygen can be supplied to the inside of the substrate. Therefore, the inside of the substrate can be completely filled with the thermal oxide silicon, and the element is well isolated.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view showing a manufacturing process of an embodiment of the present invention.

FIG. 2 is a cross-sectional view and a plan view showing the manufacturing process of the embodiment of the present invention.

FIG. 3 is a cross-sectional view and a plan view showing the manufacturing process of the embodiment of the present invention.

FIG. 4 is a sectional view and a plan view showing the manufacturing process of the embodiment of the present invention.

5A and 5B are a sectional view and a plan view showing a manufacturing process of another embodiment of the present invention.

6A and 6B are a sectional view and a plan view showing the manufacturing process of still another embodiment of the present invention.

7A and 7B are a sectional view and a plan view showing a conventional manufacturing process of a semiconductor substrate.

FIG. 8 is a cross-sectional view showing a conventional manufacturing process of a semiconductor substrate.

FIG. 9 is a cross-sectional view and a plan view showing a conventional semiconductor substrate manufacturing process.

FIG. 10 is a cross-sectional view showing a conventional semiconductor substrate manufacturing process.

[Explanation of symbols]

 1 1st semiconductor substrate 12 level | step difference 1a mirror surface 2 2nd semiconductor substrate 22 level | step difference 2a mirror surface 3 recessed part 4 oxygen introduction groove 5 cavity 6 thermal silicon oxide

Front Page Continuation (72) Inventor Seiji Fujino 14 Iwatani, Shimohakaku-cho, Nishio-shi, Aichi Japan Auto Parts Research Institute, Inc.

Claims (2)

[Claims] 1. A step of forming a recess in a mirror surface of a first semiconductor substrate, at least one of which is mirror-polished, and an oxygen introduction groove deeper than the recess communicating with the recess, and at least one of which is bonded to the mirror surface. A step of forming a terrace structure by etching the polished second semiconductor substrate or the mirror surface peripheral portion of the first semiconductor substrate to a predetermined width and depth to form a terrace structure; and the mirror surface of the first semiconductor substrate and the second semiconductor. A step of bringing the substrates into close contact with the mirror surface and performing a heat treatment to join the substrates;
In a cavity formed with a semiconductor substrate, a step of introducing an oxidizing atmosphere gas from the oxygen introducing groove and performing heat treatment to fill and bury the thermal silicon oxide in the cavity is provided. Production method. 2. A step of forming a recess in a mirror surface of a first semiconductor substrate, at least one of which is mirror-polished, and forming an oxygen introduction groove deeper than the recess communicating with the recess, and the mirror surface of the first semiconductor substrate. A step of adhering a mirror surface of a second semiconductor substrate, at least one of which is mirror-polished and having a diameter smaller than that of the first semiconductor substrate, and performing heat treatment, and a step of joining the concave portion of the first semiconductor substrate with the concave portion of the first semiconductor substrate. 2 a step of introducing an oxidizing atmosphere gas from the oxygen introduction groove into a cavity formed with the semiconductor substrate and performing a heat treatment to fill and bury the thermal silicon oxide in the cavity. Manufacturing method.