JPH082880Y2 - EEPROM data writing device - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is based on an EEPROM (Electrically erasable and prog
The present invention relates to a data writing device of a rammable read only memory), and more specifically, to improvement of a data writing process immediately before a power failure in a microprocessor device using an EEPROM as one of memories.

<Prior Art> The EEPROM has a feature that it can electrically write / erase data and does not require a battery to hold the data, but it has a drawback that the data rewriting time is long, about 2 to 10 ms. .

Conventionally, for writing data to the EEPROM,
Some are prepared, and for example, when a power failure interrupt by a power failure notification signal occurs during the first write processing (interrupts prohibited during this time), based on the interrupt processing by the power failure notification signal after the first write processing is completed. The second write process is executed.

<Problems to be solved by the invention> For this reason, the write processing based on the interrupt processing due to the power outage notice takes about the time until the first write processing is completed
I had to wait 10ms.

The present invention has been made in view of the above circumstances, and is an EEPROM in which the second write processing based on the interrupt processing by the power failure advance notice signal can be performed without waiting 10 ms as described above. It is an object of the present invention to provide a data writing device of the above.

<Means for Solving the Problems> The present invention which achieves the above-mentioned object is provided with an EEPROM, a read / write means for the EEPROM, and a power failure interrupt request flag which is set when a power failure notice signal is received. The / write means is provided with a first write process in which an interrupt is prohibited at least during the write process and a second write process based on an interrupt request by a power failure advance signal for writing the data to the EEPROM. Therefore, when the power failure interrupt request flag is set in the middle of the first write processing, the second write processing is continuously performed in the first write processing.

<Operation> The read / write means is realized by the program of the microprocessor. While the power circuit is operating normally,
The read / write means executes the normal first write processing.

When the power supply circuit loses power, a power failure notice signal is output immediately before the power failure, and the power failure interrupt request flag is thereby set. When the power failure interrupt request flag is set during the first write operation, the read / write means continues to write the first write process, and then the second write process is performed on the area in the EEPROM (where Do in the same pace).

This makes it possible to shorten the time required for the power failure interrupt process.

<Embodiment> An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a conceptual diagram showing the construction of an embodiment of the present invention. In the figure, 1 is a microprocessor, 2 is a power supply circuit for supplying power to the microprocessor, and 3 is an EE connected to the microprocessor 1 via a bus BS.
PROM, 4 is ROM, and 5 is RAM.

In the microprocessor 1, 11 is a power failure interrupt request flag which is set by receiving a power failure notice signal output immediately before the occurrence of a power failure from the power supply circuit 2, and 12 is a read / write means for each memory including the EEPROM 3. The read / write means is provided with, for example, at least a first write processing (interruption prohibited during this time) and a second write processing based on an interrupt request by a power failure advance notice signal for writing data to the EEPROM.

Reference numeral 13 is a flag status reading means for reading the status of the power failure interrupt request flag 11, and the status data read here is transmitted to the read / write means 12 of the memory.

Here, regarding the first write processing and the second write processing, the present invention monitors, for example, a signal from a process and gives an alarm when the value of the signal exceeds a preset upper and lower limit range. A case where the present invention is applied to an alarm device for outputting will be described as an example.

In such an alarm device, the user can arbitrarily set the upper limit value and the lower limit value (parameter) for determining the upper and lower limit ranges from the front of the instrument. The set parameters are written to RAM5 (assuming that RAM5 is not backed up by a battery) or EEPROM3 if you do not want these parameters to be lost even when the power is turned off.

If the user desires that the set parameters not be lost even when the power is turned off, the user gives an instruction for the first write process and writes each set parameter to the EEPROM 3 side.

In this way, the process of writing the set parameters and the like to the EEPROM 3 side based on, for example, an instruction from the outside is the first write process.

On the other hand, although a signal to be monitored is applied to the alarm device, there is a demand to continuously monitor from the same input value even after the power failure is recovered when a power failure occurs temporarily in the monitoring state. In order to meet such a demand, a process of temporarily writing the input value immediately before the occurrence of the power failure to the EEPROM based on the power failure notice signal when the power failure occurs is performed.

As described above, the process of temporarily writing the input value to the EEPROM based on the power interruption request is the second write process.

The operation of the device configured as described above will be described below.

There are multiple normal write operations to EEPROM3, each of which has a different page (for example, NEC
In the case of the µPD28C64, one page is a 32-byte block, and the upper part of the lower 5 bits of the address is common).

FIG. 2 is a time chart showing the operation when a power failure advance notice signal is output during such a first write process.

(A) is a power failure interrupt request signal, and is the first signal shown in (b).
It is assumed that a power failure has occurred during the write processing of.

Flag state reading means 13 in the microprocessor 1
Reads the state of the power failure interrupt request flag 11 at time t1 near the end of the write processing shown in (b), and if the flag is set (when there is a power failure interrupt request), the EEPROM based on the power failure interrupt request The second write process to
As shown in (b), writing is performed within the same page as the area that has been written until then. It is assumed that this area always has a space for storing data by the second write processing.

In such an operation, by assigning the address of the second write processing to the same page as the address of the first write processing, the second write processing can be continuously performed after the first write processing. Mode light can be executed.

Here, after the completion of the second write processing, the power failure interrupt processing is performed as shown in (c), but the power failure interrupt processing here is the second power processing which has already been performed in succession to the first write processing. Since the data writing process (write process) to the EEPROM has been completed by the write process, other power interruption interrupt processes (eg reset process of various flags, etc.) excluding this write process
Is done.

FIG. 3 is a time chart showing the operation when a power interruption is generated in a state other than the above.

In this state, when a power failure interrupt request is generated as shown in (a), the power failure interrupt processing (including the second write processing) based on this request is immediately executed at that time as shown in (b). To do. The write process in this case is EEPR
It is done in a certain area within the OM.

<Effect of Device> As described in detail above, according to the present invention, the EEPROM
When a power failure interrupt occurs during write processing to, and if the write processing is performed even within that interrupt, both write processing are performed consecutively, which is necessary when performing these write processing separately. The waiting time for the completion of writing can be eliminated, and the time required for a power interruption can be shortened.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart showing the operation when a power failure notice signal is output during the first write processing, and FIG. 3 is FIG. 7 is a time chart showing the operation when a power interruption is generated in a state other than that shown in FIG. 1 ... Microprocessor 2 ... Power supply circuit 3 ... EEPROM 4 ... ROM 5 ... RAM 11 ... Power interruption request flag 12 ... Read / write means 13 ... Flag status reading means

Claims (1)

[Scope of utility model registration request] 1. An EEPROM, a read / write means for the EEPROM, and a power failure interrupt request flag which is set when a power failure advance signal is received, and the read / write means is for writing data to the EEPROM. At least during the write processing, a first write processing in which an interrupt is prohibited and a second write processing based on an interrupt request by a power failure notice signal are prepared, and while the first write processing is being performed, An EEPROM data writing device, characterized in that, when a power failure interrupt request flag is set, the second write process is continuously performed in the first write process.