JPS62272815A - Digital protective relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) The present invention relates to a digital protective relay device, particularly a digital protective relay device equipped with a measure for failure cause analysis. It is related to.

(Prior Art) Computers generally store failure analysis information in order to analyze the cause of failure when a failure occurs. Even in a digital protective relay device using a microprocessor, information for failure analysis is stored in order to facilitate failure analysis. At this time, if a RAM is used as the information storage element, the stored failure analysis information will be lost when the power is turned off. Therefore, as storage elements for information for failure analysis when the power is cut off, for example, ■ Information storage using RAM with capacitor backup, ■ Non-volatile R
Information storage by AM, information storage by ΦE2PROM,
■It has been proposed to store information by writing to E2PROM when the power is turned off.

(Problems to be Solved by the Invention) Each of the above-mentioned proposals is not sufficient and has the following problems.

In case (2), the information retention time depends on the capacitance of the capacitor, making it difficult to retain information for a long time.

In the case of (2), there are currently few large-capacity devices available and they are expensive.

In the case of (2), an EPROM in which specific memory contents can be electrically erased and written has a limit on the number of times it can be written, and if failures occur frequently, the predetermined number of times it can be written will be exceeded.

In the case of (2), it takes approximately 10 m5 to write to the E2PROM, and it is difficult to write a large amount of information while the power supply is within a predetermined range after a power drop is detected.

The present invention has been made to solve the above problems, and by using E2PRQM as an information storage element, υ failure analysis information can be easily retained even when the power is turned off.
Another object of the present invention is to provide a digital protective relay system that does not cause excessive writing to the E2F ROM even when failures occur frequently.

[Structure of the invention]

(Means for Solving the Problems) The configuration for achieving the above object will be explained using FIG. 1 corresponding to the embodiment. In the present invention, the E2F ROM does not lose its memory contents even if the control power is turned off. It has been established.

(Function) Therefore, the failure analysis information that is left out from the system when a failure occurs is temporarily stored in the RAM, and the failure analysis information detected in the EPROM is written from the RAM only once after a predetermined period of time after the failure is detected. I try to get into it.

(Example) An example will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a digital protective relay device according to the present invention.

In Figure 1, voltage and current information from power transmission line l is PT
3, is taken into the digital protective relay device 3 via Cr2. 31 is input/output interface (Ilo)
-32 is CPU #33 is RAM, 34 is E2
PROM, 35 has haste, VOr)! -131
The CPU 32 is configured to perform a predetermined protection operation based on information taken in from the CPU 32. Note that the writing of failure analysis information is done by the failure detection process shown in Figure 2.
This is done only once for PROM 34. These relationships will be explained using the time charts of FIGS. 2 and 4. In FIG. 2, when a failure occurs, the starting auxiliary relay 22 is activated and closes the contact 22 (FIG. 4(b)). As a result, the cine good detection timer 23 starts operating after the time limit T (Fig. 4(C)), and outputs an operating signal via the contact 24 (Fig. 4(d)).
), the failure analysis information is written to the E 2P ROM once.

In short, when a defect occurs, the information for defect analysis is first stored in RAM.
Write to. Since there is no limit to the number of times that RAM can be written, failure analysis information is written every time a failure occurs. Thereafter, the failure analysis information stored in the RAM is written to the E2PROM for information storage after the power is turned off.

FIG. 3 is a flowchart showing the overall processing contents. First, in step f31, 28TI and conditions are read. Here, if the 28T operation flag is ON in Stella f32, the process ends because a defect has already been detected, and if the 28T operation flag is not ON, the process moves to step 33, where it is determined whether or not the 28T operation is being performed.

If 28T is not operating, go to step 35 and 28
Turn off the T operation flag. Note that the 28T operation flag is E.
This flag is used to write to PROM only once.

If it is 28T operation in step 33, proceed to step 34, turn on the 28T operation flag, read out the already stored failure analysis information from RAM (step 36), and write it to E2PROM in stay 7' 37. . Then, at Stella 7'' 38, it is determined whether or not all information writing has been completed, and step 36 is carried out until all information writing is completed.
, 37 and 38 are repeated for 0 or more, writing to the E2PROM is performed only once after a cine failure occurs.

As described above, according to this embodiment, information for failure analysis is written to the %E PROM during 28T operation when a failure occurs. Information can be stored reliably. Further, since writing to the E2PROM is only performed during 28T operation, it is possible to prevent the number of times of writing from exceeding.

FIG. 5 is a block diagram of another embodiment. In FIG. 5, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

36 is a DMA controller), and in this embodiment, after a failure occurs, the DMAC is activated (by the operation signal 28TL of 28T), and the failure analysis information stored in the RAM is automatically sent to the E2PROM without going through the CPU. I am asking you to write exactly. Therefore, according to this embodiment, high-speed transfer of failure analysis information is possible.

FIG. 6 is a block diagram of still another embodiment. In FIG. 6, the same parts as in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted.

Reference numeral 37 denotes an external switch, and in this embodiment, when a failure occurs, the external switch 37 is operated to write failure analysis information from the RAM to the EPROM (by program arithmetic processing). Therefore, according to the present example, B when serious failure continues
It is possible to prevent the number of times of failure analysis information being written to the 2F ROM.
It goes without saying that much faster transfer is possible by writing to M using DMA.

〔Effect of the invention〕

As explained above, according to the present invention, once a defect is detected, R
Since the configuration is such that the information for quality analysis is stored in the AM and written to the E2PROM only once after a predetermined period of time, the information for failure analysis can be easily retained even if the power is cut off, and the cause of the failure can be easily analyzed. It is possible to provide a digital protective relay device that is capable of

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment of a digital protective relay device according to the present invention, Fig. 2 is a circuit diagram for defect detection processing, Fig. 3 is a flowchart of writing processing, and Fig. 4 is a defect detection processing FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a block diagram of still another embodiment of the present invention.

Claims (5)

[Claims] (1) In a digital protective relay device that performs operation judgment calculations using system voltage and current values sampled at predetermined time intervals and converted into digital quantities, there is a memory RAM that can be read and written at any time, and a memory RAM that can be read and written at any time. E^2PRO is a writable non-volatile memory that does not erase memory contents.
M, temporarily stores failure analysis information input from the system when a failure is detected in a RAM, and transfers the failure analysis information from the RAM to the E^2P at a predetermined time after the failure detection.
A digital protective relay device characterized by writing to ROM. (2) The digital protective relay device according to claim 1, wherein the writing to the E^2PROM is performed by program calculation processing when a timer is activated after a predetermined time has elapsed from the detection of a defect. . (3) The digital protective relay device according to claim 1, wherein writing to the E^2PROM is performed directly via DMA during operation of a timer that operates a predetermined time after detection of a defect. . (4) The digital protective relay device according to claim 1, wherein writing to the E^2PROM is performed by program calculation processing by manual operation using an external switch. (5) The digital protective relay device according to claim 1, wherein writing to the E^2PROM is performed via DMA by manual operation using an external switch.