JP5348541B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a writing error to a nonvolatile memory when power is interrupted. <P>SOLUTION: The nonvolatile memory 4 receives first and second rewritable signals FHVED and FGVEI from the outside. The first rewritable signal FHVED is given to a first voltage supply control part 20D provided in a data area 10D via a latch circuit 30D. When the first rewritable signal FHVED is active, the first voltage supply control part 20D supplies high voltage generated by an internal power circuit (boosting circuit) 11 to a memory array 40D in the data area 10D. The second rewritable signal FHVEI is given to a second voltage supply control part 20I via a latch circuit 30I. When the second rewritable signal FHVEI is active, the second voltage supply control part 20I supplies the high voltage generated by the internal power circuit (boosting circuit) 11 to a memory array 40I in a code area 10I. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having an electrically rewritable nonvolatile memory, and more particularly to a semiconductor device having a configuration for preventing erroneous rewriting of a nonvolatile memory.

  In a nonvolatile semiconductor memory such as an EEPROM (Electronically Erasable and Programmable Read Only Memory) or a flash memory, a voltage higher than that at the time of data reading is applied to the memory cell at the time of data rewriting of the memory cell. For this reason, if a power interruption or an instantaneous power failure occurs during data rewriting, the data stored in the memory cell may be destroyed.

  Japanese Patent Laid-Open No. 5-342115 (Patent Document 1) discloses a technique for preventing data destruction that may occur at the time of power-off without providing a special auxiliary power supply. Specifically, the semiconductor device described in this document is provided with a capacitor that charges the supply voltage from the main power supply and a diode that prevents backflow from the capacitor. When a power interruption occurs in the main power supply, the discharge of the capacitor is supplied to a subsequent circuit including a CPU (Central Processing Unit) and a memory through the stabilized power supply. Thereby, a time for storing data in the memory by the CPU is secured.

  JP-A-4-137080 (Patent Document 2) discloses that only program power is applied to an IC (Integrated Circuits) memory card driven by a logical power supply (5 V power supply) and a program power supply (12 V power supply). Disclosed is a technique for preventing data destruction that occurs in Specifically, the IC memory card described in this document includes detection means for detecting the voltage of the logic power supply and switching means for controlling the program power supply on and off based on the output of the detection means.

JP-A-5-342115 JP-A-4-137080

  However, as in the technique described in Japanese Patent Laid-Open No. 5-342115 (Patent Document 1), there is a problem that the circuit area increases when a capacitor is loaded to prevent a decrease in power supply voltage. . Further, as in JP-A-4-137080 (Patent Document 2), when a new circuit is added to prevent data destruction, the circuit configuration becomes complicated and the circuit area increases.

  An object of the present invention is to provide a semiconductor device capable of reducing the possibility of erroneous writing to a nonvolatile memory at the time of power interruption or instantaneous power failure by simple means.

  A semiconductor device according to an embodiment of the present invention includes first and second memory arrays, a first power supply circuit, a rewrite command unit, and first and second voltage supply control units. In the first and second memory arrays, a plurality of electrically rewritable nonvolatile memory cells are arranged. The first power supply circuit generates a rewrite voltage necessary for rewriting data in each memory cell. The rewrite command unit commands data rewrite of the first and second memory arrays. The first voltage supply control unit supplies a rewrite voltage from the first power supply circuit to the first memory array in accordance with a command from the rewrite command unit when the first rewritable signal is in an activated state. The second voltage supply control unit supplies a rewrite voltage from the first power supply circuit to the second memory array in accordance with a command from the rewrite command unit when the second rewritable signal is in an activated state.

  According to this embodiment, when data rewriting of the first memory array is performed, only the first rewritable signal is activated, and when data rewriting of the second memory array is performed, the second rewritable is possible. Only the signal can be activated. Therefore, since the supply of the rewrite voltage is prohibited by the rewritable signal to the memory array that does not rewrite data, the possibility of erroneous data writing can be reduced.

It is a block diagram which shows the structure of the microcomputer 1 according to Embodiment 1 of this invention. It is a block diagram which shows the detailed structure of the non-volatile memory 4 of FIG. FIG. 3 is a block diagram showing a configuration of a latch circuit 30 in FIG. 2. FIG. 4 is a circuit diagram illustrating an example of a configuration of a level shifter 31 in FIG. 3. FIG. 4 is a timing chart showing an operation of the latch circuit 30 of FIG. 3 (in a case other than rewriting). FIG. 4 is a timing chart showing the operation of the latch circuit 30 of FIG. 3 (in the case of rewriting). FIG. 4 is a timing diagram showing an operation of the latch circuit 30 of FIG. 3 (when reset during rewriting). It is a table | surface which shows the voltage level of the rewritable signal FHVED, FHVEI, and VHVEX corresponding to a memory array operation state. FIG. 3 is a block diagram showing a configuration of a nonvolatile memory 104 as a modification of the nonvolatile memory 4 of FIG. 2. It is a block diagram which shows the structure of the microcomputer 201 as a modification of the microcomputer 1 of FIG. It is a block diagram which shows the structure of the microcomputer 301 according to Embodiment 2 of this invention. FIG. 12 is a block diagram illustrating a detailed configuration of the nonvolatile memory 304 of FIG. 11.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the following description, a microcomputer having a nonvolatile memory will be described as an example. However, the present invention is also applicable to other types of semiconductor devices having a nonvolatile memory.

<Embodiment 1>
[Microcomputer configuration]
FIG. 1 is a block diagram showing a configuration of a microcomputer 1 according to the first embodiment of the present invention. Referring to FIG. 1, a microcomputer 1 (semiconductor device) connects a CPU 2, a RAM (Random Access Memory) 3, a nonvolatile memory 4, a peripheral circuit 5, an interface circuit 7, and these components to each other. A data bus 8 and a power supply circuit 6 (second power supply circuit) are included.

  The power supply circuit 6 receives an external power supply voltage VCC (for example, 3 V) from the outside of the microcomputer 1 and generates an internal power supply voltage VDD (for example, 1.5 V) that is lower than the external power supply voltage VCC. The internal power supply voltage VDD is supplied to each part of the microcomputer 1.

  The power supply circuit 6 monitors the voltage level of the generated internal power supply voltage VDD, and outputs a monitor signal VDDONL that is activated when the internal power supply voltage VDD reaches a predetermined voltage level. The signal level of the monitor signal VDDONL is a VCC signal that becomes the power supply voltage VCC when it is at the H level and becomes the ground voltage GND when it is at the L level. Hereinafter, when clearly indicating that the signal is a VCC signal, VCC is added to the end of the reference symbol as in the monitoring signal VDDONL_VCC. Similarly, in the case of a VDD-type signal that becomes the power supply voltage VDD at the H level and becomes the ground voltage GND at the L level, it is distinguished by adding VDD to the end of the reference symbol.

  The nonvolatile memory 4 is a semiconductor storage device such as an EEPROM or a flash memory. Each memory cell of these semiconductor memory devices has a floating gate between the control gate and the channel layer. Information is stored in each memory cell depending on the presence or absence of charges accumulated in the floating gate. Note that a silicon nitride film can be used as the charge trapping layer instead of the floating gate.

  In this type of memory cell, when charge is injected into the floating gate (write mode) or when charge is extracted from the floating gate (erase mode), a voltage higher than the normal operation mode is applied to the control gate, source region, Or it needs to be applied to a P-type well or the like. Therefore, the nonvolatile memory 4 is provided with a booster circuit 11 (first power supply circuit) that boosts the internal power supply voltage VDD. The booster circuit (internal power supply circuit) 11 generates a write voltage, an erase voltage, and a read voltage to be applied to the control gate and the like in the write mode, erase mode, and read mode. In this specification, the write voltage and the erase voltage are collectively referred to as a rewrite voltage. Further, the voltages generated by the booster circuit 11 are collectively referred to as a control voltage.

  The non-volatile memory 4 shown in FIG. 1 is provided with a code area 10I and a data area 10D. The memory array in the code area 10I mainly stores program information. The memory array in the data area 10D stores processing results obtained by the arithmetic processing of the CPU 2 and data from the outside of the microcomputer 1. Normally, the number of rewrites of data stored in the code area 10I is smaller than the number of rewrites of data stored in the data area 10D. Details of the configuration of the code area 10I and the data area 10D will be described later with reference to FIG.

  By the way, when the external power supply voltage VCC supplied to the power supply circuit 6 is cut off or the power supply circuit 6 is momentarily interrupted, the internal power supply voltage VDD is lowered, so that the logic level of the signal inside the nonvolatile memory 4 becomes indefinite. . At this time, if the nonvolatile memory 4 is rewriting data, a high voltage is generated by the booster circuit (internal power supply circuit) 11, so that the high voltage may be accidentally applied to the memory cell and data may be rewritten. There is.

  In order to reduce the possibility of such erroneous data rewriting, the nonvolatile memory 4 is supplied with rewritable signals FHVED, FHVEI, and FHVEX from outside the microcomputer 1. These rewritable signals FHVED, FHVEI, and FHVEX are VCC signals, and are provided corresponding to a plurality of areas of the nonvolatile memory 4 individually. Specifically, the rewritable signal FHVED corresponds to the data area 10D, and the rewritable signal FHVEI corresponds to the code area 10I. The rewritable signal FHVEX corresponds to a special area provided in the memory cells of the data area 10D and the code area 10I. Each area is controlled to be in a rewritable state when a corresponding rewritable signal is in an activated state. As described above, since a rewritable signal is provided for each of a plurality of areas, application of a high voltage to an area that is not a data rewrite target can be prevented, so that the possibility of erroneous data rewriting can be reduced. A more detailed control procedure will be described later with reference to FIGS.

  As shown in FIG. 1, the microcomputer 1 is also provided with a terminal for receiving a reset signal RST for resetting the microcomputer 1 from the outside.

[Configuration of non-volatile memory]
FIG. 2 is a block diagram showing a detailed configuration of the nonvolatile memory 4 of FIG. FIG. 2 mainly shows components used for data rewriting of the memory cell among the components of the nonvolatile memory 4.

  Referring to FIG. 2, nonvolatile memory 4 includes a data area 10D and a code area 10I. These data area 10D and code area 10I are provided with memory arrays 40D and 40I for storing data, respectively.

  The memory array 40D in the data area 10D further includes a normal area 41D and a special area 42D. In the normal area 41D, processing results obtained by arithmetic processing of the CPU 2 and data from the outside of the microcomputer 1 are stored. The special area 42D stores an area for storing a boot program at system startup, redundant bytes for storing defective block information and error correction codes, and power supply trimming information for finely adjusting the rewrite voltage. An area or the like is provided.

  Similarly, the memory array 40I of the code area 10I includes a normal area 41I and a special area 42I. Program information corresponding to the application is stored in the normal area 41I. Further, the special area 42I is provided with an area for storing a boot program and power supply trimming information, a redundant byte, and the like, similar to the special area 42D provided in the data area 10D.

  A plurality of code areas 10I may be provided in the nonvolatile memory 4. When a plurality of code areas 10I are provided, a rewritable signal FHVEI individually corresponding to each code area 10I is supplied from the outside of the microcomputer 1.

  In the data area 10D of the nonvolatile memory 4, a P / E sequencer 21 (rewrite command unit), an internal power supply circuit 11 (first power supply circuit), and a power supply control signal generation for generating control signals for the internal power supply circuit 11 are further provided. A unit 22 and a test internal register 13 (test control unit) are provided. These constituent elements 11, 21, 22, and 13 are provided in common in the memory arrays 40D and 40I of the data area 10D and the code area 10I.

  The data area 10D further includes a power switch unit 14D (distributor), a power switch control signal generator 23D that generates a control signal for the power switch unit 14D, an X decoder 15D, and an X system control that generates a control signal for the X decoder. A signal generator 24D is provided. Each of these components 14D, 23D, 15D, and 24D is provided exclusively for the memory array 40D in the data area 10D.

  P / E sequencer 21 is provided to control internal power supply circuit 11, power switch unit 14D, and X decoder 15D in a predetermined sequence at the time of data writing and data erasing in accordance with a command from CPU 2 in FIG. . In accordance with commands from P / E sequencer 21, power supply control signal generator 22, power supply SW control signal generator 23D, and X-system control signal generator 24D are connected to internal power supply circuit 11, power switch 14D, and X decoder, respectively. A control signal is output to 15D.

  The internal power supply circuit 11 generates a control voltage used in each operation mode such as writing, erasing, and reading based on the internal power supply voltage VDD. The internal power supply circuit 11 is configured by, for example, a charge pump circuit. The internal power supply circuit 11 boosts the internal power supply voltage VDD to a predetermined voltage or stops boosting according to a control signal from the power supply control signal generator 22.

  The power switch unit 14D supplies various control voltages (write voltage, erase voltage, read voltage) generated by the internal power supply circuit 11 in accordance with each operation mode, an X decoder 15D, a column selection circuit (not shown), and a sense. Distribute to amplifiers (not shown). The power switch unit 14D includes a plurality of switches that perform on / off control of supply of a plurality of control voltages. The plurality of switches are turned on or off according to a control signal from the power supply SW control signal generator 23D. The power switch 14D and the power SW control signal generator 23D function as a voltage supply controller 20D that supplies a control voltage from the internal power circuit 11 to the memory array 40D in accordance with a command from the P / E sequencer 21.

  The X decoder 15D supplies the control voltage supplied from the power switch unit 14D to the word lines, source lines, P-type wells, etc. of the memory array 40D according to the X address signal supplied from the X-system control signal generator 24D. .

  The internal register 13 is provided for changing the output voltage of the internal power supply circuit 11 during the burn-in test. During the burn-in test, data is set in the internal register 13 in accordance with a command from the CPU 2 in FIG. Then, a control signal corresponding to the data set in the internal register 13 is output from the power control signal generator 22 to the internal power circuit 11.

  Similarly to the above, the code area 10I of the non-volatile memory 4 has a power switch unit 14I (distributor) dedicated to the code area 10I, a power switch control signal generator 23I that generates a signal for controlling the power switch unit 14I, An X decoder 15I and an X system control signal generator 24I for generating a signal for controlling the X decoder 15I are provided. Since the functions of these components are the same as those of data area 10D, description thereof will not be repeated. The power supply switch unit 14I and the power supply SW control signal generation unit 23I function as a voltage supply control unit 20I that supplies a control voltage from the internal power supply circuit 11 to the memory array 40I in accordance with a command from the P / E sequencer 21.

[Control of nonvolatile memory 4 by rewritable signal]
As described with reference to FIG. 1, the nonvolatile memory 4 is controlled so that the corresponding area can be rewritten when the rewritable signals FHVED, FHVEI, and FHVEX are activated. Hereinafter, a specific control method will be described.

(1. Control of power supply SW control signal generator 23D by rewritable signal FHVED)
First, when the rewritable signal FHVED is in the activated state, the power switch control signal generating unit 23D in the data area 10D turns on or off a predetermined switch of the power switch unit 14D according to a command from the P / E sequencer 21. A control signal is output so as to be in a state.

  On the other hand, when the rewritable signal FHVED is in an inactive state, basically, the power switch control signal generator 23D is for the high voltage of the power switch unit 14D regardless of the command content of the P / E sequencer 21. A control signal is output to turn off the switch. However, as an exception, when the memory array 40D is rewriting data, the power supply SW control signal generator 23D continues to supply a high voltage from the internal power supply circuit 11 to the memory array 40D until the data rewriting is completed. The power switch unit 14D is controlled. This is because if the supply of the rewrite voltage to the memory array suddenly stops during the data rewrite, the data stored in the memory array may be destroyed.

  In order to perform such control, a latch circuit 30D that holds the logic state of the rewritable signal FHVED is provided in the data area 10D of the nonvolatile memory 4. The latch circuit 30D further receives a control signal seqmode_on from the P / E sequencer 21. The control signal seqmode_on is a signal that is activated (H level) during data rewriting.

  Specifically, the latch circuit 30D holds the logic state of the rewritable signal FHVED when the control signal seqmode_on is switched to the activated state (H level), and the control signal seqmode_on is in the inactivated state (L level). The held logic state is output until it is switched to. On the other hand, while the control signal seqmode_on is in an inactive state (L level), the latch circuit 30D outputs the logical state of the input rewritable signal FHVED as it is. A more detailed configuration of the latch circuit 30D will be described later with reference to FIGS.

  The data area 10D of the nonvolatile memory 4 is further provided with a level shifter 12 for level shifting (stepping down) the output of the latch circuit 30D from the VCC system to the VDD system. The level shifter 12 can be constituted by, for example, an inverter circuit that operates at the internal power supply voltage VDD.

  The power switch control signal generator 23D for the power switch unit 14D receives the output of the latch circuit 30D converted to the VDD system by the level shifter 12 as a rewritable signal fhved_vdd. When the rewritable signal fhved_vdd is in the activated state (H level), the power switch control signal generating unit 23D turns on or off a predetermined switch of the power switch unit 14D according to a command from the P / E sequencer 21. Such a control signal is output. On the other hand, when the rewritable signal fhved_vdd is in an inactive state (L level), the power SW control signal generator 23D switches the high voltage switch of the power switch 14D regardless of the command content of the P / E sequencer 21. A control signal is output so that is turned off.

(2. Control of power supply SW control signal generator 23I by rewritable signal FHVEI)
The control method for the power supply SW control signal generator 23I of the code area 10I by the rewritable signal FHVEI is the same as that of the rewritable signal FHVED for the data area 10D. In other words, the data area 10D of the nonvolatile memory 4 is provided with a latch circuit 30I that holds the logic state of the rewritable signal FHVEI. The latch circuit 30I further receives a control signal seqmode_on from the P / E sequencer 21. The specific operation of the latch circuit 30I is the same as that of the latch circuit 30D. Hereinafter, the latch circuits 30D and 30I are also collectively referred to as the latch circuit 30 when they are generically referred to, or when they indicate unspecified ones.

  The power switch control signal generator 23I for the power switch unit 14I receives the output of the latch circuit 30I converted into the VDD system by the level shifter 12 as a rewritable signal fhvei_vdd. When the rewritable signal fhvei_vdd is in the activated state (H level), the power switch control signal generator 23I turns on or off a predetermined switch of the power switch unit 14I according to a command from the P / E sequencer 21 Such a control signal is output. On the other hand, when the rewritable signal fhvei_vdd is in an inactive state (L level), the power SW control signal generator 23I switches the high voltage switch of the power switch 14I regardless of the content of the command of the P / E sequencer 21. A control signal is output so that is turned off.

(3. Control of power supply control signal generator 22 by rewritable signals FHVED and FHVEI)
The power supply control signal generator 22 for the internal power supply circuit 11 receives rewritable signals fhved_vdd and fhvei_vdd in which the outputs of the latch circuits 30D and 30I are level-converted to the VDD system by the level shifter 12. The power supply control signal generator 22 generates a high voltage according to a command from the P / E sequencer 21 when at least one of the rewritable signals fhved_vdd and fhvei_vdd is in an activated state (H level). Output a control signal. On the other hand, when both of the rewritable signals fhved_vdd and fhvei_vdd are inactive (L level), the power supply control signal generator 22 generates a high voltage from the internal power supply circuit 11 regardless of the command content of the P / E sequencer 21. A control signal is output to stop the generation of.

(4. Control of special areas 42D and 42I by rewritable signal FHVEX)
The special areas 42D and 42I of the memory arrays 40D and 40I are supplied with a rewritable signal fhvex_vdd in which the rewritable signal FHVEX is level-converted to the VDD system by the level shifter 12. The memory cells in the special areas 42D and 42I are rewritable when the rewritable signal fhvex_vdd is in an activated state (H level), and are rewritable when the rewritable signal fhvex_vdd is in an inactivated state (L level). For example, in the case of a flash memory, the cell block cannot be selected when the rewritable signal fhvex_vdd is in an inactive state (L level).

  Normally, data stored in the memory cells in the special areas 42D and 42I is rewritten by the manufacturer of the microcomputer 1. Therefore, it is considered that there is a low possibility that the rewritable signal FHVEX is reset to the L level by mistake during data rewriting. Therefore, no latch circuit is provided for the rewritable signal FHVEX.

(5. Control of internal power supply circuit 11 by rewritable signals FHVED and FHVEI)
Internal power supply circuit 11 receives rewritable signals FHVED and FHVEI supplied from the outside without passing through latch circuits 30D and 30I. When at least one of the rewritable signals FHVED and FHVEI is in an activated state (H level), the internal power supply circuit 11 generates a high voltage (write voltage, erase voltage, etc.) according to a control signal from the power supply control signal generator 22. Control voltage) can be generated. Internal power supply circuit 11 does not generate a high voltage when rewritable signals FHVED and FHVEI are both in an inactive state (L level).

  Therefore, even when the logic state of the signal in the nonvolatile memory 4 becomes indefinite when the power supply circuit 6 in FIG. 1 returns after the power is shut off, as long as both the rewritable signals FHVED and FHVEI are at the L level, The internal power supply circuit 11 does not generate a high voltage. As a result, it is possible to prevent a high voltage from being erroneously applied to the memory cell.

  The charge pump circuit constituting the internal power supply circuit 11 is provided with a charge storage capacitor. For this reason, even if the rewritable signals FHVED and FHVEI are reset to the L level during the data rewriting of the memory cell, the output of the internal power supply circuit 11 does not suddenly decrease. Therefore, the internal power supply circuit 11 is directly supplied with rewritable signals FHVED and FHVEI without going through the latch circuits 30D and 30I.

(6. Control of test internal register 13 by rewritable signals FHVED, FHVEI, and FHVEX)
The test internal register 13 receives VDD-related rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd. The output of the internal register 13 is valid only when the rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd are all in an activated state (H level), and otherwise the output of the internal register 13 is invalidated.

  Therefore, when the power supply circuit 6 in FIG. 1 is restored after the power supply is cut off, even if the logic state of the test internal register 13 is indefinite, the internal power supply circuit 11 erroneously causes the high voltage for burn-in test. Is not generated. As a result, it is possible to prevent erroneous application of the test high voltage 1 to the memory cell.

  Note that the test internal register 13 can be controlled using a new rewritable signal instead of the rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd. However, in this case, it is necessary to provide a new external terminal in the microcomputer 1. As described above, by sharing the rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd for controlling the internal register 13, the total number of external terminals provided in the microcomputer 1 can be reduced.

  Further, during the recovery after the externally input power supply voltage VCC itself has failed, the logic states of the outputs of the latch circuits 30D and 30I (rewritable signals fhved_vdd and fhvei_vdd) become undefined. By using the rewritable signal fhved_vdd that does not pass through the latch circuit as described above, it is possible to prevent a high voltage for testing from being erroneously applied to the memory cell even during recovery after such power supply voltage VCC is lost. it can.

[Configuration and operation of latch circuit]
Hereinafter, the configuration and operation of the latch circuit 30 of FIG. 2 will be described in more detail.

  FIG. 3 is a block diagram showing a configuration of the latch circuit 30 of FIG. 2 and 3, the latch circuit 30 includes a level shifter 31 that converts (boosts) a VDD control signal seqmode_on into a VCC signal, an inverter IV4 that inverts the output of the level shifter 31, and an external power supply voltage. And a D latch 32 operating at VCC.

  The control signal seqmode_on is output from the P / E sequencer 21. The control signal seqmode_on is activated (H level) during data rewriting (writing mode, erasing mode) of the memory array 40D or 40I, and is deactivated (L level) at times other than data rewriting.

  Inverter IV4 operates with external power supply voltage VCC. The output signal Fhelatch of the inverter IV4 is a VCC signal.

  The D latch 32 generally has an input terminal D, an output terminal Q, and a clock input terminal CLK. When the clock input is at the H level, the D latch 32 outputs from the output terminal Q a signal having the same logic level as the logic level of the input signal to the input terminal D. On the other hand, the D latch 32 holds the logic level of the input signal when the clock input is switched to the L level until the input signal returns to the H level. While the clock input is at the L level, the D latch 32 outputs the held logic level signal from the output terminal Q.

  In the case of FIG. 3, the VCC rewritable signal FHVED (or FHVEI) is input to the input terminal D, and the output signal Fhelatch (VCC system) of the inverter IV4 is input to the clock input terminal CLK. Since the D latch 32 operates upon receiving the external power supply voltage VCC, the signal Infhved (or Infhvei) output from the output terminal Q is a VCC signal. By operating the D latch 32 with the external power supply voltage VCC, even if the power supply circuit 6 in FIG. 1 is in a power failure state, the logic level of the output of the D latch 32 does not become unstable.

  The level shifter 31 is a circuit that converts (boosts) a VDD signal to a VCC signal. In the case of FIG. 3, the level shifter 31 converts the level of the control signal seqmode_on output from the P / E sequencer 21 into a VCC signal.

  Further, the level shifter 31 is further supplied with a monitoring signal VDDONL that is activated (H level) when the power supply voltage VDD reaches a predetermined voltage level. The level shifter 31 is controlled by the monitoring signal VDDONL so that a through current does not flow through the level shifter 31 when the internal power supply voltage VDD is decreasing during recovery after power-off.

  FIG. 4 is a circuit diagram showing an example of the configuration of the level shifter 31 of FIG. Referring to FIG. 4, level shifter 31 includes PMOS (P-channel Metal Oxide Semiconductor) transistors QP1, QP2, and QP3, NMOS (N-channel Metal Oxide Semiconductor) transistors QN1, QN2, and QN3, and internal power supply voltage VDD. Inverters IV1 and IV2 that operate, and inverter IV3 that operates with external power supply voltage VCC are included.

  First, connection between each element of the level shifter 31 will be described. Transistors QP1 and QN1 are connected in this order between the power supply node (VCC) and node ND3. Transistors QP2 and QN2 are connected in parallel with transistors QP1 and QN1 between power supply node (VCC) and node ND3 in this order. Transistor QP3 is connected in parallel with transistor QP2. Transistor QN3 is connected between node ND3 and a ground node (GND). The gate of the transistor QP1 is connected to the drain (node ND2) of the transistor QP2, and the gate of the transistor QP2 is connected to the drain (node ND1) of the transistor QP1. Inverter IV1 inverts control signal seqmode_on and outputs the inverted signal to the gate of transistor QN1. Inverter IV2 inverts the output of inverter IV1 and outputs the result to the gate of transistor QN2. The monitor signal VDDONL is input to the gates of the transistors QP3 and QN3. Inverter IV3 inverts and shapes the voltage at node ND2 and outputs the result. The output of the inverter IV3 is further inverted by the inverter IV4 of FIG. 3, and is supplied to the clock input terminal CLK of the D latch 32 as the signal Fhelatch.

Next, the operation of the level shifter 31 in FIG. 4 will be described.
First, since the monitor signal VDDONL_VCC is at the L level until the internal power supply voltage VDD reaches a predetermined voltage level, the transistor QP3 is in the conductive state. As a result, the drain (node ND2) of the transistor QP2 becomes equal to the power supply voltage VCC, and the output signal / Fhelatch of the level shifter 31 is fixed at the L level. Thus, the transistor QP3 is provided so that the output of the level shifter 31 does not become unstable until the internal power supply voltage VDD reaches a predetermined voltage level.

  When internal power supply voltage VDD reaches a predetermined voltage level, transistor QN3 is turned on, so that the voltage at node ND3 becomes equal to ground voltage GND. Further, since the transistor QP3 is in a non-conductive state, the level shifter 31 outputs a value corresponding to the input control signal seqmode_on.

  When the control signal seqmode_on is at L level (GND), the transistor QN1 is turned on and the transistor QN2 is turned off. As a result, transistor QP1 is turned off and transistor QP2 is turned on, so that the voltage at node ND2 is equal to external power supply voltage VCC. As a result, an H level (VCC) signal Fhelatch is applied to the clock input terminal CLK of the D latch 32 of FIG.

  On the other hand, when the control signal seqmode_on is at H level (VDD), the transistor QN1 is turned off and the transistor QN2 is turned on. As a result, transistor QP1 is turned on and transistor QP2 is turned off, so that the voltage at node ND2 is equal to ground voltage GND. As a result, the L level (GND) signal Fhelatch is applied to the clock input terminal CLK of the D latch 32 of FIG.

  5 to 7 are timing charts showing the operation of the latch circuit 30 shown in FIG. Hereinafter, the operation of the latch circuit 30 shown in FIG. 3 will be described by summarizing the above description with reference to FIGS.

  FIG. 5 is a timing chart of the latch circuit 30 in cases other than data rewriting. 3 and 5, it is assumed that internal power supply voltage VDD is at the H level (VDD) in any time zone. Therefore, the monitoring signal VDDONL is also at the H level (VCC). Since data rewriting is not in progress, the control signal seqmode_on (VDD system) output from the P / E sequencer 21 is at the L level (GND).

  When the rewritable signal FHVED (or FHVEI) is at L level (GND) as in the time period from time t1 to time t2 in FIG. 5, the output signal Infhved (or Infhvei) of the latch circuit 30 is at L level (GND). Become. Further, when the rewritable signal FHVED (or FHVEI) is at the H level (VCC) as at times t3 to t4, the output signal Infhved (or Infhvei) of the latch circuit 30 is at the H level (VCC). That is, the latch circuit 30 outputs the logic level of the input signal as it is.

  FIG. 6 is a timing chart of the latch circuit 30 at the time of data rewriting. Referring to FIGS. 3 and 6, internal power supply voltage VDD is at H level (VDD) in any time period, and therefore monitor signal VDDONL is at H level (VCC). In addition, the reset signal RST (VCC system) is at L level (GND) in any time zone, and no forced reset is performed from the outside.

  At time t1 in FIG. 6, the rewritable signal FHVED (or FHVEI) is switched from L level to H level (VCC). In the time zone up to the next time t2, the control signal seqmode_on (VDD system) output from the P / E sequencer 21 is at the L level (GND). Therefore, the output signal Infhved (or Infhvei) of the latch circuit 30 is switched from the L level to the H level (VCC) at the time t1 according to the logic level of the input rewritable signal FHVED (or FHVEI).

  When the control signal seqmode_on (VDD system) is switched to the H level (VDD) at the next time t2, the latch circuit 30 holds the logic level (H level) of the rewritable signal FHVED (or FHVEI) at this time t2. To do. In the time period from this time t2 to the next time t3, the control signal seqmode_on (VDD system) output from the P / E sequencer 21 maintains the H level (VDD). Therefore, latch circuit 30 continues to output the held H level (VCC) signal until time t3.

  When the control signal seqmode_on (VDD system) returns to the L level (GND) at the next time t3, the latch circuit 30 outputs a signal having a logic level corresponding to the logic level of the input rewritable signal FHVED (or FHVEI). Output. From this time t3 to the next time t4, since the rewritable signal FHVED (or FHVEI) is at the H level, the output signal Infhved (or Infhvei) of the latch circuit 30 remains at the H level (VCC).

  At the next time t4, the rewritable signal FHVED (or FHVEI) returns to the L level (GND), so that the output signal Infhved (or Infhvei) of the latch circuit 30 also returns to the L level (GND) according to the change.

  FIG. 7 is a timing diagram of the latch circuit 30 when it is reset during rewriting. 3 and 7, it is assumed that internal power supply voltage VDD is at H level (VDD) in any time period, and therefore, monitoring signal VDDONL is at H level (VCC). In the case of FIG. 7, unlike the case of FIG. 6, the microcomputer 1 is forced from the outside at time t <b> 3 in the time period from time t <b> 2 to t <b> 4 when the control signal seqmode_on (VDD system) becomes H level (VDD). (The reset signal RST is switched to H level).

  At time t1 in FIG. 7, the rewritable signal FHVED (or FHVEI) is switched from the L level to the H level (VCC). In the time zone up to the next time t2, the control signal seqmode_on (VDD system) output from the P / E sequencer 21 is at the L level (GND). Therefore, the output signal Infhved (or Infhvei) of the latch circuit 30 is switched from the L level to the H level (VCC) at the time t1 according to the logic level of the input rewritable signal FHVED (or FHVEI).

  When the control signal seqmode_on (VDD system) is switched to the H level (VDD) at the next time t2, the latch circuit 30 holds the logic level (H level) of the rewritable signal FHVED (or FHVEI) at this time t2. To do. In the time period from time t2 to time t4, the control signal seqmode_on (VDD system) output from the P / E sequencer 21 is at the H level (VDD). Therefore, latch circuit 30 continues to output the held H level (VCC) signal until time t4.

  At time t3 between times t2 and t4, the reset signal RST switches to the H level, and the rewritable signal FHVED (or FHVEI) returns to the L level (GND). At this time, since the control signal seqmode_on (VDD system) remains at the H level (VDD), the output signal Infhved (or Infhvei) of the latch circuit 30 remains at the held H level (VCC).

  When the control signal seqmode_on (VDD system) returns to the L level (GND) at the next time t4, the latch circuit 30 outputs a signal having a logic level corresponding to the logic level of the input rewritable signal FHVED (or FHVEI). Output. Since the rewritable signal FHVED (or FHVEI) has already returned to the L level (GND) at the time t3, the output signal Infhved (or Infhvei) of the latch circuit 30 becomes the L level (GND) after the time t4. Become.

At the next time t5, the reset signal RST returns to the L level (GND).
[Summary]
FIG. 8 is a table showing logic levels of rewritable signals FHVED, FHVEI, and VHVEX corresponding to the operation state of the memory array. Hereinafter, the control method of the nonvolatile memory 4 by the rewritable signals FHVED, FHVEI, and VHVEX will be summarized with reference to FIGS.

  First, when the normal area 41D of the memory array 40D in the data area 10D is rewritten, the rewritable signal FHVED becomes H level (VCC). As a result, the internal power supply circuit 11, the power supply control signal generation unit 22, and the power supply SW control signal generation unit 23D for the power supply switch unit 14D are activated.

  Next, when the normal area 41I of the memory array 40I in the code area 10I is rewritten, the rewritable signal FHVEI becomes H level (VCC). As a result, the internal power supply circuit 11, the power supply control signal generation unit 22, and the power supply SW control signal generation unit 23I for the power supply switch unit 14I are activated.

  Next, when the special area 42I of the memory array 40I in the code area 10I is rewritten, the rewritable signals FHVEI and FHVEX are set to the H level (VCC). As a result, the internal power supply circuit 11, the power supply control signal generation unit 22, and the power supply SW control signal generation unit 23I for the power supply switch unit 14I are activated. Further, the memory cell in the special area 42I can be rewritten, for example, by selecting a cell block in the special area 42I.

  Next, when the special area 42D of the memory array 40D in the data area 10D is rewritten, the rewritable signals FHVED and FHVEX become the H level (VCC). As a result, the internal power supply circuit 11, the power supply control signal generation unit 22, and the power supply SW control signal generation unit 23D for the power supply switch unit 14D are activated. Further, the memory cell in the special area 42D can be rewritten, for example, by selecting a cell block in the special area 42D.

  On the other hand, the rewritable signal corresponding to the area where data is not being rewritten becomes L level (GND). As a result, erroneous data writing can be prevented in the case of power interruption or instantaneous power failure.

  As described above, according to the nonvolatile memory 4 of the first embodiment, in the case of power shutdown or instantaneous power failure by a simple method of using a plurality of rewritable signals FHVED, FHVEI, FHVEX corresponding to each area of the memory array Can reduce the possibility of erroneous data writing. Therefore, compared with the prior art, in the case of the nonvolatile memory 4 according to the first embodiment, the circuit configuration is not complicated and the circuit area is hardly increased.

  Further, by providing the latch circuits 30D and 30I that hold the logic states of the rewritable signals FHVED and FHVEI, even when the rewritable signals FHVED and FHVEI are reset during the data rewriting, the data rewriting can be normally terminated. it can.

[Modification 1]
FIG. 9 is a block diagram showing a configuration of a nonvolatile memory 104 as a modification of the nonvolatile memory 4 of FIG. The nonvolatile memory 104 in FIG. 9 is supplied with a rewritable signal FHVET dedicated to the test internal register 113 from the outside of the microcomputer 1.

  Specifically, the level shifter 112 provided in the data area 110D of FIG. 9 is further different from the level shifter 12 of FIG. 2 in that the level of the rewritable signal FHVET_VCC is converted to the VDD rewritable signal fhvet_vdd.

  Further, the internal register 113 of FIG. 9 is different from the internal register 13 of FIG. 2 in that only the rewritable signal fhvet_vdd is received instead of the rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd. The output of the internal register 113 is valid when the rewritable signal fhvet_vdd is in an activated state (H level). When the rewritable signal fhvet_vdd is in an inactive state (L level), the output of the internal register 113 is invalidated.

  Since the nonvolatile memory 104 of FIG. 9 is the same as the nonvolatile memory 4 of FIG. 2 in other points, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Modification 2]
FIG. 10 is a block diagram showing a configuration of a microcomputer 201 as a modification of the microcomputer 1 shown in FIG.

  The microcomputer 201 of FIG. 10 differs from the microcomputer 1 of FIG. 1 in that it further includes a register 9 (a signal generation circuit that generates a rewritable signal) that operates at the external power supply voltage VCC. The register 9 outputs rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC in the logic state according to the set data in the register to the nonvolatile memory 4. In the case of FIG. 1, the rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC are given from the outside of the microcomputer 1, whereas in the case of FIG. 10, the rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC are inside the microcomputer 201. Is generated.

  In FIG. 12, when the data stored in the nonvolatile memory 4 is rewritten, the data in the register 9 is set so that the rewritable signal corresponding to the area to be rewritten is activated (H level). Setting data of the register 9 is given from the outside of the microcomputer 201 via the interface circuit 7 and the data bus 8.

  According to the above configuration, it is not necessary to provide a dedicated external terminal for inputting the rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC. Therefore, the number of external terminals provided in the microcomputer 201 can be reduced as compared with the case of the microcomputer 1 in FIG. Since the other points of FIG. 10 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Embodiment 2>
FIG. 11 is a block diagram showing a configuration of microcomputer 301 according to the second embodiment of the present invention.

  A microcomputer 301 (semiconductor device) in FIG. 11 is different from the microcomputer 1 in FIG. 1 in that the power supply voltage VDD is supplied from the outside without including the internal power supply circuit 11 that generates the power supply voltage VDD. That is, the microcomputer 301 receives two external power supply voltages VDD and VCC for driving from the outside of the microcomputer 301.

  As shown in FIG. 11, the microcomputer 301 includes a CPU 2, a RAM 3, a nonvolatile memory 304, a peripheral circuit 5, an interface circuit 7, and a data bus 8 that connects these components to each other. The external power supply voltage VDD is used to operate most of these components. The external power supply voltage VCC is used to operate some analog circuits such as an A / D (Analog to Digital) converter included in the peripheral circuit 5 and the latch circuits 30D and 30I described in FIG. In the second embodiment, external power supply voltage VCC is higher than external power supply voltage VDD.

  The microcomputer 301 of FIG. 11 is further different from the microcomputer 1 of FIG. 1 in that it receives rewritable signals FHVED_EXVDD, FHVEI_EXVDD, and VHVEX_EXVDD from the outside in addition to the rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC. The rewritable signals FHVED_VCC, FHVEI_VCC, and VHVEX_VCC are VCC signals (H level: power supply voltage VCC, L level: ground voltage GND), and are signals output from an external circuit that operates at the power supply voltage VCC. On the other hand, the rewritable signals FHVED_EXVDD, FHVEI_EXVDD, and VHVEX_EXVDD are external VDD signals (H level: power supply voltage VDD, L level: ground voltage GND), and are signals output from an external circuit operating at the power supply voltage VDD. is there. In FIG. 11 and FIG. 12, EXVDD is added to the end of the reference symbol to indicate an external VDD signal.

  These rewritable signals are provided corresponding to a plurality of areas of the nonvolatile memory 304. Specifically, the rewritable signals FHVED_VCC and FHVED_EXVDD correspond to the data area 310D, and the rewritable signals FHVEI_VCC and FHVEI_EXVDD correspond to the code area 10I. Further, the rewritable signals FHVEX_VCC, FHVEX_EXVDD correspond to special areas provided in the memory cells of the data area 10D and the code area 10I.

  As described above, both the VCC-type rewritable signal and the external VDD-type rewritable signal correspond to each region. Each area is controlled to be in a rewritable state when both of the corresponding two rewritable signals are activated. As a result, even if one of the two external power supplies is shut off or an instantaneous power failure occurs, the rewritable signal of the other power supply system is maintained in the inactive state (L level). Thus, the possibility of erroneously rewriting data in the memory cell when returning from the power failure state can be reduced. A detailed control method of the nonvolatile memory 304 by the rewritable signal will be described with reference to FIG.

  In addition, the microcomputer 301 of FIG. 11 is provided with a terminal for receiving a reset signal RST for resetting the microcomputer 1 from the outside. The microcomputer 301 is also provided with a terminal for receiving a monitoring signal VDDONL that is activated when the voltage level of the external power supply voltage VDD reaches a predetermined voltage level.

  FIG. 12 is a block diagram showing a detailed configuration of the nonvolatile memory 304 of FIG. As shown in FIG. 12, the data area 310D of the nonvolatile memory 304 is different from the data area 10D of FIG. 2 in that latch circuits 330D and 330I, a level shifter 50, and AND circuits 51 to 55 are further provided. Hereinafter, these different points will be mainly described, and the same or corresponding parts as those in FIG. 2 may be denoted by the same reference numerals and the description thereof may not be repeated.

  First, the latch circuits 330D and 330I have a configuration similar to that of the latch circuit 30 of FIG. 3, but are different from the latch circuit 30 of FIG. 3 in that the level shifter 31 is not included. That is, in the case of the latch circuit 330D (or 330I) in FIG. 12, the external VDD rewritable signal FHVED_EXVDD (or FHVEI_EXVDD) is input to the input terminal D of the D latch 32. A signal obtained by inverting the control signal seqmode_on by the inverter IV4 is input to the clock input terminal CLK of the D latch 32. Here, as in the first embodiment, the control signal seqmode_on is output from the P / E sequencer 21 and is activated (H mode) during data rewriting (write mode, erase mode) of the memory array 40D or 40I. Level), and inactive (L level) when data is not rewritten. Inverter IV4 and D latch 32 in latch circuits 330D and 330I operate with external power supply voltage VDD instead of external power supply voltage VCC.

  With the above configuration, the latch circuit 330D (or 330I) holds the logic state of the rewritable signal FHVED_EXVDD (or FHVEI_EXVDD) when the control signal seqmode_on is switched to the activated state (H level), and the control signal seqmode_on The held logic state is output until is switched to the inactive state (L level). On the other hand, while the control signal seqmode_on is in an inactive state (L level), the latch circuit 330D outputs the logic state of the input rewritable signal FHVED_EXVDD (or FHVEI_EXVDD) as it is.

  The level shifter 50 performs level conversion (step-down) of the rewritable signals FHVED_VCC and FHVEI_VCC from the VCC system to the VDD system. The level shifter 50 can be configured by, for example, an inverter circuit that operates at the external power supply voltage VDD.

  All of the AND circuits 51 to 55 operate with the external power supply voltage VDD. The AND circuit 51 performs an AND operation on the rewritable signal FHVED_VCC level-converted to the VDD system by the level shifter 50 and the external VDD rewritable signal FHVED_EXVDD, and outputs the operation result to the internal power supply circuit 11. Similarly, the AND circuit 52 performs an AND operation on the rewritable signal FHVEI_VCC level-converted to the VDD system by the level shifter 50 and the external VDD rewritable signal FHVEI_EXVDD, and outputs the operation result to the internal power supply circuit 11.

  When at least one of the outputs of the AND circuits 51 and 52 is in an activated state (H level), the internal power supply circuit 11 operates in accordance with a control signal from the power supply control signal generation unit 22 in accordance with a high voltage (write voltage, erase voltage). Control voltage). On the other hand, internal power supply circuit 11 does not generate a high voltage when both outputs of AND circuits 51 and 52 are in an inactive state (L level). Here, the outputs of the AND circuits 51 and 52 are activated (H level) when the rewritable signals of both the VCC system and the external VDD system are activated (H level). Therefore, even if one of the external power supply voltages VCC and VDD recovers after a power failure, the logic state of the rewritable signal of the power supply that is in the power failure becomes indefinite. As long as the rewritable signal of the power supply system is at the L level, the internal power supply circuit 11 does not generate a high voltage. As a result, it is possible to prevent a high voltage from being erroneously applied to the memory cell.

  The AND circuit 53 performs an AND operation on the signal fhved_vdd obtained by level conversion of the output of the latch circuit 30D by the level shifter 12 and the output signal fhved_exvdd of the latch circuit 330D, and outputs the operation result as a rewritable signal fhved_and. The rewritable signal fhved_and output from the AND circuit 53 is input to the power SW control signal generator 23D, the test internal register 13, and the power control signal generator 22 in the data area 310D.

  The AND circuit 54 performs an AND operation on the signal fhvei_vdd in which the output of the latch circuit 30I is level-converted to the VDD system by the level shifter 12 and the output signal fhvei_exvdd of the latch circuit 330I, and outputs the operation result as a rewritable signal fhvei_and. The rewritable signal fhvei_and output from the AND circuit 54 is input to the power SW control signal generator 23I, the test internal register 13, and the power control signal generator 22 in the code area 10I.

  The AND circuit 55 performs an AND operation on the signal fhvex_vdd obtained by converting the level of the rewritable signal FHVEX_VCC into the VDD system by the level shifter 12 and the external VDD system rewritable signal FHVEX_VDD, and outputs the operation result as a rewritable signal fhvex_and. The rewritable signal fhvex_and output from the AND circuit 55 is input to the special areas 42D and 42I of the memory arrays 40D and 40I and the internal register 13 for testing.

  The rewritable signals fhved_and, fhvei_and, and fhvex_and are associated with the rewritable signals fhved_vdd, fhvei_vdd, and fhvex_vdd in the first embodiment, respectively.

  For example, control of power supply SW control signal generator 23D in data area 310D by rewritable signal fhved_and is the same as control of power supply SW control signal generator 23D by rewritable signal fhved_vdd in the first embodiment. That is, when the rewritable signal fhved_and is in the activated state (H level), the power switch control signal generating unit 23D turns on or off a predetermined switch of the power switch unit 14D according to a command from the P / E sequencer 21. Output a control signal such that On the other hand, when the rewritable signal fhved_and is in an inactive state (L level), the power SW control signal generator 23D switches the high voltage switch of the power switch 14D regardless of the command content of the P / E sequencer 21. A control signal is output so that is turned off.

  Therefore, the voltage supply control unit 20D configured by the power supply SW control signal generation unit 23D and the power supply switch unit 14D has the rewritable signals FHVED_VCC and FHVED_EXVDD supplied from the outside in an activated state (H level). In accordance with a command from the P / E sequencer 21, a high voltage (control voltage such as a write voltage and an erase voltage) is supplied from the internal power supply circuit 11 to the memory array 40D via the X decoder 15D. When at least one of the rewritable signals FHVED_VCC and FHVED_EXVDD is in an inactive state (L level), the voltage supply control unit 20D basically receives a command from the P / E sequencer 21 from the internal power supply circuit 11. A high voltage is not supplied to the memory array 40D. However, as an exception, when the memory array 40D is rewriting data, the voltage supply control unit 20D has a high voltage from the internal power supply circuit 11 to the memory array 40D until the data rewriting is completed due to the effect of the latch circuits 30D and 330D. Continue to supply

  Thus, since the two rewritable signals FHVED_VCC and FHVED_EXVDD of the VCC system and the external VDD system are used for control, even if one of the external power supply voltages VCC and VDD is interrupted, the data area 310D is restored when the power is restored from the power failure. It is possible to prevent a high voltage from being erroneously applied to the memory array 40D.

  Similarly, the control of power supply SW control signal generator 23I in code area 10I by rewritable signal fhvei_and is the same as the control of power supply SW control signal generator 23I by rewritable signal fhvei_vdd in the first embodiment. Also in this case, since the two rewritable signals FHVEI_VCC and FHVEI_EXVDD for the VCC system and the external VDD system are used for control, even if one of the external power supply voltages VCC and VDD fails, a code is returned when the power supply is restored from the power failure state. It is possible to prevent a high voltage from being erroneously applied to the memory array 40I in the region 10I.

  Similarly, also in the second embodiment, the power supply control signal generating unit 22 is activated when one of the rewritable signals fhved_and and fhvei_and is in the activated state (H level). The test internal register 13 is activated when the rewritable signals fhved_and, fhvei_and, and fhvex_and are all in an activated state (H level). The special areas 42D and 42I of the memory arrays 40D and 40I are activated when the rewritable signal fhvex_and is activated. Here, in order for each of the rewritable signals fhved_and, fhvei_and, and fhvex_and to be activated, both the VCC-based rewritable signal and the external VDD-based rewritable signal need to be activated (H level). There is. Therefore, even if one of the external power supply voltages VCC and VDD fails, it is possible to prevent a high voltage from being erroneously applied to the memory arrays 40D and 40I when returning from the power failure state.

  Each embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 201, 301 Microcomputer, 2 CPU, 4, 104, 304 Non-volatile memory, 6 power supply circuit, 10I code area, 10D, 110D, 310D data area, 11 internal power supply circuit (boost circuit), 12, 112 level shifter, 13, 113 Internal register, 14D, 14I Power switch unit, 15D, 15I X decoder, 20D, 20I Voltage supply control unit, 21 P / E sequencer, 22 Power supply control signal generator (for internal power supply circuit 11), 23D Power supply SW Control signal generator (for power switch unit 14D), 23I power SW control signal generator (for power switch unit 14I), 30D, 30I latch circuit, 31 level shifter, 32D latch, 40D, 40I memory array, 41D, 41I Area, 42D, 42I special area, F VED_VCC, FHVEI_VCC, FHVEX_VCC, FHVET_VCC rewritable signal (VCC system), fhved_vdd, fhvei_vdd, fhvex_vdd, fhvet_vdd rewritable signal (VDD system), FHVED_EXVD Voltage.

Claims (11)

First and second memory arrays in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A voltage generation circuit for generating a rewrite voltage necessary for data rewriting of each of the memory cells;
A rewriting command unit that operates in a first power supply voltage, directing the data rewriting of the first and second memory arrays,
When a first rewritable signal that is activated when data is rewritten to the first memory array and deactivated when data is rewritten to the second memory array is in an activated state, the command of the rewrite command unit is followed. performed supply to the first memory array of the writing voltage generated by the voltage generating circuit, the first rewritable signal in the case of non-activated state, regardless of the instruction of the rewrite command unit A first voltage supply control unit configured to cut off supply of the rewrite voltage generated by the voltage generation circuit to the first memory array ;
When a second rewritable signal that is activated when data is rewritten to the second memory array and deactivated when data is rewritten to the first memory array is in an activated state, the command of the rewrite command unit is followed. performed supply to the second memory array of the writing voltage generated by the voltage generating circuit, said second rewritable signal in the case of non-activated state, regardless of the instruction of the rewrite command unit A second voltage supply control unit that cuts off supply of the rewrite voltage generated by the voltage generation circuit to the second memory array ;
The semiconductor device, wherein the first rewritable signal and the second rewritable signal are driven by a second power supply voltage different from the first power supply voltage .   The semiconductor device according to claim 1, wherein the first and second voltage supply control units are operated by the first power supply voltage. The semiconductor device further includes a power supply circuit that receives the second power supply voltage from outside and generates the first power supply voltage from the second power supply voltage,
2. The semiconductor device according to claim 1, wherein the first and second rewritable signals are signals input to the semiconductor device from a circuit outside the semiconductor device that operates at the second power supply voltage. The semiconductor device includes:
A power supply circuit that receives the second power supply voltage from outside and generates the first power supply voltage from the second power supply voltage;
Operated by the previous SL second power supply voltage, further comprising a signal generating circuit for generating the first and second rewritable signal based on a command from outside, the semiconductor device according to claim 1. The voltage generation circuit can generate the rewritable voltage when at least one of the first and second rewritable signals is activated,
5. The semiconductor device according to claim 3, wherein the voltage generation circuit stops generating the rewrite voltage when both the first and second rewritable signals are inactive. The semiconductor device includes:
When the first rewritable signal is received and the first memory array is not in the middle of data rewriting, a signal having the same logical state as the logical state of the first rewritable signal is output, and the first memory array Is being rewritten, the logic state of the first rewritable signal at the time when the first memory array starts data rewriting is held until the end of data rewriting, and the signal of the held logic state is A first latch circuit for outputting;
When the second rewritable signal is received and the second memory array is not rewriting data, a signal having the same logical state as the logical state of the second rewritable signal is output, and the second memory array When the data is being rewritten, the logic state of the second rewritable signal at the time when the second memory array starts data rewriting is held until the end of data rewriting, and the signal of the held logic state is A second latch circuit for outputting,
The first voltage supply control unit includes the first memory array of the rewrite voltage generated by the voltage generation circuit in accordance with a command of the rewrite command unit when an output of the first latch circuit is in an activated state. performed supply to said first of said first memory array of the rewriting voltage output is generated by the voltage generation circuit irrespective of the command of the rewrite command unit when the inactive mode the latch circuit Shut off the supply to
The second voltage supply control unit is configured to control the second memory array of the rewrite voltage generated by the voltage generation circuit according to a command of the rewrite command unit when an output of the second latch circuit is in an activated state. performed supply to said second memory array of the second of the rewriting voltage output of the latch circuit is generated by the voltage generation circuit irrespective of the command of the rewrite command section for non-activated state The semiconductor device according to claim 2, wherein supply to the device is cut off .   The semiconductor device according to claim 6, wherein the first and second latch circuits operate with the second power supply voltage. The semiconductor device has the first and second memory arrays when at least one of the first and second rewritable signals is activated and the third rewritable signal is activated. A test control unit for instructing the voltage generation circuit to generate a test voltage necessary for the test of
The semiconductor device according to claim 6, wherein the voltage generation circuit further generates the test voltage in accordance with a command from the test control unit. The semiconductor device is configured to instruct the voltage generation circuit to generate a test voltage necessary for testing the first and second memory arrays when the third rewritable signal is in an activated state. Further comprising
The semiconductor device according to claim 6, wherein the voltage generation circuit further generates the test voltage in accordance with a command from the test control unit.   The semiconductor device according to claim 8, wherein the test control unit does not instruct the voltage generation circuit to generate the test voltage when the third rewritable signal is in an inactive state.   The semiconductor device according to claim 1, wherein the first memory array is a data area, and the second memory array is a code area.

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