CN113724766B - Semiconductor memory device and flash memory operation method - Google Patents
Semiconductor memory device and flash memory operation method Download PDFInfo
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- CN113724766B CN113724766B CN202010456377.3A CN202010456377A CN113724766B CN 113724766 B CN113724766 B CN 113724766B CN 202010456377 A CN202010456377 A CN 202010456377A CN 113724766 B CN113724766 B CN 113724766B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000011084 recovery Methods 0.000 claims abstract description 29
- 230000002093 peripheral effect Effects 0.000 claims description 31
- 230000009191 jumping Effects 0.000 claims description 2
- 230000007704 transition Effects 0.000 description 15
- 230000004044 response Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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Abstract
The invention provides a semiconductor memory device and an operation method of a flash memory, which can shorten the recovery time from a deep power saving mode without a special command for releasing the deep power saving mode. The flash memory of the present invention comprises: a standard command I/F circuit and a DPD controller operated by an external power supply voltage; a voltage supply node that supplies power from an external power supply voltage via a first current path; a voltage supply node that supplies power from an external power supply voltage via a second current path; an internal circuit group connected to the voltage supply node; and a charge pump circuit connected to the voltage supply node. When the DPD mode is released, the charge pump circuit is enabled, and then the internal circuit group is enabled.
Description
Technical Field
The present invention relates to a semiconductor memory device such as a flash memory and a method thereof, and more particularly, to an operation in a standby mode or a deep power saving mode.
Background
A NAND flash memory (NAND) can be read out or programmed (program) in units of pages and erased in units of blocks. The flash memory shown in patent document 1 discloses the following technology, namely: in a standby mode (standby-by mode) and a normal operation mode, different power supply voltages are supplied to the page buffer/readout circuit, thereby reducing power consumption in the standby mode.
[ Prior Art literature ]
[ patent literature ]
[ patent document 1] Japanese patent laid-open No. 2006-252748
Disclosure of Invention
[ problem to be solved by the invention ]
Flash memory has an active mode that reads, programs, erases, etc. in response to commands from a user, and a standby mode that accepts commands from a user. In the standby mode, the operation of the internal circuit is restricted so that the power consumption becomes equal to or less than a predetermined level, but when a command is input from a user, the command must be responded immediately. Therefore, even in the standby mode, an off-leakage current (i.e., an off-leakage current) is generated in a volatile circuit such as a logic circuit or a register (register) and increases with a reduction in the size of the element, and when an internal power supply voltage is used, the internal power supply voltage detection circuit must be operated, and some power is consumed. That is, it is difficult to reduce the consumption current in the standby mode.
In order to further reduce power consumption in the standby mode, a deep power-down mode (hereinafter, referred to as DPD mode) is mounted depending on the flash memory. In the DPD mode, power supply to the inside of a part of active internal circuits for standby mode is stopped, and the current leakage is reduced. The DPD mode enters the mode, for example, by a DPD start command, and is restored from the mode by a DPD release command. In the recovery from the DPD mode, although a certain time is required to normally operate the turned-off circuit, there is an advantage in that the power consumption can be greatly reduced.
Fig. 1A shows an example of an operation waveform when a NAND flash memory having a serial peripheral interface (Serial Peripheral interface, SPI) function is shifted to a DPD mode. In the standby mode, the chip select signal CS is set to a low level to select the flash memory, and during this period, a dpd command is input from the data input terminal DI in synchronization with the clock signal (B9 h). The flash memory is at a time T when a certain period tDP has elapsed from the input of the DPD command DPD The control circuit jumps to the DPD mode to block the internal supply voltage to the specific internal circuit. Time T DPD In the previous period, the standby mode current is consumed, time T DPD In the subsequent period, the DPD mode current is consumed.
Fig. 1B shows an example of an operation waveform at the time of recovering from the DPD mode. In the standby mode, the chip select signal/CS is set to a low level to select the flash memory, and a DPD release command for releasing the DPD mode is input from the data input terminal DI in synchronization with the clock signal during this period (ABh). The flash memory supplies power to the turned-off internal circuit during tRES from the time when the DPD release command is input, and at time T ST And restoring the internal circuit to a normal operation state. At time T ST Previously, the current of the DPD mode was consumed at time T ST Thereafter, consumeCurrent in standby mode.
Fig. 2 is an internal block diagram of a NAND type flash memory supporting DPD mode. The flash memory 10 includes a DPD controller 20, a memory cell array (memory cell array) 30, a row decoder 40, a page buffer/readout circuit 50, a peripheral circuit 60, a high voltage circuit 70, and the like. The flash memory 10 is supplied with an external power supply voltage (e.g., 3.3V) VCC, and the DPD controller 20 operates directly using the external power supply voltage VCC. A P-channel metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) transistor P is connected between the external power supply voltage VCC and the internal circuit, and a DPD enable signal DPDEN is applied to the gate of the transistor P. In the active mode and standby mode, DPD controller 20 generates a DPD enable signal DPDEN at L level to turn on transistor P. Thus, the internal voltage VDD is supplied to each internal circuit via the voltage supply node INTVDD. In the DPD mode, the DPD controller 20 generates a DPD enable signal DPDEN at an H level to turn the transistor P off. Thereby, the supply of the external power supply voltage VCC is stopped, and the operation of the internal circuit is stopped.
When the DPD mode is released, as shown in fig. 1B, the user inputs a DPD release command from the outside (ABh). The DPD controller 20 transitions the DPD enable signal DPDEN to L level in response to input of the DPD release command, turns on the transistor P, and starts supplying power from the external power supply voltage VCC to the internal circuit. Thus, the internal circuit is restored to an operable state after the period tRES.
As described above, in the conventional flash memory, in order to use the DPD mode, the user must input not only the DPD command but also the DPD release command, and the DPD mode cannot be used in the flash memory controller which does not support the DPD command and the DPD release command. Further, when the DPD mode is released and the power from the external power supply voltage VCC is supplied to the voltage supply node INTVDD, if the load capacitance of the internal circuit is large, the time tRES until the voltage supply node INTVDD reaches the voltage at which the internal circuit can operate becomes long.
The present invention solves the above-described conventional problems, and an object of the present invention is to provide a semiconductor memory device capable of shortening a restoration time from a deep power saving mode without requiring a dedicated command for canceling the deep power saving mode.
[ means of solving the problems ]
The operation method of the flash memory comprises the following steps: a step of jumping to a deep power saving mode that blocks power supply from a power supply source to an internal circuit; a step of releasing the deep power saving mode when a standard command including read, program or erase is inputted; and a step of executing the standard command after releasing the deep power saving mode, the step of releasing supplying power from the power supply source to at least a first circuit portion and a second circuit portion of the internal circuit, respectively.
In one embodiment of the flash memory of the present invention, the step of releasing further supplies a first enable signal for making the first circuit portion operable to the first circuit portion, and supplies a second enable signal for making the second circuit portion operable to the second circuit portion after supplying the first enable signal. In one embodiment of the flash memory of the present invention, the step of performing uses the first circuit portion in a first processing sequence and uses the second circuit portion in a second processing sequence subsequent to the first processing sequence. In one embodiment of the flash memory of the present invention, the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than recovery time for enabling the entire internal circuit to be in an operational state. In one embodiment of the flash memory of the present invention, the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion. In one embodiment of the flash memory of the present invention, the first circuit portion includes a charge pump circuit, the second circuit portion includes a peripheral circuit of the memory cell array, and a time required for the charge pump to generate the boosted voltage is shorter than a difference between the second recovery time and the first recovery time. In one embodiment of the flash memory of the present invention, the deep power saving mode jumps from the standby mode when the standby mode continues for a certain time.
The semiconductor memory device of the present invention includes: an internal circuit including at least a first circuit portion and a second circuit portion; a jump member that jumps to a deep power saving mode that blocks power supply from a power supply source to the first circuit portion and the second circuit portion; a releasing section that releases the deep power saving mode when a standard command including reading, programming, or erasing is input; and an execution unit that executes the standard command after releasing the deep power saving mode, the release unit including: a first current path that supplies electric power from the electric power supply source to the first circuit portion; and a second current path that supplies electric power from the electric power supply source to the second circuit portion.
In one embodiment of the semiconductor memory device of the present invention, the canceling member includes: a first supply section that supplies a first enable signal for making the first circuit section operable to the first circuit section; and a second supply section that supplies a second enable signal for making the second circuit operable to the second circuit section after the first enable signal is supplied. In one embodiment of the semiconductor memory device of the present invention, the executing means uses the first circuit portion in a first processing sequence and uses the second circuit portion in a second processing sequence subsequent to the first processing sequence. In one embodiment of the semiconductor memory device of the present invention, the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than the recovery time for bringing the first circuit portion and the second circuit portion into an operable state. In one embodiment of the semiconductor memory device of the present invention, a load capacitance of the first circuit portion is smaller than a load capacitance of the second circuit portion. In one embodiment of the semiconductor memory device of the present invention, the first circuit portion includes a charge pump circuit, the second circuit portion includes a peripheral circuit of the memory cell array, and a time required for the charge pump to generate the boosted voltage is shorter than a difference between the second recovery time and the first recovery time. In one embodiment of the semiconductor memory device of the present invention, the canceling means includes a first transistor and a second transistor in the first current path and the second current path, and the canceling means controls conduction or non-conduction of the first transistor and the second transistor. In one embodiment of the semiconductor memory device of the present invention, the semiconductor memory device is a flash memory.
[ Effect of the invention ]
According to the present invention, the deep power saving mode can be released in response to the input of the standard command without a dedicated command for releasing the deep power saving mode. Further, when the deep power saving mode is released, since the electric power is supplied from the electric power supply source to the first circuit portion and the second circuit portion, the time for bringing the first circuit portion or the second circuit portion into an operable state can be shortened as compared with the case where the electric power is supplied to the first circuit portion and the second circuit portion in common, and as a result, the recovery time from the deep power saving mode can be minimized.
Drawings
Fig. 1A is a diagram showing an example of an operation waveform when a conventional flash memory jumps to a DPD mode;
fig. 1B is a diagram showing an example of an operation waveform when a DPD mode is released in a conventional flash memory;
fig. 2 is a diagram showing an internal configuration of a conventional flash memory;
fig. 3 is a diagram showing an internal configuration of a flash memory according to an embodiment of the present invention;
fig. 4 is a diagram showing operation waveforms of each section when the DPD mode of the embodiment of the present invention is released.
[ description of symbols ]
10. 100: flash memory
20. 120: DPD controller
30. 130: memory cell array
40: line decoder
50: page buffer/read-out circuit
60: peripheral circuit
70: high voltage circuit
110: standard command I/F circuit
140: row decoder (peripheral circuit)
150: page buffer/read-out circuit (peripheral circuit)
160: peripheral circuit
170: high voltage circuit (peripheral circuit)
180: charge pump circuit
ABh: DPD release command
B9h: DPD command
CPUEN: CPU enable signal
DEC: decoding result
DI: data input terminal
DPDEN: DPD Enable Signal
INTVDD, INTVDDCP: voltage supply node
P: PMOS transistor
P1, P2: transistor with a high-voltage power supply
PUMPEN: pump enable signal
T DPD 、T ST : time of day
t1, t2A, t3: time of day
tDP: for a certain period of time
tRES: period, time, recovery time
VCC: external supply voltage
VWWPUMP: pump voltage
/CS: chip select signal
Detailed Description
The semiconductor memory device of the present invention is Not particularly limited, and is implemented in, for example, NAND-type OR NOR (Not OR NOR) -type flash memory OR the like.
Examples (example)
Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Fig. 3 is a diagram showing a schematic internal structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a standard command interface (I/F) circuit 110 for receiving standard commands, a DPD controller 120 for controlling switching to the DPD mode, releasing the DPD mode, and other internal circuits such as a memory cell array 130, a row decoder 140, a page buffer/read circuit 150, a peripheral circuit 160, a high voltage circuit 170, and a charge pump circuit 180.
The flash memory 100 of the present embodiment can operate in a plurality of power consumption modes. The active mode performs standard command (e.g., read, program, erase) operations without limiting power consumption and with full specification (full specification). The standby mode is a mode in which, when the active mode is not the active mode, the internal circuit is operated in accordance with a predetermined power consumption requirement, and the operation is performed in response to an input of a standard command or the like. In the standby mode, for example, a charge pump (charge pump) of a high-voltage circuit is stopped, or an internal supply voltage is lowered. In order to further reduce the power consumption in the standby mode, the DPD mode blocks the power supply to the specific circuit in the standby mode.
The standard command I/F circuit 110 and DPD controller 120 operate directly using the external power supply voltage VCC (e.g., 3.3V), i.e., can operate in standby mode and DPD mode. The standard command I/F circuit 110 is an interface circuit for receiving a standard command prepared in advance for standard operation of the flash memory from the outside. Standard commands are for example commands for read out, programming, erasing etc. The standard command I/F circuit 110 includes a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic device for decoding an input standard command, and the decoding result DEC thereof is supplied to the DPD controller 120 and the peripheral circuit 160 (including a controller or a state machine (state machine) or the like for controlling the operation of the standard command).
The DPD controller 120 controls the transition from the standby mode to the DPD mode and the release of the DPD mode. The PMOS transistor P1 is connected to a first current path between the external power supply voltage VCC and the voltage supply node INTVDD, and the PMOS transistor P2 is connected to a second current path between the external power supply voltage VCC and the voltage supply node INTVDDCP. The row decoder 140, the page buffer/read circuit 150, the peripheral circuit 160, and the high voltage circuit 170 are connected to the voltage supply node INTVDD, and the charge pump circuit 180 is connected to the voltage supply node INTVDDCP.
The DPD enable signal DPDEN from the DPD controller 120 is commonly applied to the gates of the transistors P1 and P2. In the active mode and the standby mode, DPD controller 120 generates an L-level DPD enable signal DPDEN to turn on transistors P1 and P2, thereby supplying power from external power supply voltage VCC to voltage supply node INTVDD via the first current path and to voltage supply node INTVDDCP via the second current path. In the DPD mode, the DPD controller 120 transitions the DPD enable signal DPDEN to the H level, and turns off the transistors P1 and P2 of the first and second current paths to block the supply of power from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP.
The method of switching from standby mode to DPD mode is not particularly limited, and in one embodiment, DPD controller 120 does not input a command for switching to DPD mode from the user, but automatically switches to DPD mode in response to a signal from peripheral circuit 160 (including a controller that controls the operation of the flash memory, etc.). For example, when a signal indicating a transition to the standby mode is supplied from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures a time from a point of time indicating a transition to the standby mode, and transitions to the DPD mode after the duration of the standby mode exceeds a predetermined time, and the DPD enable signal DPDEN transitions to the H level, thereby blocking the supply of electric power from the external power supply voltage VCC. In addition, in another embodiment, the DPD controller 120 may also skip to the DPD mode in response to input from the user of a command to skip to the DPD mode.
In the conventional flash memory, a dedicated command for releasing the DPD mode needs to be externally input, but this embodiment has a function of automatically releasing the DPD mode without inputting such a dedicated command. If the standard command I/F circuit 110 inputs a standard command in the DPD mode, the DPD controller 120 releases the DPD mode in response to the input of the standard command. The inputted standard command is seamlessly executed after the lapse of time required for restoration from the DPD mode.
The DPD controller 120 also generates a pump enable signal PUMPEN for enabling the charge pump circuit 180 to operate and a CPU enable signal CPUEN for enabling a central processing unit (Central Processing Unit, CPU) included in the controller of the peripheral circuit 160 to operate, when the DPD mode is released, that is, when power is supplied from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP, respectively, via the first current path and the second current path, respectively. The pump enable signal pummen is supplied to the charge pump circuit 180, and the cpu enable signal CPUEN is supplied to the peripheral circuit 160. As will be described later in detail, the DPD controller 120 transitions the pump enable signal PUMPEN to H level when the voltage supply node INTVDDCP reaches the target voltage from the point in time when the DPD mode is released, and enables the charge pump circuit 180, and then transitions the CPU enable signal CPUEN to H level when the voltage supply node INTVDD reaches the target voltage, and enables the controller of the peripheral circuit 160.
The DPD controller 120 of the present embodiment may be configured using hardware and/or software, and may include, for example, a microcomputer, a state machine, a logic device, etc.
The memory cell array 130 includes a plurality of blocks, each including a plurality of NAND strings (strings). The NAND strings may be formed two-dimensionally on the substrate, or may be formed three-dimensionally in the vertical direction from the main surface of the substrate. In addition, the memory cell may store binary data or multi-valued data.
The peripheral circuit 160 includes, for example, the following: a controller or state machine that controls the operation of the flash memory 100 based on standard commands or the like received by the standard command I/F circuit 110; or error checking and correcting (Error Checking and Correction, ECC) circuit, column selecting circuit, and performing error detection and correction of data. The high voltage circuit 170 receives the voltage boosted by the charge pump circuit 180, and generates high voltages (e.g., a program pulse voltage, an erase pulse voltage, a read path voltage, etc.) necessary for the read, program, and erase operations. The flash memory 100 may be equipped with SPI (Serial Peripheral Interface), and recognizes an input command, address, and data in synchronization with a serial clock signal in place of a control signal (e.g., an address latch is permitted, and a command latch is permitted) in the SPI.
Next, the operation of canceling the DPD mode of the flash memory of the present embodiment will be described. Fig. 4 is a diagram showing operation waveforms of each section when the DPD mode is released. When the flash memory 100 is in the DPD mode, the DPD enable signal DPDEN is at the H level, the power supply from the external power supply voltage VCC is blocked, and the voltage supply node INTVDD, the voltage supply node INTVDDCP is at the Ground (GND) level. In the DPD mode, the standard command I/F circuit 110 and the DPD controller 120 are in a state of being operable by power from the external power supply voltage VCC.
If a standard command is input to the standard command I/F circuit 110, the standard command I/F circuit 110 supplies the decoding result DEC of the standard command to the DPD controller 120 and the peripheral circuit 160. However, at this point in time, peripheral circuit 160 is not in an operational state.
When the DPD controller 120 receives the decoding result DEC from the standard command I/F command 110 in the DPD mode, the DPD mode is automatically released. That is, at time t1, DPD controller 120 transitions DPD enable signal DPDEN from the H level to the L level, and turns on transistors P1 and P2. Thus, power is supplied from the external power supply voltage VCC via the first current path to the voltage supply node INTVDD, and power is supplied from the external power supply voltage VCC via the second current path to the voltage supply node INTVDDCP. That is, the voltage supply node INTVDD and the voltage supply node INTVDCP are each charged with power from the external power supply voltage VCC, respectively.
The row decoder 140, the page buffer/read circuit 150, the peripheral circuit 160, and the high voltage circuit 170 are connected to the voltage supply node INTVDD, and the charge pump circuit 180 is connected to the voltage supply node INTVDDCP. The peripheral circuit groups 140 to 170 connected to the voltage supply node INTVDD have a larger number of transistors and a larger wiring capacitance (a larger load capacitance) than the charge pump circuit 180 connected to the voltage supply node INTVDDCP, and thus the voltage supply node INTVDD rises to the target voltage more slowly than the voltage supply node INTVDDCP. Therefore, the voltage supply node INTVDDCP reaches the target voltage at time t2 after tRESCP from time t1, as shown in fig. 4, but reaches the target voltage at time t3 after tRESVDD from time t1 (tRESCP < tRESVDD). The target voltage of the voltage supply node INTVDDCP is a voltage at which the charge pump circuit 180 becomes operable, and the target voltage of the voltage supply node INTVDD is a voltage at which the CPU of the peripheral circuit 160 becomes operable.
The DPD controller 120 transitions the pump enable signal PUMPEN from the L level to the H level at time t2 when the charge pump circuit 180 becomes operable. The charge pump circuit 180 starts the pump operation at time t2 in response to the pump enable signal pummen, and generates a desired pump voltage VWWPUMP at time t2A after tPUMP from time t 2. In this embodiment, the charge pump circuit 180 can operate after the voltage supply node INTVDDCP reaches the target voltage, without waiting for the voltage supply node INTVDD to reach the target voltage.
Further, at time t3 when peripheral circuit 160 is in an operable state, DPD controller 120 transitions CPU enable signal CPUEN from the L level to the H level. The Controller (CPU) of the peripheral circuit 160 starts the operation of the standard command at time t3 in response to the CPU enable signal CPUEN. At time t3 when the two voltage supply nodes INTVDD, INTVDDCP reach the target voltage, the recovery time tRES from the DPD mode ends. If tPUMP < trevdd-trecp, the pump voltage VWWPUMP is already generated at the time point when the operation of the standard command is started, and thus the high voltage generation circuit 170 can immediately supply the high voltage required for the operation to the page buffer/readout circuit 150 or the row decoder 140, or the like. In contrast, even if the relationship of tPUMP > trevdd-tresscp is adopted, the supply pump voltage VWWPUMP can be quickened as compared with the case where the operation of the charge pump circuit 180 is not advanced.
The control method for the time t2 and the time t3 by the DPD controller 120 is not particularly limited, and for example, the DPD controller 120 may measure the time from the time t1 by using a built-in timer and transition the enable signal PUMPEN and the enable signal CPUEN to the H level when the time reaches tRESCP, tRESVDD. In another embodiment, a detection circuit may be provided to detect the voltages of the voltage supply node INTVDDCP and the voltage supply node INTVDD, and the DPD controller 120 may transition the enable signal PUMPEN and the enable signal CPUEN to the H level when the target voltage of each voltage supply node is detected by the detection circuit.
As a specific example of operation, when a read, program, or erase command is input to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 transitions the DPD enable signal DPDEN to L level, turns on the transistors P1 and P2, starts power supply from the external power supply voltage VCC, and releases the DPD mode. The DPD controller 120 operates the charge pump circuit 180 at time t2 after tresscp from time t1 until the voltages at the voltage supply nodes INTVDD and INTVDDCP are restored, generates the pump voltage VWWPUMP by the charge pump circuit 180 from time t1 until time t3 after trevdd, and starts executing the command at time t 3. The boost voltage required for sensing, programming or erasing can be utilized immediately after the command is executed.
As described above, according to the present embodiment, since the DPD mode is automatically released in response to the input of the standard command, it is not necessary to input a dedicated command for releasing the DPD mode, and the DPD mode can be released even in a flash memory that does not support the release command of the DPD mode.
Further, when the internal circuit after shut down (shutdown) is restored from the DPD mode, instead of supplying power to the voltage supply node INTVDD connected to the entire internal circuit as shown in fig. 2, power is supplied separately to the voltage supply nodes INTVDD connected to the peripheral circuit groups 140 to 170 and the voltage supply node INTVDDCP connected to the charge pump circuit 180, so that the operation of the charge pump circuit 180 is advanced, and thus, the time tRES for restoring the internal circuit to an operable state can be shortened as compared with the conventional one (fig. 1B).
In the above-described embodiment, the internal circuit to which the power supply is blocked by the DPD mode is divided into the peripheral circuit groups 140 to 170 and the charge pump circuit 180 to restore from the DPD mode, but the present invention is not necessarily limited to this division. The internal circuit for advancing the operation in the recovery from the DPD mode may not necessarily include a charge pump circuit, but may be another circuit. Further, the circuit recovered from the internal circuit may be divided into three or more circuit portions, and power may be supplied to each circuit portion via a different current path.
In a certain embodiment, in the case of resetting the first circuit portion and the second circuit portion from the DPD mode, the selection of the first circuit portion and the second circuit portion may also correspond to the processing order when executing the standard command. That is, the first processing sequence when executing the standard command uses the first circuit portion, and the second processing sequence uses the second circuit portion, so that the first circuit portion becomes an operable state earlier than the second circuit portion. When the load capacitance of the first circuit portion is smaller than that of the second circuit portion, the first circuit portion starts to operate in restoration of the second circuit portion, and the restoration time is shortened more effectively. For example, in the case where the program operation includes both of the program verify and the program verify operation is performed first, only the circuit portion related to the verify connected to the voltage supply node INTVDDx is allowed to be operated first, and in the verify operation, the voltage supply node INTVDDy connected to the circuit portion for programming reaches the target voltage.
In addition, in the embodiment, the reading, programming, and erasing are exemplified as the standard commands, but the standard commands may include, in addition to these, status Read (Status Read) or Identifier (ID) Read, etc. Status Read is a command for reading whether the flash memory is in ready (ready) state, whether it is in write protection mode, whether it is in program/erase operation, and ID Read is a command recognized by a Read manufacturer or product.
In the above embodiment, the example in which the voltage supply nodes INTVDD and INTVDDCP are supplied with power from the external power supply voltage VCC has been shown, but this is an example, and the voltage supply nodes INTVDD and INTVDDCP may be supplied with power from other internal power supply voltages instead of being directly supplied from the external power supply voltage VCC.
The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.
Claims (14)
1. A method of operating a flash memory, comprising:
a step of jumping to a deep power saving mode that blocks power supply from a power supply source to an internal circuit;
a step of releasing the deep power saving mode when a standard command including read, program or erase is inputted; and
after releasing the deep power saving mode, executing the standard command,
the step of releasing supplies power from the power supply source to at least a first circuit portion and a second circuit portion of the internal circuit each respectively,
wherein the step of releasing further supplies a first enable signal for enabling the first circuit portion to operate to the first circuit portion, supplies a second enable signal for enabling the second circuit portion to operate to the second circuit portion after the first enable signal is supplied, and
wherein the first circuit portion includes a charge pump circuit and the second circuit portion includes peripheral circuitry of a memory cell array.
2. The method of claim 1, wherein,
the step of performing uses the first circuit portion in a first processing sequence and the second circuit portion in a second processing sequence subsequent to the first processing sequence.
3. The method for operating a flash memory according to claim 1 or 2, wherein,
the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than the recovery time for enabling the entire internal circuit to be in an operable state.
4. The method for operating a flash memory according to claim 1 or 2, wherein,
the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion.
5. The method for operating a flash memory of claim 3, wherein,
the charge pump generates a boosted voltage for a shorter time than the difference between the second recovery time and the first recovery time.
6. The method of claim 1, wherein,
the deep power saving mode jumps from the standby mode when the standby mode continues for a certain time.
7. A semiconductor memory device comprising:
an internal circuit including at least a first circuit portion and a second circuit portion;
a jump member that jumps to a deep power saving mode that blocks power supply from a power supply source to the first circuit portion and the second circuit portion;
a releasing section that releases the deep power saving mode when a standard command including reading, programming, or erasing is input; and
an execution unit configured to execute the standard command after the deep power saving mode is released,
the release member includes: a first current path that supplies electric power from the electric power supply source to the first circuit portion; and a second current path for supplying power from the power supply source to the second circuit portion,
wherein the release member includes: a first supply section that supplies a first enable signal for enabling operation of the first circuit section to the first circuit section; and a second supply section that supplies a second enable signal for enabling operation of the second circuit to the second circuit section after supplying the first enable signal, and
wherein the first circuit portion includes a charge pump circuit and the second circuit portion includes peripheral circuitry of a memory cell array.
8. The semiconductor memory device according to claim 7, wherein,
the execution unit uses the first circuit portion in a first processing sequence and uses the second circuit portion in a second processing sequence subsequent to the first processing sequence.
9. The semiconductor memory device according to claim 7, wherein,
the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than recovery times for bringing the first circuit portion and the second circuit portion into an operable state.
10. The semiconductor memory device according to claim 7, wherein,
the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than recovery time for bringing the first circuit portion and the second circuit portion into an operable state.
11. The semiconductor memory device according to claim 7 or 8, wherein,
the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion.
12. The semiconductor memory device according to claim 9 or 10, wherein,
the charge pump generates a boosted voltage for a shorter time than the difference between the second recovery time and the first recovery time.
13. The semiconductor memory device according to claim 7, wherein,
the release component comprises a first transistor and a second transistor in the first current path and the second current path, and the release component controls conduction or non-conduction of the first transistor and the second transistor.
14. The semiconductor memory device according to claim 7 or 8, wherein,
the semiconductor memory device is a flash memory.
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