CN113724766A - Semiconductor memory device and method for operating flash memory - Google Patents
Semiconductor memory device and method for operating flash memory Download PDFInfo
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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Abstract
The invention provides a semiconductor memory device and a method for operating a flash memory, which can shorten the recovery time from a deep power-saving mode without a special command for releasing the deep power-saving mode. The flash memory of the present invention comprises: a standard command I/F circuit and a DPD controller operated by an external power supply voltage; a voltage supply node supplied with power from an external power supply voltage via a first current path; a voltage supply node supplied with power from an external power supply voltage via a second current path; an internal circuit group connected to the voltage supply node; and a charge pump circuit connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.
Description
Technical Field
The present invention relates to a semiconductor memory device such as a flash memory and a method thereof, and more particularly, to an operation in a standby mode or a deep power saving mode.
Background
A NAND (Not and, NAND) type flash memory (flash memory) can be read or programmed in units of pages and erased in units of blocks. The flash memory disclosed in patent document 1 includes: in a standby-by mode and a normal operation mode, different power supply voltages are supplied to a page buffer/read out circuit, thereby reducing power consumption in the standby mode.
[ Prior art documents ]
[ patent document ]
[ patent document 1] Japanese patent application laid-open No. 2006-252748
Disclosure of Invention
[ problems to be solved by the invention ]
The flash memory has an active mode for reading, programming, erasing, etc. in response to a command from a user, and a standby mode for accepting a command from a user. In the standby mode, the operation of the internal circuit is restricted so that the power consumption is not more than a certain level, but when a command is input from the user, the command must be immediately responded to. Therefore, even in the standby mode, a shoot-through current (off-leak current) is generated in a volatile circuit such as a logic circuit or a register (register), the shoot-through current increases with the reduction in the size of the element, and when an internal power supply voltage is used, the internal power supply voltage detection circuit must be operated to consume a certain amount of power. That is, it is difficult to reduce the current consumption in the standby mode.
In order to further reduce power consumption in the standby mode, a deep power-down mode (hereinafter referred to as a DPD mode) is mounted depending on the flash memory. In the DPD mode, power supply to the internal circuits of some active internal circuits in the standby mode is turned off, and the power leakage current is reduced. The DPD mode is entered into the mode by a DPD start command, for example, and is recovered from the mode by a DPD release command. While recovery from the DPD mode requires a certain time to normally operate the shutdown circuit, it has an advantage that power consumption can be significantly reduced.
Fig. 1A shows an example of an operation waveform when a NAND flash memory having a Serial Peripheral Interface (SPI) function jumps to a DPD mode. In the standby mode, the flash memory is selected by setting the chip select signal/CS to low level, and a dpd command is input from the data input terminal DI in synchronization with a clock signal during this period (B9 h). Flash memory has passed through from the input of DPD commandTime T of fixed period tDPDPDThe operation jumps to the DPD mode, and blocks the internal supply voltage to a specific internal circuit. Time TDPDIn the previous period, the current of the standby mode is consumed, and the time TDPDIn the subsequent period, the current of the DPD mode is consumed.
Fig. 1B shows an example of an operating waveform when the DPD mode is restored. In the standby mode, the flash memory is selected by setting the chip select signal/CS to low level, and a DPD release command for releasing the DPD mode is inputted from the data input terminal DI in synchronization with the clock signal during this period (ABh). The flash memory supplies power to the internal circuit that is turned off during the period of tRES from the input of the DPD release command, and at time TSTAnd the state of the internal circuit is recovered to be in normal operation. At time TSTPreviously, consuming the current of DPD mode at time TSTThereafter, the current of the standby mode is consumed.
Fig. 2 is an internal block diagram of a NAND-type flash memory supporting a DPD mode. The flash memory 10 includes a DPD controller 20, a memory cell array (memory cell array)30, a row decoder 40, a page buffer/readout circuit 50, peripheral circuits 60, and a high voltage circuit 70. An external power supply voltage (e.g., 3.3V) VCC is supplied to the flash memory 10, and the DPD controller 20 operates directly using the external power supply voltage VCC. A P-channel Metal Oxide Semiconductor (PMOS) transistor P is connected between the external power supply voltage VCC and the internal circuit, and a DPD enable signal DPDEN is applied to a gate of the transistor P. In the active mode and the standby mode, the DPD controller 20 generates a DPD enable signal DPDEN of an L level to turn on the transistor P. Thus, the internal voltage VDD is supplied to each internal circuit via the voltage supply node INTVDD. In the DPD mode, the DPD controller 20 generates a DPD enable signal DPDEN of H level to turn off the transistor P. Thus, the supply of the external power supply voltage VCC is stopped, and the operation of the internal circuit is stopped.
In the case of releasing the DPD mode, as shown in fig. 1B, the user inputs a DPD release command from the outside (ABh). In response to the input of the DPD release command, the DPD controller 20 transits the DPD enable signal DPDEN to L level, turns on the transistor P, and starts to supply power from the external power supply voltage VCC to the internal circuits. Thus, the internal circuit is restored to an operable state after the period tRES.
As described above, in the conventional flash memory, in order to use the DPD mode, the user must input not only the DPD command but also the DPD release command, and the DPD mode cannot be used in the flash memory controller which does not support the DPD command and the DPD release command. Further, when the DPD mode is released and power from the external power supply voltage VCC is supplied to the voltage supply node INTVDD, if the load capacitance of the internal circuit is large, the time tRES until the voltage supply node INTVDD reaches the voltage at which the internal circuit can operate becomes long.
The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a semiconductor memory device which can shorten the recovery time from a deep power saving mode without requiring a dedicated command for releasing the deep power saving mode.
[ means for solving problems ]
The operation method of the flash memory comprises the following steps: a step of jumping to a deep power saving mode that blocks supply of power from a power supply source to an internal circuit; a step of releasing the deep power saving mode when a standard command including read, program or erase is inputted; and a step of executing the standard command after the deep power saving mode is released, the step of releasing supplying power from the power supply source to at least a first circuit part and a second circuit part of the internal circuit, respectively.
In one embodiment of the flash memory according to the present invention, the step of releasing further supplies a first enable signal for making the first circuit portion operable to the first circuit portion, and supplies a second enable signal for making the second circuit portion operable to the second circuit portion after supplying the first enable signal. In one embodiment of the flash memory of the present invention, the executing step uses the first circuit portion in a first processing order and uses the second circuit portion in a second processing order subsequent to the first processing order. In one embodiment of the flash memory according to the present invention, a first reset time until the first enable signal is supplied and a second reset time until the second enable signal is supplied are shorter than a reset time for setting the entire internal circuit to an operable state. In one embodiment of the flash memory of the present invention, a load capacitance of the first circuit portion is smaller than a load capacitance of the second circuit portion. In one embodiment of the flash memory of the present invention, the first circuit portion includes a charge pump circuit, and the second circuit portion includes a peripheral circuit of the memory cell array, and a time required for the charge pump to generate the boosted voltage is shorter than a difference between the second reset time and the first reset time. In one embodiment of the flash memory according to the present invention, the deep power saving mode jumps from the standby mode when the standby mode continues for a certain time.
The semiconductor memory device of the present invention includes: an internal circuit including at least a first circuit portion and a second circuit portion; a skip section that skips to a deep power saving mode that blocks supply of power from a power supply source to the first circuit portion and the second circuit portion; a release section that releases the deep power saving mode when a standard command including reading, programming, or erasing is input; and an executing unit configured to execute the standard command after the deep power saving mode is released, the releasing unit including: a first current path that supplies power from the power supply source to the first circuit portion; and a second current path that supplies power from the power supply source to the second circuit portion.
In one embodiment of the semiconductor memory device of the present invention, the release unit includes: a first supply section that supplies a first enable signal for making the first circuit portion operable to the first circuit portion; and a second supply section that supplies a second enable signal for making the second circuit operable to the second circuit section after the first enable signal is supplied. In one embodiment of the semiconductor memory device of the present invention, the execution unit uses the first circuit portion in a first process sequence, and uses the second circuit portion in a second process sequence subsequent to the first process sequence. In one embodiment of the semiconductor memory device of the present invention, a first reset time until the first enable signal is supplied and a second reset time until the second enable signal is supplied are shorter than reset times for making the first circuit portion and the second circuit portion operable. In one embodiment of the semiconductor memory device of the present invention, a load capacitance of the first circuit portion is smaller than a load capacitance of the second circuit portion. In one embodiment of the semiconductor memory device of the present invention, the first circuit portion includes a charge pump circuit, the second circuit portion includes a peripheral circuit of a memory cell array, and a time required for the charge pump to generate the boosted voltage is shorter than a difference between the second reset time and the first reset time. In one embodiment of the semiconductor memory device of the present invention, the release unit includes a first transistor and a second transistor in the first current path and the second current path, and the release unit controls conduction or non-conduction of the first transistor and the second transistor. In one embodiment of the semiconductor memory device of the present invention, the semiconductor memory device is a flash memory.
[ Effect of the invention ]
According to the present invention, the deep power saving mode can be released in response to the input of a standard command without a dedicated command for releasing the deep power saving mode. Further, when the deep power saving mode is released, electric power is supplied from the electric power supply source to the first circuit portion and the second circuit portion, respectively, and therefore, as compared with the case where electric power is supplied to the first circuit portion and the second circuit portion in common, the time for bringing the first circuit portion or the second circuit portion into an operable state can be shortened, and as a result, the recovery time from the deep power saving mode can be minimized.
Drawings
Fig. 1A is a diagram showing an example of an operation waveform when a conventional flash memory jumps to a DPD mode;
FIG. 1B is a diagram showing an example of an operation waveform when a conventional flash memory releases a DPD mode;
fig. 2 is a diagram showing an internal configuration of a conventional flash memory;
FIG. 3 is a diagram showing the internal configuration of a flash memory according to an embodiment of the present invention;
fig. 4 is a diagram showing operation waveforms of respective sections when the DPD mode according to the embodiment of the present invention is released.
[ description of symbols ]
10. 100, and (2) a step of: flash memory
20. 120: DPD controller
30. 130, 130: memory cell array
40: row decoder
50: page buffer/read-out circuit
60: peripheral circuit
70: high voltage circuit
110: standard command I/F circuit
140: row decoder (peripheral circuit)
150: page buffer/readout circuit (peripheral circuit)
160: peripheral circuit
170: high voltage circuit (peripheral circuit)
180: charge pump circuit
ABh: DPD Release Command
B9 h: DPD command
CPUEN: CPU enable signal
DEC: decoding result
DI: data input terminal
DPDEN: DPD enable signal
INTVDD, INTVDDCP: voltage supply node
P: PMOS transistor
P1, P2: transistor with a metal gate electrode
PUMPEN: pump enable signal
TDPD、TST: time of day
t1, t2, t2A, t 3: time of day
tDP: for a certain period of time
tRES: duration, time, recovery time
VCC: voltage of external power supply
VWWPUMP: pump voltage
CS: chip select signal
Detailed Description
The semiconductor memory device of the present invention is Not particularly limited, and is implemented in, for example, a NAND-type OR NOR (Not OR, NOR) flash memory.
[ examples ]
Next, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 3 is a diagram showing a schematic internal configuration of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a standard command interface (I/F) circuit 110 that receives a standard command, a DPD controller 120 that controls jumping to a DPD mode and releasing the DPD mode, and other internal circuits such as a memory cell array 130, a row decoder 140, a page buffer/readout circuit 150, a peripheral circuit 160, a high voltage circuit 170, and a charge pump circuit 180.
The flash memory 100 of the present embodiment can operate in a plurality of power consumption modes. The active mode performs operations such as standard commands (e.g., read, program, erase) without limiting power consumption and full specification. The standby mode is a mode in which, when not the active mode, the internal circuit is operated in accordance with a predetermined power consumption request, and the operation is performed so as to respond to an input of a standard command or the like. In the standby mode, for example, a charge pump (charge pump) of the high voltage circuit is stopped, or the internal supply voltage is lowered. In the DPD mode, power supply to a specific circuit is blocked in the standby mode in order to further reduce power consumption in the standby mode.
The standard command I/F circuit 110 and DPD controller 120 operate directly using an external power supply voltage VCC (e.g., 3.3V), i.e., are operable in a standby mode and a DPD mode. The standard command I/F circuit 110 is an interface circuit for receiving a standard command prepared in advance for standard operation of the flash memory from the outside. The standard commands are for example commands for reading, programming, erasing etc. The standard command I/F circuit 110 includes a Complementary Metal Oxide Semiconductor (CMOS) logic device for decoding an input standard command, and a decoding result DEC is provided to the DPD controller 120 and the peripheral circuit 160 (including a controller or a state machine (state machine) for controlling the operation of the standard command, etc.).
The DPD controller 120 controls jumping from the standby mode to the DPD mode and releasing of the DPD mode. A first current path between the external power supply voltage VCC and the voltage supply node INTVDD is connected to the PMOS transistor P1, and a second current path between the external power supply voltage VCC and the voltage supply node INTVDDCP is connected to the PMOS transistor P2. The row decoder 140, the page buffer/readout circuit 150, the peripheral circuit 160, and the high voltage circuit 170 are connected to a voltage supply node INTVDD, and the charge pump circuit 180 is connected to a voltage supply node INTVDDCP.
The DPD enable signal DPDEN from the DPD controller 120 is applied to the gates of the transistors P1, P2 in common. In the active mode and the standby mode, the DPD controller 120 generates the DPD enable signal DPDEN of the L level to turn on the transistors P1 and P2, thereby supplying power from the external power supply voltage VCC to the voltage supply node INTVDD via the first current path and supplying power to the voltage supply node INTVDDCP via the second current path. In the DPD mode, the DPD controller 120 makes the DPD enable signal DPDEN transition to the H level, turns off the transistors P1 and P2 of the first and second current paths, and blocks the supply of power from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP.
The method of jumping from the standby mode to the DPD mode is not particularly limited, and in one embodiment, the DPD controller 120 does not input a command for jumping to the DPD mode from a user, and automatically jumps to the DPD mode in response to a signal from a peripheral circuit 160 (including a controller or the like that controls the operation of the flash memory). For example, when a signal indicating a jump to the standby mode is supplied from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures a time from a time point indicating the jump to the standby mode, jumps to the DPD mode when the duration of the standby mode exceeds a certain time, transitions the DPD enable signal DPDEN to the H level, and blocks the supply of power from the external power supply voltage VCC. In addition, in another embodiment, the DPD controller 120 may also jump to the DPD mode in response to an input of a command for jumping to the DPD mode from a user.
In the conventional method for releasing the DPD mode, a dedicated command for releasing the DPD mode needs to be inputted from the outside, but in the present embodiment, a function for automatically releasing the DPD mode without inputting such a dedicated command is provided. If the standard command is input from the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 releases the DPD mode in response to the input of the standard command. The input standard command is seamlessly executed after the lapse of time required for restoration from the DPD mode.
The DPD controller 120 further generates a pump enable signal PUMPEN for subsequently enabling the charge pump circuit 180 and a CPU enable signal CPU en for subsequently enabling a Central Processing Unit (CPU) included in a controller of the peripheral circuit 160, when the DPD mode is released, that is, when power is supplied from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP through the first current path and the second current path, respectively. The pump enable signal PUMPEN is supplied to the charge pump circuit 180, and the CPU enable signal CPU en is supplied to the peripheral circuit 160. These operations will be described in detail later, but the DPD controller 120 makes the pump enable signal PUMPEN transition to the H level to enable the charge pump circuit 180 when the voltage supply node INTVDDCP reaches the target voltage from the time point when the DPD mode is released, and then makes the CPU enable signal CPU en transition to the H level to enable the controller of the peripheral circuit 160 when the voltage supply node INTVDD reaches the target voltage.
The DPD controller 120 of the present embodiment may be configured using hardware and/or software, and may include, for example, a microcomputer, a state machine, a logic device, and the like.
The memory cell array 130 includes a plurality of blocks, each block including a plurality of NAND strings (strings). The NAND string may be formed two-dimensionally on the substrate or three-dimensionally in a vertical direction from the main surface of the substrate. In addition, the memory unit may store binary data or multivalued data.
The peripheral circuit 160 includes, for example, the following parts: a controller or state machine that controls the operation of the flash memory 100 based on a standard command or the like received by the standard command I/F circuit 110; or an Error Checking and Correcting (ECC) circuit and a column selection circuit, and performs Error detection and Correction of data. The high voltage circuit 170 receives the voltage boosted by the charge pump circuit 180, and generates high voltages (e.g., a program pulse voltage, an erase pulse voltage, a read path voltage, etc.) required for read, program, and erase operations. The flash memory 100 may be equipped with an SPI (serial Peripheral interface) that recognizes an input command, address, and data in synchronization with a serial clock signal in place of a control signal (address latch permission, command latch permission, and the like).
Next, the operation of releasing the DPD mode in the flash memory according to the present embodiment will be described. Fig. 4 is a diagram showing operation waveforms of respective sections when the DPD mode is released. When the flash memory 100 is in the DPD mode, the DPD enable signal DPDEN is at an H level, power supply from the external power supply voltage VCC is blocked, and the voltage supply nodes INTVDD and INTVDDCP are Ground (GND) levels. In the DPD mode, the standard command I/F circuit 110 and the DPD controller 120 are in a state of being operable by power from the external power supply voltage VCC.
If a standard command is input to the standard command I/F circuit 110, the standard command I/F circuit 110 supplies a decoding result DEC of the standard command to the DPD controller 120 and the peripheral circuit 160. However, at this point in time, the peripheral circuit 160 is not in an operable state.
The DPD controller 120 automatically releases the DPD mode when the decoding result DEC is received from the standard command I/F command 110 in the DPD mode. That is, at time t1, the DPD controller 120 transits the DPD enable signal DPDEN from the H level to the L level, and turns on the transistors P1 and P2. Thus, power is supplied from the external power supply voltage VCC via the first current path to the voltage supply node INTVDD, and power is supplied from the external power supply voltage VCC via the second current path to the voltage supply node INTVDDCP. That is, the voltage supply node INTVDD and the voltage supply node INTVDCP are each charged with power from the external power supply voltage VCC.
The row decoder 140, the page buffer/readout circuit 150, the peripheral circuit 160, and the high voltage circuit 170 are connected to a voltage supply node INTVDD, and the charge pump circuit 180 is connected to a voltage supply node INTVDDCP. The peripheral circuit groups 140 to 170 connected to the voltage supply node INTVDD have a larger number of transistors and a larger wiring capacitance (larger load capacitance) than the charge pump circuit 180 connected to the voltage supply node INTVDDCP, and thus the voltage supply node INTVDD rises to the target voltage more slowly than the voltage supply node INTVDDCP. Therefore, the charge time to the target voltage of the voltage supply node INTVDDCP is faster than the voltage supply node INTVDD, and as shown in fig. 4, the voltage supply node INTVDDCP reaches the target voltage at time t2 after tresscp from time t1, but the voltage supply node INTVDD reaches the target voltage at time t3 after tressvdd from time t1 (tresscp < tressvdd). In addition, the target voltage of the voltage supply node INTVDDCP is a voltage at which the charge pump circuit 180 becomes operable, and the target voltage of the voltage supply node INTVDD is a voltage at which the CPU of the peripheral circuit 160 becomes operable.
The DPD controller 120 makes the pump enable signal PUMPEN transition from the L level to the H level at time t2 when the charge pump circuit 180 becomes operable. The charge pump circuit 180 starts the pump operation at time t2 in response to the pump enable signal PUMPEN, and generates the desired pump voltage VWWPUMP at time t2A after tPUMP from time t 2. In this embodiment, the charge pump circuit 180 can operate after the voltage supply node INTVDDCP reaches the target voltage, without waiting for the voltage supply node INTVDD to reach the target voltage.
Further, the DPD controller 120 makes the CPU enable signal CPUEN transition from the L level to the H level at time t3 when the peripheral circuit 160 becomes operable. The Controller (CPU) of the peripheral circuit 160 starts the execution of the standard command at time t3 in response to the CPU enable signal CPU en. At time t3 when the two voltage supply nodes INTVDD and INTVDDCP reach the target voltages, the recovery time tRES for recovery from the DPD mode ends. In the case of the relationship of tPUMP < tRESVDD-tRESCP, the pump voltage VWPUMP is already generated at the time point of starting the operation of the standard command, and thus the high voltage generating circuit 170 may immediately supply the high voltage required for the operation to the page buffer/readout circuit 150 or the row decoder 140, etc. In contrast, even in the relationship of tPUMP > tRESVDD-tRESCP, the supply pump voltage VWPUMP can be made faster than in the case where the operation of the charge pump circuit 180 is not advanced.
The control method at time t2 and time t3 by the DPD controller 120 is not particularly limited, and for example, the DPD controller 120 may measure the time from time t1 by a built-in timer, and transition the enable signal PUMPEN and the enable signal CPUEN to the H level when tresscp and trevdd are reached. In another embodiment, a detection circuit for detecting the voltages of the voltage supply nodes INTVDDCP and INTVDD may be provided, and the DPD controller 120 may transition the enable signals PUMPEN and CPUEN to H level when the detection circuit detects the target voltages of the voltage supply nodes.
As a specific operation example, when a read, program, or erase command is input to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 transits the DPD enable signal DPDEN to the L level, turns on the transistor P1 and the transistor P2, starts supplying power from the external power supply voltage VCC, and releases the DPD mode. The DPD controller 120 operates the charge pump circuit 180 at time t2 after tresscp from time t1 until the voltages of the voltage supply node INTVDD and the voltage supply node INTVDDCP are restored, generates the pump voltage VWWPUMP from the charge pump circuit 180 during a period from time t1 to time t3 after trevdd, and starts the command execution at time t3 by the controller of the peripheral circuit 160. The boost voltage required for sensing, programming or erasing can be utilized immediately after the command is executed.
As described above, according to the present embodiment, the DPD mode is automatically released in response to the input of the standard command, and therefore, it is not necessary to input a dedicated command for releasing the DPD mode, and the DPD mode can be released even in a flash memory which does not support the command for releasing the DPD mode.
Further, when the shut down internal circuit is restored from the DPD mode, power is supplied not to the voltage supply node INTVDD connected to the entire internal circuit as shown in the conventional fig. 2 but to the voltage supply nodes INTVDD connected to the peripheral circuit groups 140 to 170 and the voltage supply node INTVDDCP connected to the charge pump circuit 180 in a divided manner, and the operation of the charge pump circuit 180 is advanced, so that the time tRES for restoring the internal circuit to the operable state can be shortened as compared with the conventional one (fig. 1B).
In the above embodiment, the internal circuits to which power is not supplied in the DPD mode are divided into the peripheral circuits 140 to 170 and the charge pump circuit 180 to recover from the DPD mode. When the operation is resumed from the DPD mode, the internal circuit for advancing the operation may not necessarily include a charge pump circuit, but may be another circuit. Further, the circuit restored from the internal circuit may be divided into three or more circuit portions, and power may be supplied to each circuit portion via a different current path.
In a certain embodiment, in the case of restoring the first circuit portion and the second circuit portion from the DPD mode, the selection of the first circuit portion and the second circuit portion may also correspond to the processing order when the standard command is executed. That is, the first processing sequence when the standard command is executed uses the first circuit portion, and the second processing sequence uses the second circuit portion, so that the first circuit portion is made operable earlier than the second circuit portion. When the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion, the first circuit portion starts operating in the reset of the second circuit portion, and the reset time is more effectively shortened. For example, in the case where the program operation includes both the program verify operation and the program verify operation, and the program verify operation is performed first, only the circuit part related to the verify connected to the voltage supply node INTVDDx may be operated first, and in the verify operation, the voltage supply node INTVDDy connected to the circuit part for the program reaches the target voltage.
In the above embodiment, the Read, program, and erase are exemplified as the standard commands, but the standard commands may include, in addition to these, Status Read (Status Read) which is a command for reading whether the flash memory is in a ready (ready) state, a write protect mode, a program/erase operation, and an ID Read which is a command for reading a manufacturer or product identification.
In the above embodiment, the power is supplied from the external power supply voltage VCC to the voltage supply node INTVDD and the voltage supply node INTVDDCP, but this is an example, and the power may be supplied from another internal power supply voltage to the voltage supply node INTVDD and the voltage supply node INTVDDCP without being directly supplied from the external power supply voltage VCC.
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the invention described in the claims.
Claims (16)
1. A method of operating a flash memory, comprising:
a step of jumping to a deep power saving mode that blocks supply of power from a power supply source to an internal circuit;
a step of releasing the deep power saving mode when a standard command including read, program or erase is inputted; and
executing the standard command after releasing the deep power saving mode,
the step of releasing supplies power from the power supply source to at least a first circuit part and a second circuit part of the internal circuit, respectively.
2. The method of operating a flash memory according to claim 1,
the step of releasing further supplies a first enable signal for enabling the first circuit portion to operate to the first circuit portion, and supplies a second enable signal for enabling the second circuit portion to operate to the second circuit portion after the first enable signal is supplied.
3. The method of operating the flash memory according to claim 2,
the step of performing uses the first circuit portion in a first processing order and uses the second circuit portion in a second processing order subsequent to the first processing order.
4. The method of operating the flash memory according to claim 2 or 3,
the first reset time until the first enable signal is supplied and the second reset time until the second enable signal is supplied are shorter than the reset time for setting the entire internal circuit to an operable state.
5. The method of operating the flash memory according to any one of claims 1 to 3,
the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion.
6. The method of operating the flash memory according to claim 4,
the first circuit portion includes charge pump circuitry, the second circuit portion includes peripheral circuitry of an array of memory cells,
the time required for the charge pump to generate the boosted voltage is shorter than a difference between the second recovery time and the first recovery time.
7. The method of operating a flash memory according to claim 1,
the deep power saving mode jumps from a standby mode when the standby mode continues for a certain time.
8. A semiconductor memory device, comprising:
an internal circuit including at least a first circuit portion and a second circuit portion;
a skip section that skips to a deep power saving mode that blocks supply of power from a power supply source to the first circuit portion and the second circuit portion;
a release section that releases the deep power saving mode when a standard command including reading, programming, or erasing is input; and
an execution unit that executes the standard command after the deep power saving mode is released,
the release member includes: a first current path that supplies power from the power supply source to the first circuit portion; and a second current path that supplies power from the power supply source to the second circuit portion.
9. The semiconductor memory device according to claim 8,
the release member includes: a first supply section that supplies a first enable signal for enabling the first circuit section to operate to the first circuit section; and a second supply section that supplies a second enable signal for enabling the second circuit to operate to the second circuit portion after the first enable signal is supplied.
10. The semiconductor memory device according to claim 8,
the execution unit uses the first circuit portion in a first processing order and uses the second circuit portion in a second processing order subsequent to the first processing order.
11. The semiconductor memory device according to claim 8,
the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than the recovery time for bringing the first circuit portion and the second circuit portion into an operable state.
12. The semiconductor memory device according to claim 9,
the first recovery time until the first enable signal is supplied and the second recovery time until the second enable signal is supplied are shorter than the recovery time for bringing the first circuit portion and the second circuit portion into an operable state.
13. The semiconductor storage device according to any one of claims 8 to 10,
the load capacitance of the first circuit portion is smaller than the load capacitance of the second circuit portion.
14. The semiconductor storage device according to claim 11 or 12,
the first circuit portion includes charge pump circuitry, the second circuit portion includes peripheral circuitry of an array of memory cells,
the time required for the charge pump to generate the boosted voltage is shorter than a difference between the second recovery time and the first recovery time.
15. The semiconductor memory device according to claim 8,
the release unit includes a first transistor and a second transistor in the first current path and the second current path, and controls conduction or non-conduction of the first transistor and the second transistor.
16. The semiconductor storage device according to any one of claims 8 to 10,
the semiconductor memory device is a flash memory.
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