JP2009237602A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system improved in operational reliability. <P>SOLUTION: This memory system is provided with: a semiconductor memory 3 with a non-volatile memory cell for storing data; and a backup control circuit 6 for supplying a backup power source 2 and a first external power source (power source C). When the first external power source is interrupted during the write-in of data in the memory cell of the semiconductor memory 3, the backup control circuit 6 supplies a voltage applied from the backup power source 2 to the semiconductor memory 3, and stops the supply of the voltage to be applied from the backup power source 2 after the end of the write-in of the data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory system. For example, it relates to a memory system having a backup power source.

For example, in a memory system such as a mobile device such as a mobile phone, supply from an external power supply that supplies power to the nonvolatile memory may be interrupted while the nonvolatile memory is executing a write operation. . In such a case, the writing operation in the nonvolatile memory may not be completed normally (see, for example, Patent Document 1). For this reason, there is a problem that expected write data is erased or destroyed in the nonvolatile memory.
JP-A-3-63714

  The present invention provides a memory system that improves operational reliability.

  A memory system according to an aspect of the present invention includes a semiconductor memory including a nonvolatile memory cell capable of holding data, a first external voltage applied from a first external power supply, and a backup voltage applied from a backup power supply. A backup control circuit that supplies the semiconductor memory, and the backup control circuit supplies the backup voltage when the first external power supply is cut off during the writing of data to the memory cell. After the supply to the semiconductor memory and the writing is completed, the supply of the backup voltage is stopped.

  ADVANTAGE OF THE INVENTION According to this invention, the memory system which improves operation | movement reliability can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A memory system according to a first embodiment of the present invention will be described.

<Example of overall configuration of memory system>
First, an example of the overall configuration of the memory system will be described with reference to FIG. FIG. 1 is a block diagram of a memory system according to this embodiment.

  As shown in the figure, the memory system includes an LSI 1 and a backup power source 2. The LSI 1 is a non-volatile semiconductor memory device, and operates by receiving voltage supply from the power sources B and C and the backup power source 2 which are external power sources. The backup power supply 2 supplies an emergency (backup) voltage to the LSI 1 when the power supply C is shut off.

  The LSI 1 includes a nonvolatile memory 3, a memory controller 4, a control circuit 5 having a timer function (hereinafter referred to as a timer 5), and a backup control circuit 6. The nonvolatile memory 3 is a semiconductor memory including nonvolatile memory cells that can hold data, and is, for example, a NAND flash memory. In response to an instruction from the memory controller 4, data is written / read / erased.

  The nonvolatile memory 3 outputs a busy signal to the memory controller 4 and the backup control circuit 6. The busy signal is a signal for notifying the operating state of the nonvolatile memory 3 to the outside. That is, when the nonvolatile memory 3 is writing or reading data and does not accept external access, the busy signal is asserted (assert, in this embodiment, the ‘L’ level). This state is hereinafter referred to as a busy state. On the other hand, in a state where access is possible from the outside, the busy signal is negated (in the present embodiment, 'H' level). Hereinafter, this state is referred to as a ready state. Further, the power supply terminal VDD_Mem of the nonvolatile memory 3 is connected to the backup control circuit 6, and a power supply voltage is supplied from either the power supply C or the backup power supply 2.

  The memory controller 4 operates by receiving supply of power supply voltage from the power supply B via the power supply terminal VDD_Cont. The memory controller 4 performs control such as data writing / reading / erasing with respect to the nonvolatile memory 3 in response to a command from a host device (not shown). The memory controller 4 exchanges data and control signals with the nonvolatile memory 3 when the nonvolatile memory 3 is in a ready state, that is, when the busy signal is at the “H” level. In the busy state, exchange of data and control signals is prohibited.

  The timer 5 has a clock function, for example. The timer 5 is connected to the power supply C and the backup power supply 2 via the power supply terminal VDD_B. In other words, even when the power source C is shut off for some reason, for example, the voltage is supplied from the backup power source 2, so that the timer 5 can always operate.

  The backup control circuit 6 supplies a voltage supplied from the power supply C to the nonvolatile memory 3. The nonvolatile memory 3 operates using this voltage as a power supply voltage. Further, the backup control circuit 6 gives the backup power supply 2 via the input terminal T2 when the power supply C is interrupted for some reason while the data write operation is being performed in the nonvolatile memory 3. The supplied voltage is supplied from the output terminal T4 to the nonvolatile memory 3. In this case, the nonvolatile memory 3 operates using the voltage supplied from the backup power supply 2 as the power supply voltage. When the writing operation is completed in the nonvolatile memory 3, the backup control circuit 6 stops supplying the voltage supplied from the backup power source 2 to the nonvolatile memory 3. The backup control circuit 6 receives the busy signal from the input terminal T3, and determines whether or not the nonvolatile memory 3 is performing a write operation.

  Hereinafter, details of the above-described nonvolatile memory 3, memory controller 4, and backup control circuit 6 will be described.

<Configuration Example of Nonvolatile Memory 3>
Next, details of the configuration of the nonvolatile memory 3 will be described with reference to FIG.

  As shown, the nonvolatile memory 3 includes a memory cell array 11, a bit line control circuit 12, a column decoder 13, a data input / output buffer 14, a data input / output terminal 15, a word line control circuit 16, a control unit 17, and a control signal. An input terminal 18 is provided.

  The memory cell array 11 includes a plurality of nonvolatile memory cells. The memory cell is an n-channel MOS transistor including a stacked gate including a charge storage layer and a control gate, for example. The control gate of the memory cell is connected to the word line, the drain is electrically connected to the bit line, and the source is electrically connected to the source line.

  The word line control circuit 16 selects the row direction of the memory cell array 11. That is, one of the word lines is selected according to the row address given from the control unit 17, and a voltage is applied to the selected word line.

  The column decoder 13 selects the column direction of the memory cell array 1 according to the column address given from the control unit 17.

  In the data write operation, the bit line control circuit 12 transfers the data supplied from the data input / output buffer 14 to the bit line and writes the data to the memory cell. At the time of reading, data is read to the bit line selected by the column decoder 13, and the read data is sensed and amplified.

  The data input / output terminal 15 outputs the write data, address, and command supplied from the memory controller 4 to the data input / output buffer 14. Further, the read data is output to the memory controller 4.

  The data input / output buffer 14 temporarily holds write data, an address, and a command received at the data input / output terminal 15. Then, the write data is output to the bit line control circuit 12, and the address and command are output to the control unit 17. The read data received from the bit line control circuit 12 is output to the memory controller 4 via the data input / output terminal 15.

  The control signal input terminal 18 supplies the control signal supplied from the memory controller 4 to the control unit 17. The control signal is, for example, a write enable signal for controlling the write operation, a chip enable signal for enabling the operation of the nonvolatile memory 3 itself, or the like.

  The control unit 17 controls the operation of the entire nonvolatile memory 3. That is, based on the control signal received at the control input terminal 18 and the command and address received from the data input / output buffer 14, the operation sequence during the data write operation, read operation and erase operation is executed. In order to execute this sequence, the operation of each circuit block included in the nonvolatile memory 3 is controlled. The control unit 17 outputs the busy signal described above to the memory controller 4 based on the control state of each circuit block in the nonvolatile memory 3. Further, the control unit 17 includes a voltage generation circuit. The voltage generation circuit generates a voltage necessary for a data write operation, a read operation, and an erase operation, and supplies the voltage to each circuit block in the nonvolatile memory 3.

<Configuration Example of Memory Cell Array 11>
Next, a configuration example of the memory cell array 11 will be described in detail with reference to FIG. FIG. 3 is a block diagram of the NAND flash memory according to the present embodiment.

  As illustrated, the memory cell array 11 includes a plurality of NAND cells 20 in which nonvolatile memory cells are connected in series. Each of the NAND cells 20 includes, for example, 16 memory cell transistors MT and select transistors ST1 and ST2. The memory cell transistor MT is an n-channel MOS transistor having a MONOS type or FG type stacked gate, for example. The MONOS type stacked gate has the following configuration. That is, the stacked gate is formed of a charge storage layer (insulating film) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween, and an insulating film (hereinafter referred to as a dielectric constant higher than the charge storage layer). And a control gate formed on the block layer. In the case of the FG type, the stacked gate is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a charge storage layer (floating gate: conductive layer) and on the floating gate with an intergate insulating film interposed therebetween. Control gate. The number of memory cell transistors MT is not limited to 16, and may be 8, 32, 64, 128, 256, etc., and the number is not limited. The adjacent memory cell transistors MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to one of the word lines WL0 to WL15, and the gate electrodes of the select transistors ST1 and ST2 of the memory cells in the same row are connected to the select gate lines SGD and SGS, respectively. Commonly connected. For simplification of description, the word lines WL0 to WL15 may be simply referred to as word lines WL below when not distinguished from each other. Further, the drains of the select transistors ST1 in the same column in the memory cell array 11 are commonly connected to any one of the bit lines BL0 to BLn (n is a natural number). Hereinafter, the bit lines BL0 to BLn are collectively referred to as the bit lines BL unless they are distinguished. The sources of the selection transistors ST2 are commonly connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as the NAND cell 5 can be selected.

  In FIG. 3, only one row of NAND cells 20 is illustrated. However, a plurality of rows of NAND cells 20 may be provided in the memory cell array 11. In this case, NAND cells 20 in the same column are connected to the same bit line BL. Data is collectively written in the plurality of memory cell transistors MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from a plurality of NAND cells in the same row, and this unit is called a memory block.

<Configuration Example of Memory Controller 4>
Next, a configuration example of the memory controller 4 will be described with reference to FIG. FIG. 4 is a block diagram of the memory controller 4.

  As shown in the figure, the memory controller 4 has a physical state inside the memory cell array 11 (for example, what logical block address data is included in the physical block address, or where the block is in the erased state. Manage). The memory controller 4 includes a memory interface 30, an MPU (Micro Processing Unit) 32, a RAM (Random Access Memory) 31, and a host interface 33. For example, they are formed on the same substrate and are communicably connected by an internal bus 34.

  The host interface 33 can be connected to a host device (not shown) and manages communication with the host device.

  The memory interface 30 manages communication with the nonvolatile memory 3 through a data bus (not shown). That is, the memory interface 30 transmits and receives control signals, addresses, commands, and data signals to and from the nonvolatile memory 3. The control signal is also a control signal for determining whether a signal transmitted to the nonvolatile memory 3 is an address, a command, or data. The data signal is a signal of data written / read to / from the memory cell array 11 and is transmitted / received to / from the nonvolatile memory 3 via a data bus (not shown). An address and a command signal are also transmitted to the nonvolatile memory 3 via a data bus (not shown).

  The MPU 32 controls the overall operation of the memory controller 4. Various tables are created on the RAM 31 by reading firmware (control program) stored in a host device (not shown) onto the RAM 31 and executing predetermined processing. That is, a write command, a read command, and an erase command are received from the host interface 33, and a predetermined operation is performed on the nonvolatile memory 3 and data transfer processing is controlled.

  The RAM 31 is used as a work area for the MPU 32 and stores a control program and the like.

<Configuration Example of Backup Control Circuit 6>
Next, a configuration example of the backup control circuit 6 will be described in detail with reference to FIG. FIG. 5 is a block diagram of the backup control circuit 6. As illustrated, the backup control circuit 6 includes a comparator 40, a switch control circuit 41, and a switch circuit 44.

  The comparator 40 has a normal rotation input terminal connected to the power supply B via the connection node T1, and an inverting input terminal supplied with a reference voltage VREF to be compared with the power supply B. The comparator 40 compares the reference voltage VREF (for example, 3.0 [V]) supplied from the memory controller 4 with the power supply B. That is, the comparator 40 outputs a 'L' level signal when the value of the power source B becomes equal to or lower than the reference voltage VREF. Specifically, the timing for outputting the ‘L’ level is when the power supply B becomes 2.7 [V] or less, for example. Further, when the value of the power supply B is larger than the reference voltage VREF, the 'H' level is output. Specifically, when the value of the power supply B is 2.8 [V] or more, the “H” level is output.

  The switch control circuit 41 includes an inverter 45 and a NAND gate 46. The inverter 45 inverts the comparison result of the comparator 40. The NAND gate 46 performs a NAND operation on the busy signal given from the nonvolatile memory 3 via the connection node T3 and the inversion result of the inverter 45. Then, the NAND gate 46 outputs the NAND operation result to the switch circuit 44 as a signal BACKCONT. Therefore, the NAND gate 46 sets the signal BACKCONT to “L” when the busy signal is at the “H” level (ready state) and the output of the inverter 45 is at the “H” level, and otherwise becomes “H”. Level. The configuration of the switch control circuit 41 is not limited to the combination of the inverter 45 and the NAND gate 46 as long as it can output the signal BACKCONT under similar logic conditions.

  The switch element 42 is, for example, an npn-type bipolar transistor, the signal BACKCONT is supplied to the base, the collector is connected to the power supply C and the backup power supply 2 via the connection node T2, and the emitter is connected to the nonvolatile memory via the connection node T4. 3 is connected. Therefore, when the signal BACKCONT is at the “H” level, the switch element 42 is turned on. As a result, the voltage generated by the power source C or the backup power source 2 is supplied to the nonvolatile memory 3. Therefore, even if the power source C is shut off for some reason, the voltage generated by the backup power source 2 is supplied to the nonvolatile memory 3 if the switch element 42 is in the ON state.

  The switch element 43 is, for example, an npn-type bipolar transistor, the output of the comparator 40 is supplied to the base, the collector is connected to the power supply C and the backup power supply 2 via the connection node T2, and the emitter is connected to the connection node T4. It is connected to the nonvolatile memory 3. Therefore, when the output of the comparator 40 is at the “H” level, the switch element 43 is turned on.

  Next, the operation of the backup control circuit 6 having the above configuration will be described with reference to FIG. FIG. 6 is a flowchart showing the operation flow of the backup control circuit 6. When both the power supplies B and C are off (step S0, NO), that is, when the power supplies B and C are not connected to the LSI 1, the comparator 40 outputs the 'L' level (S1).

  Further, when the busy signal is at the “H” level (ready state) (S2, YES), the signal BACKCONT is at the “L” level (S3). By step S0 and step S3, both switch elements 42 and 43 are turned off (S4).

  When the busy signal is at the “L” level in step S2 (busy state) (S2, NO), the signal BACKCONT is at the “H” level (S5). Thereby, the switch element 42 is turned on (S6), and the switch element 43 is turned off (S7).

  When the power supplies B and C are both in the on state (S0, YES), the output of the comparator 40 becomes the 'H' level (S8). In this case, the signal BACKCONT becomes 'H' regardless of the busy signal (S9). Accordingly, both the switch elements 42 and 43 are turned on (S10).

<Operation of the entire memory system>
Next, the operation of the memory system configured as described above will be described with reference to FIG. FIG. 7 is a state transition diagram showing an operation flow of the memory system. FIG. 7 shows that when the power supplies B and C are interrupted for some reason during the writing operation in the nonvolatile memory 3 after the power supplies B and C are switched from the OFF state to the ON state, the nonvolatile memory 3 writes data. A case where a voltage is supplied from the backup power source 2 to the nonvolatile memory 3 until the work is completed is shown.

  First, state 1 will be described. As shown in the figure, the power supplies B and C are in the off state (step S0, NO). Therefore, the output of the comparator 40 is at the “L” level (S1), and the busy signal is at the “H” level (S2, YES). Further, since the step S1 and the signal BACKCONT are at the 'L' level (S3), the switch elements 42 and 43 are both in the off state (S4). Further, since both the switch elements 42 and 43 are in the off state, a power supply path for the power supply voltage that the backup power supply 2 supplies to the nonvolatile memory 3 is not formed. For this reason, the power source of the nonvolatile memory 3 is in an off state.

  Next, state 2 will be described. As shown in the figure, when the power supplies B and C are turned on (S0, YES), the memory controller 4 connected to the power supply B is turned on, and the backup control circuit 6 is turned on. That is, a power supply path to the nonvolatile memory 3 is formed. That is, since the power supply B is in the ON state, the comparator 40 outputs the “H” level (S8). Since the nonvolatile memory 3 has not yet been written / read, the busy signal is at the “H” level (ready state). As a result, the signal BACKCONT becomes the “H” level (S9). As a result, the switch elements 42 and 43 are both turned on (S 10), and the power source C is connected to the nonvolatile memory 3. When the voltage is supplied from the power supply C, the nonvolatile memory 3 is also in an operating state.

  Next, state 3 will be described. The state 3 is a state in which the busy signal is set to the “L” level in the state 2. That is, the nonvolatile memory 3 is in a state where data writing / reading work is being performed. Otherwise, it is exactly the same as state 2.

  Next, state 4 will be described. State 4 is a state in which both the power supplies B and C are cut off (S0, NO) while the nonvolatile memory 3 performs a data write operation and the busy signal is at the ‘L’ level. In this case, since the output of the comparator 40 is ‘L’ level (S1) and the busy signal is ‘L’ level (S2, NO), the signal BACKCONT is ‘H’ level (S5). As a result, the switch element 42 is turned on (S6). Therefore, even if the power supplies B and C are cut off, the voltage from the backup power supply 2 is supplied to the nonvolatile memory 3 via the switch element 42. On the other hand, when the power supply B is shut off, the switch element 43 is turned off (S7).

  Next, state 5 will be described. In state 4, the data writing operation is normally completed. When data writing is completed in the nonvolatile memory 3, the busy signal is inverted from the 'L' level to the 'H' level (S2, YES). That is, the busy state transitions to the ready state. Then, since the signal BACKCONT is set to the “L” level (S3), the switch element 42 is switched to the off state (S4). Thereby, the supply of voltage from the backup power source 2 to the nonvolatile memory 3 is stopped. Note that the timer 5, which is always connected to the backup power supply, is always on.

<Effects according to this embodiment>
As described above, according to the memory system of the first embodiment, at least the following effects can be obtained.
(1) Operation reliability can be improved (part 1).
This will be described in detail below with reference to a memory system having a backup power supply as a comparative example.

  FIG. 8 shows a block diagram of a memory system as a comparative example. As shown in the drawing, the configuration according to the comparative example is obtained by eliminating the backup control circuit 6 from the configuration in FIG. 1 according to the present embodiment. That is, the memory system includes a nonvolatile memory 3, a memory controller 4, a timer 5, and a backup power source 2. In addition, the same reference number is attached | subjected to the same structure as this embodiment. As shown in the figure, in the memory system according to the comparative example, the backup power source 2 is used only for the timer 5. For this reason, for example, in the nonvolatile memory 3, if any one of the power source A and the power source B is interrupted for some reason during data writing, the power supply to the nonvolatile memory 3 is stopped. Therefore, the write operation in the nonvolatile memory 3 does not end normally. As a result, there is a problem in that the expected write data is erased or data is destroyed.

  In this regard, the memory system according to the present embodiment includes the backup control circuit 6. Therefore, the backup control circuit 6 supplies the voltage generated by the backup power supply 2 to the nonvolatile memory 3 even when the external power supplies B and C are cut off during writing in the nonvolatile memory 3. Therefore, the voltage supply to the nonvolatile memory 3 is not stopped until the data writing operation in the nonvolatile memory 3 is completed, and the data can be prevented from being erased or destroyed. Can be improved.

  The operation of the memory system 1 according to the present embodiment has been described for the case where both the power sources B and C are cut off. However, even when only the power source B is cut off for some reason, the nonvolatile memory 3, The operation of the backup control circuit 6 is the same as that in the above embodiment. In this case, the power supplied to the nonvolatile memory 3 is not the backup power 2 but the power C. Further, when only the power source C is shut off for some reason, the power source B is in an on state, so that the nonvolatile memory 3 and the backup control circuit 6 perform normal operations. That is, even if only the power source C is cut off during the data writing in the nonvolatile memory 3, the operations in the states 2 and 3 shown in FIG. 7 are performed.

[Second Embodiment]
Next explained is a memory system according to the second embodiment of the invention. In the present embodiment, the first embodiment is applied to a nonvolatile memory 3 having a dummy busy function. Hereinafter, only differences from the first embodiment will be described.

<Dummy busy function>
First, the dummy busy function of the nonvolatile memory 3 will be described. The non-volatile memory 3 according to this embodiment having a dummy busy function has the configuration of FIG. 2 as in the first embodiment. In the configuration of FIG. 2, the bit line control circuit 12 includes a data buffer (storage circuit) (not shown).

  At the time of data writing, the write data input from the data input / output terminal 15 is first stored in the data input / output buffer 14 and then the data in the bit line control circuit 12 in response to an instruction from the memory controller 4. Transferred to buffer. Thereafter, the write data transferred to the data buffer is applied to the bit line BL, and data is written.

  That is, the nonvolatile memory 3 has a configuration including a two-stage data buffer. Therefore, even if data is being written to the memory cell, if the data input / output buffer 14 is empty, the nonvolatile memory 3 can receive data from the outside. That is, it becomes a ready state. Conversely, even when data is not being written to the memory cell, if the data input / output buffer 14 is holding data, the nonvolatile memory 3 cannot receive data from the outside.

  Therefore, the nonvolatile memory 3 according to the present embodiment outputs a busy signal if the data input / output buffer 15 is in a state of holding data even when data is not being written to the memory cell. That is, the busy signal is asserted. This is a dummy busy function, and outputting a busy signal in the dummy busy function is hereinafter sometimes referred to as a dummy busy operation. As a result, the memory controller 4 can recognize that the nonvolatile memory 3 is in a state where it cannot receive data.

  The dummy busy function includes an operation of forcibly outputting (that is, asserting) a busy signal according to the state of the nonvolatile memory 3 in response to an instruction from the memory controller 4. That is, according to the dummy busy operation, the output of the busy signal is stopped when the data input / output buffer 15 is empty, even though the data is actually being written to the memory cell. That is, it is negated. However, in some cases, the memory controller 4 may need information on whether or not writing to the memory cell is actually being executed in the nonvolatile memory 3.

  In such a case, when there is a command from the memory controller 4 (hereinafter, this command is referred to as a switching command), the nonvolatile memory 3 outputs a busy signal according to the actual operation performed by itself. That is, if writing to the memory cell is being executed, the circuit 17 asserts a busy signal. In other words, it outputs a busy signal and notifies the memory controller 4 that it is busy. On the other hand, if writing has not been performed, the circuit 17 continues to negate the busy signal. In other words, the output stop of the busy signal is maintained, and the memory controller 4 is notified that it is in a ready state. The dummy busy function includes such an operation, and asserting or negating a busy signal in this operation may be hereinafter referred to as a true busy operation. The busy signal asserted in the true busy operation is negated when the writing to the memory cell is completed.

<Configuration of LSI 1>
Next, the configuration of the LSI 1 according to the present embodiment will be described with reference to FIG. FIG. 9 is a block diagram of a partial region of the LSI 1 according to the present embodiment, and particularly shows the backup control circuit 6 and the memory control unit 4.

<About the backup control circuit>
The configuration of the backup control circuit 6 is substantially the same as the configuration described with reference to FIG. 5 in the first embodiment. The difference from FIG. 5 is that the signal POWERON output from the memory controller 4 is input to the base of the bipolar transistor 43 instead of the output from the comparator 40, and the output from the comparator 40 is applied to the memory controller 4. It is. Other configurations and operations are the same as those in the first embodiment.

<About the memory controller 4>
Next, the memory controller 4 according to the present embodiment will be described. In addition to the functions described in the first embodiment, the memory controller 4 according to the present embodiment executes the true busy operation with respect to the nonvolatile memory 3 by generating the switching command and giving it to the nonvolatile memory 3. Order to do. Further, the signal POWERON is output in accordance with the comparison result of the comparator 40 received at the input terminal VLD_Mon, thereby controlling the bipolar transistor 43.

  Next, details of the operation of the memory controller 4 will be described with reference to FIG. FIG. 10 is a flowchart showing the operation of the memory controller 4, and particularly relates to the true busy operation and the output of the signal POWERON.

  As shown in the figure, the memory controller 4 confirms the busy signal (step S20), and if the busy signal is 'H' level (if negated: S21, NO), confirms the output of the comparator 40 (S22). ). If the output of the comparator 40 is 'L' level (S23, YES), a switching command is generated and output to the nonvolatile memory 3 (S24). That is, it instructs the nonvolatile memory 3 to perform a true busy operation. Then, the signal POWERON is set to the “L” level, and the bipolar transistor 43 is turned off (S25).

  If the output of the comparator 40 is 'H' level in step S23 (S23, NO), the memory controller 4 sets the signal POWERON to 'H' level (S26). Thereby, the bipolar transistor 43 is turned on.

  If the busy signal is 'L' level in step S21 (if asserted: S21, YES), the memory controller 4 checks the output of the comparator 40 (S27). If the output of the comparator 40 is 'H' level (S28, NO), the process of step S26 is performed. That is, the signal POWERON is set to the “H” level. On the other hand, if the output of the comparator 40 is 'L' level (S28, YES), the process proceeds to step S25. That is, the operation of the backup control circuit 6 according to the series of processes of steps S27, S28, and S25 and the series of processes of steps S27, S28, and S26 is the same as the operation in the first embodiment.

<Operation of memory system>
Next, the operation of the memory system according to the present embodiment will be described with reference to FIG. FIG. 11 is a time chart of signals output from the memory controller 4 to the non-volatile memory 3, showing commands and data output from the memory controller 4 to the non-volatile memory 3, busy signals, and operating states of the non-volatile memory 3. Yes.

  As shown in the drawing, first, the memory controller 4 outputs a command “80h” to the nonvolatile memory 3 at time t0. The command “80h” is a command for instructing the nonvolatile memory 3 to start a write operation. Subsequently, the memory controller 4 outputs an address to the nonvolatile memory 3 at time t1, and outputs write data at time t2.

  Next, the memory controller 4 outputs the command “15h” to the nonvolatile memory 3 at time t3. Command '15h' is an instruction to transfer write data from the data input / output buffer 14 to the data buffer in the bit line control circuit 12 and to program the write data in the data buffer into the memory cell.

  Then, in response to the command “15h”, the write data is transferred to the data buffer in the nonvolatile memory 3, and the program of the transferred write data into the memory cell is started. The control unit 17 performs a dummy busy operation and outputs a busy signal until the data input / output buffer 14 becomes empty. That is, the busy signal is set to the “L” level.

  Thereafter, when the data input / output buffer 14 becomes empty at time t5, the control unit 17 sets the busy signal to the 'H' level. Then, in response to the busy signal becoming “H” level, the memory controller 4 outputs a switching command to the nonvolatile memory 3. In response to the switching command, the nonvolatile memory 3 starts a true busy operation at time t6. At this time, since the program to the memory cell is being executed, the control unit 17 sets the busy signal to the ‘L’ level. After that, when the program ends at time t7, the busy signal becomes ‘H’ level.

<Effect>
As described above, according to the memory system according to the second embodiment, in addition to the effect (1), at least the following effects can be obtained.
(2) Operation reliability can be improved (part 2).
In the configuration according to the present embodiment, even in the memory system having the nonvolatile memory 3 having the dummy busy function, the power supply is cut off during the data writing to the memory cell as in the first embodiment. In this case, erasure and destruction of data can be prevented.

  In the memory system according to the present embodiment, the memory controller 4 generates a switching command when the power sources B and C are shut off when the nonvolatile memory 3 is in a ready state (busy signal = 'H'). Then, a busy signal is asserted to the nonvolatile memory 3. Then, if the nonvolatile memory 3 in the ready state is not being written, the busy signal is maintained at the “H” level. However, if the non-volatile memory 3 in the ready state is being written, the busy signal becomes ‘L’ level. Accordingly, the bipolar transistor 42 is turned on, and the voltage generated by the backup power supply 2 is supplied to the nonvolatile memory 3. Therefore, erasure and destruction of data are prevented. As a result, the operation reliability of the memory system can be improved as in the first embodiment.

  As described above, in the memory system according to the first and second embodiments of the present invention, when the power is cut off while the nonvolatile memory 3 is writing data, the voltage is supplied from the backup power supply. It is possible to prevent illegal termination of the write operation. Compared with the comparative example shown in FIG. 8, the power supply A can be eliminated by supplying the voltage supplied from the power supply C to the nonvolatile memory 3. That is, the number of external power supplies required by the memory system can be reduced, which also contributes to the solution of the problem that data is erased or destroyed during writing. In the above embodiment, the case where the comparator 40 is included in the backup control circuit 6 has been described as an example. However, the comparator 40 may be included in the memory controller 4.

  In the present embodiment, the case where the nonvolatile memory 3, the memory controller 4, the timer 5, and the backup control circuit 6 constituting the memory system are provided in the same LSI (Chip) is described. However, each component may be an independent LSI (Chip). That is, the memory system shown in FIG. 1 may be configured by a plurality of LSIs (Chips).

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of a memory system according to a first embodiment of the present invention. 1 is a block diagram of a nonvolatile memory according to a first embodiment of the present invention. 1 is a circuit diagram of a NAND flash memory according to a first embodiment of the present invention. 1 is a block diagram of a memory controller according to a first embodiment of the present invention. 1 is a block diagram of a backup control circuit according to a first embodiment of the present invention. 1 is a flowchart of a memory system according to a first embodiment of the present invention. FIG. 5 is a transition diagram of the operation of the memory system according to the first embodiment of the present invention. 1 is a block diagram of a memory system cited as a comparative example according to the first embodiment of the present invention. The block diagram of the memory system which concerns on 2nd Embodiment of this invention. 6 is a flowchart showing a process flow of a memory system according to the second embodiment of the present invention. The time chart which shows the flow of a process of the memory system which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory system, 2 ... Backup power supply, 3 ... Non-volatile memory, 4 ... Memory control part, 5 ... Peripheral circuit provided with timer function, 6 ... Backup control circuit, 11 ... Memory cell array, 12 ... Bit line control circuit, DESCRIPTION OF SYMBOLS 13 ... Column decoder, 14 ... Data input / output buffer, 15 ... Data input / output terminal, 16 ... Word line control circuit, 17 ... Control part, 18 ... Control signal input terminal, 20 ... NAND cell, 30 ... Memory interface, 31 ... RAM, 32 ... MPU, 33 ... HOST interface, 34 ... internal bus, 40 ... comparator, 41 ... switch control circuit, 42, 43 ... switch element, 44 ... switch circuit, 45 ... inverter, 46 ... NAND gate

Claims (5)

A semiconductor memory having nonvolatile memory cells capable of holding data; and
A backup control circuit for supplying either the first external voltage supplied from the first external power supply or the backup voltage supplied from the backup power supply to the semiconductor memory, and the backup control circuit is connected to the memory cell. The backup voltage is supplied to the semiconductor memory when the first external power supply is cut off during the data writing, and the supply of the backup voltage is stopped after the writing is completed. system. The semiconductor memory outputs a busy signal indicating that the data is being written while the data is being written to the memory cell,
The backup control circuit includes a comparator that compares a reference voltage with a second external voltage supplied from a second external power supply;
A switch circuit for connecting or disconnecting the backup power supply and the semiconductor memory;
As a result of comparison in the comparator, when the second external voltage is smaller than the reference voltage and the semiconductor memory is outputting the busy signal, the backup power supply and the semiconductor memory are connected to the switch circuit. And a switch control circuit for disconnecting the backup power supply and the semiconductor memory from the switch circuit when the output of the busy signal is stopped. The described memory system. A memory controller for controlling the operation of the semiconductor memory;
The memory system according to claim 1, wherein the semiconductor memory outputs a busy signal indicating that the data is being written to the memory controller while the data is being written to the memory cell. A control circuit connected to the backup power source and the first external power source and having a timer function;
The memory system according to claim 1, wherein the backup power supply supplies the backup voltage to the control circuit when the first external power supply is shut off. A memory controller for controlling the operation of the semiconductor memory;
The semiconductor memory includes a first buffer circuit that temporarily holds write data received from the outside;
A second buffer circuit for transferring the write data from the first buffer circuit and writing the write data into the memory cell;
A memory cell array in which the memory cells are disposed;
When the write data is held in the first buffer circuit, the busy signal is output, and when the write data is transferred to the second buffer circuit, the first buffer circuit becomes empty. A control circuit for stopping the output of the busy signal, and the memory controller, when the second external power supply is shut off while the semiconductor memory stops outputting the busy signal, 3. The memory system according to claim 2, wherein when the data is being written to the memory cell, the memory system is instructed to output the busy signal again.

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