JP4004659B2 - High voltage input interface circuit and semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high withstand voltage input interface technology, for example, a technology effective when applied to a flash memory which is an example of a semiconductor integrated circuit.
[0002]
[Prior art]
In a system in which a plurality of LSIs having different power supply voltages are mixed, it is necessary to have means for receiving an input amplitude larger than the power supply voltage supplied to the LSIs in order to enable signal exchange between such LSIs. Become. As such means, there is a method using an nMOS transistor for clamping. That is, an n-channel MOS transistor for clamping is provided between an input terminal and an input first stage circuit for capturing a signal input via the input terminal, and the gate electrode is coupled to the high potential side power supply Vdd. .
[0003]
As an example of a document describing a clamp circuit, there is “Nikkei Microdevice October issue, page 84” issued by Nikkei BP in 1992.
[0004]
[Problems to be solved by the invention]
FIG. 2 shows a circuit to be compared with the circuit according to the present invention.
[0005]
Three inverters 22, 23 and 24 are connected in series, and a clamping n-channel MOS transistor 21 is provided between the inverter 22, which is one of them, and the input terminal 20. The high-potential-side power supply Vdd is supplied to the gate electrode of the n-channel MOS transistor 21 for clamping. The input terminal 20 is supplied with a voltage exceeding the high potential side power supply Vdd (referred to as V1).
[0006]
While the input voltage Vin is 0 to Vdd−Vth (where Vth is the threshold voltage of the clamping n-channel MOS transistor), the clamping n-channel MOS transistor is turned on, and the voltage Vin ′ at the input terminal of the inverter 22 is , Equal to the input voltage Vin. When the input voltage Vin is in the range of (Vdd−Vth) to V1, the clamping n-channel MOS transistor 21 is turned off and Vin ′ = Vdd−Vth. The voltage Vin ′ applied to the inverter 22 at the first input stage is suppressed to Vdd−Vth even when the voltage V1 exceeding the high potential side power supply Vdd is supplied to the input terminal 20. In this manner, the action of the clamping n-channel type MOS transistor 21 prevents a voltage exceeding the high-potential-side power supply Vdd from being applied to the input gate of the inverter 22 at the first input stage. A gate breakdown voltage of 22 is ensured. Here, the circuit shown in FIG. 2 can withstand practical use when the threshold voltage of the MOS transistor is sufficiently small compared to the high-potential side power supply Vdd, but the LSI has been lowered in voltage and compared with the high-potential side power supply Vdd. If the threshold voltage of the MOS transistor is not sufficiently small, normal operation is not guaranteed.
[0007]
For example, by using an n-channel MOS transistor for clamping in an LSI of 3.3V process, an input / output buffer that accepts an input of 0 to 5V can be formed. When applied to this LSI, the voltage drop of the n-channel MOS transistor for clamping cannot be ignored, and the stable operation of the circuit cannot be guaranteed.
[0008]
An object of the present invention is to provide an interface technology capable of stable operation even when the voltage is lowered.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
That is, a clamping element (21) for clamping a signal input via the input terminal to a predetermined voltage level, and an input first stage circuit for capturing a signal transmitted from the input terminal via the clamping element (22) includes a pull-up circuit for raising the potential of the input terminal of the input first stage circuit to the power supply voltage level in accordance with a signal transmitted to the input first stage circuit. A control circuit (30) is provided.
[0011]
According to the above means, the pull-up control circuit raises the potential of the input terminal of the input initial stage circuit to the power supply voltage level in accordance with the signal transmitted to the input initial stage circuit. In spite of this, the stable operation of the circuit is achieved by completely turning off the p-channel MOS transistor that constitutes the input first stage circuit, although the voltage is lowered.
[0012]
At this time, the pull-up control circuit includes a resistor (R) coupled to a high potential side power supply, a p-channel MOS transistor (32) coupled to the resistor and an input terminal of the input first stage circuit, An inverter (31) for controlling the p-channel MOS transistor in accordance with a signal transmitted to the input first stage circuit can be configured.
[0013]
The operation timing of the pull-up control circuit can be optimized by setting the logic threshold voltage of the inverter to be lower than the logic threshold voltage of the input first stage circuit.
[0014]
By providing a capacitor (C) between the connection node of the resistor and the p-channel MOS transistor and the low-potential side power supply, the delay time characteristic at the rise of the waveform and the delay time characteristic at the fall of the waveform are matched. be able to.
[0015]
Furthermore, in the semiconductor integrated circuit provided with a buffer for taking in a signal from the outside and formed on one semiconductor substrate, the high withstand voltage input interface circuit can be applied as the buffer.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 shows an overall configuration example of a flash memory which is an example of a semiconductor integrated circuit according to the present invention.
[0017]
The flash memory 96 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
[0018]
MATU is the first memory mat 1, and MATD is the second memory mat 2. In order to distribute one word line load capacity in each of the memory mats 1 and 2, the word lines arranged at the same address are divided into two, and a sub-decoder 19 is assigned to each. Although not particularly limited, this flash memory is an effective flash memory when applied to a disk device compatible ATA file memory. A word line arranged at the same address has a memory cell of (2048 + 128) × 2 bits, which corresponds to a sector of 521 bytes and a sector management area of 16 bytes.
[0019]
Reference numeral 60 denotes a column circuit. The column system circuit 60 includes a sense latch and a Y system decode unit (described in detail later). Each of the column selection gates 6 and 7 is interfaced with eight pairs of common data lines 61, and the column decoder controls conduction between the eight pairs of common data lines 61 and the bit lines BLU and BLD according to a column address signal or the like. The common data line 61 includes non-inversion side common data lines IO0 to IO7 and inversion side common data lines / IO0 to 7 (/ means low active or signal inversion). A main amplifier (MA) 63 and an input / output buffer 64 are coupled. The input / output buffer 64 is interfaced with the outside via an external connection electrode (I / O) such as a bonding pad.
[0020]
The input / output buffer 64 is also used for input / output of memory data, input of address data, and input of command data. Write data to the memory cell is supplied to the common data line 61 via the output switching circuit 62. Read data from the memory mat is supplied to the main amplifier 63 via the input / output switching circuit 62, amplified there, and supplied to the input / output buffer 64.
[0021]
The address data supplied to the input / output buffer 64 is supplied to the address counter 65, and then supplied to the main decoder 17, the gate decoder 18, the column decoder, etc. via the address generator 66. Although not particularly limited, the address counter 65 has an initial value preset as address data, and is sequentially incremented according to an operation mode instructed to the flash memory by a command. The incremented address is output from the address generator 65. The memory mats 1 and 2 have spare bits realized by redundant word lines (not shown), etc., and the relief circuit 68 replaces the address of the defective bit with a redundant address according to the program state of the redundant fuse trimming circuit 67 to the address generator 66. This replaces defective bits with spare bits. The address generator 66 forms an internal complementary address signal according to the input, and assigns the address signal to the main decoder 17, the gate decoder 18, the column decoder, and the like.
[0022]
The data input / output control circuit 70 to which the serial click SC is supplied from the outside uses the main amplifier 63, the input / output switching circuit 62, and the input / output between the address counter 65 and the input / output buffer 64 as the serial clock SC. Synchronize.
[0023]
An external control signal is supplied to the control signal input buffer 71. The external control signal is supplied to the write enable signal WEB for instructing information input to the flash memory, the chip enable signal CEB for instructing operation of the flash memory, the output enable signal OEB for instructing information output of the flash memory, and the flash memory. A signal CED indicating whether the information to be processed is a command or data, and a reset signal RESB. The internal operation of the flash memory is synchronized with the clock signal output from the clock generator 72.
[0024]
The command supplied from the input / output buffer 64 is supplied to the command decoder 73. The command is a command related to reading (reading), writing (programming), and erasing (erasing) with respect to the memory cell. The contents specified by the program and the erase command include a verify operation. Internal control based on commands is a control method similar to so-called microprogram control. That is, the ROM holds a sequence of control codes (state information) for defining processing according to the command for each command. The decoding result of the command by the command decoder 73 is the head address in the ROM 75 of the control code series corresponding to the command. When the command decoding result is given to the ROM 75, the first control code of the control code series corresponding to the command is read from the ROM 75. The read control code is decoded by the ROM decoder 76, and an operation control signal is supplied to the write / erase determination circuit 80, the direct system control circuit 81, and the power supply control circuit 82. Designation of the second and subsequent control codes of the control code series is performed by the ROM control system circuit 74 based on the ROM address of the head control code. In consideration of conditional branching of the execution order of the control code, the ROM address of the next control code may be stored in the control code like the microprogram.
[0025]
The power control circuit 82 controls the operation power supply of various circuits necessary for the read, program and erase operations. The operation power supply includes, for example, a reference voltage generation circuit 85 that generates a reference voltage based on a band gap of silicon, and the like, and a charge pump circuit that generates a power supply such as −10 V using the reference voltage formed by the reference voltage generation circuit 85 84, and a power supply switching circuit 83 for switching the operation power supply of various circuits such as the main decoder in accordance with operations such as read, erase, and program. The write / erase determination circuit 80 is a circuit that determines completion of a write operation or an erase operation. The determination result is supplied to the ROM control system circuit 74 and reflected in the control contents in the control step next to the series of write operation or erase operation. The direct system control circuit 81 controls the word line selection timing and the column selection timing.
[0026]
Reference numeral 86 denotes a status register and test system circuit. The status register and test system circuit 86 can output the internal state of the flash memory to the outside via the input / output buffer 64, and a buffer 87. The ready / busy status is output to the outside via.
[0027]
FIG. 1 shows the main part of the input buffer for one bit in the input / output buffer 64.
[0028]
The input buffer shown in FIG. 1 is not particularly limited, but three inverters 22, 23, and 24 are connected in series, and an n-channel type for clamping is connected between the inverter 22 and the input terminal 20, which is one of them. A MOS transistor 21 is provided. The output signal of the inverter 24 is transmitted to the command decoder 73 and the input / output switching circuit 62 shown in FIG. A high potential side power supply Vdd is supplied to the gate electrode of the n-channel MOS transistor 21 for clamping. A pull-up control circuit 30 is provided for raising the potential of the input terminal of the input first stage circuit to the power supply voltage level in response to the signal Vin ′ transmitted to the inverter 22.
[0029]
The pull-up control circuit 30 is not particularly limited, but includes a resistor R coupled to the high potential side power supply Vdd, a p-channel MOS transistor 32 coupled to the resistor R and an input terminal of the inverter 22, and the inverter And an inverter 31 for controlling the p-channel MOS transistor in accordance with a signal transmitted to 22.
[0030]
Then, when the logic threshold voltage of the inverter 22 is VLT1 and the logic threshold voltage of the inverter 31 is VLT2, the logic threshold voltages of the inverters 22 and 31 are set so that VLT1> VLT2.
[0031]
In the above configuration, it is assumed that the input terminal 20 is supplied with a voltage exceeding the high potential side power supply Vdd (referred to as V1).
[0032]
When the input voltage Vin is in the range of 0 to VLT2, the following occurs.
[0033]
In this case, the clamping n-channel MOS transistor 21 is turned on and the pull-up p-channel MOS transistor 32 is turned off. In this state, the voltage Vin ′ input to the inverter 22 is equal to the input voltage Vin. That is, Vin ′ = Vin.
[0034]
When the input voltage Vin is in the range of the logic threshold voltages VLT2 to Vdd-Vth, both the clamping n-channel MOS transistor 21 and the pull-up p-channel MOS transistor 32 are turned on. At this time, a current flows from the high potential side power source Vdd toward the input terminal 20, but the value of this current is limited by the resistor R. Since the value of the resistor R is set to be much larger than the on-resistance of the clamping n-channel MOS transistor 21, the voltage drop due to the on-resistance of the clamping n-channel MOS transistor 21 can be ignored. it can. Therefore, Vin ′ = Vin.
[0035]
When the input voltage Vin is in the range of (Vdd−Vth) to V1, the clamping n-channel MOS transistor 21 is turned off and the pull-up p-channel MOS transistor 32 is turned on. When the pull-up p-channel MOS transistor 32 is turned on, Vin ′ = Vdd. In other words, when the voltage V1 having a level higher than that of the high potential side power source Vdd is supplied to the input terminal 20, the potential Vin ′ of the input terminal of the inverter 22 becomes equal to the level of the high potential side power source Vdd. No through current flows through 22. Further, even when the threshold voltage Vth and the logic threshold voltage VLT are increased due to a decrease in power supply voltage or process variations, the logic threshold voltage VLT2 of the inverter 31 is set to a sufficiently low value, so that the circuit Stable operation is guaranteed.
[0036]
Next, the operation of the capacitor C will be described.
[0037]
In the case where the capacitor C is not present, when the rising time and the falling time of the input voltage Vin are compared, the rising time of the input voltage Vin tends to be delayed more than the falling time. However, this is avoided as follows by providing the capacitor C between the connection node between the resistor R and the pull-up p-channel MOS transistor 32 and the low-potential-side power supply Vss.
[0038]
When a low level is input to the input terminal 20, the pull-up p-channel MOS transistor 32 is turned off, and the capacitor C is charged by applying the high potential side power supply Vdd. Then, the rising waveform is input to the input terminal 20 and the pull-up p-channel MOS transistor 32 is turned on, so that charges are supplied to the nodes from the high potential side power supply Vdd to the input terminals of the inverters 22 and 21. If this charging is left to the high potential side power supply Vdd only, it takes time to charge the nodes reaching the input terminals of the inverters 22 and 21 due to the presence of the resistor R. However, if the capacitor C is provided, the charge accumulated in the capacitor C when the pull-up p-channel MOS transistor 32 is turned off is generated when the pull-up p-channel MOS transistor 32 is turned on. In addition, since the voltage is quickly supplied to the nodes reaching the input terminals of the inverters 22 and 21 via the pull-up p-channel MOS transistor 32, the characteristics at the time of rising of the input voltage Vin are improved. Therefore, the delay time can be matched between the rising time and the falling time of the input voltage Vin.
[0039]
FIG. 3 shows operation waveforms by simulation of the circuit shown in FIG.
[0040]
Although the voltage Vin input to the input terminal 20 is higher than the high potential side power supply Vdd, it is clamped by the clamping n-channel MOS transistor 21 and pulled up by the pull-up control circuit 30. The high level is substantially equal to the high potential side power supply Vdd level. Note that, since the logic threshold voltage VLT2 of the inverter 31 is set lower than the logic threshold voltage VLT1 of the inverter 22, the inverter 31 shifts from the high level to the low level slightly earlier than the inverter 22. Also from this characteristic diagram, it can be seen that the circuit shown in FIG. 1 is stably operated.
[0041]
FIG. 5 shows a file system to which the flash memory 96 is applied.
[0042]
Reference numeral 90 denotes a flash memory card formed as a PC card, although not particularly limited, and is a kind of ATA (AT Attachment) card. The flash memory card 90 is detachably attachable to a computer 99 such as a personal computer via a connector (not shown) via a standard bus 91 compliant with IDE (Integrated Device Electronics).
[0043]
The flash memory card 90 includes a bus interface unit 92, a write buffer 93, an ECC circuit 94, a microcomputer 95, a flash memory 96, and a management table memory 97, which are commonly connected to an internal bus 98.
[0044]
The bus interface unit 92 performs interface control with the standard bus 91 so as to comply with the specifications of the ATA card or the like. The write buffer 93 is a data buffer that temporarily stores write data supplied from the standard bus 91, and the data stored in the write buffer 93 is written into the flash memory 96. The ECC circuit 94 is a circuit having an error detection and correction function for improving the accuracy of data stored in the flash memory 96. The management table memory 97 is composed of an electrically rewritable semiconductor memory such as a flash memory or an EEPROM, for example, and forms a sector management table and a rewrite count management table. The defective address of the flash memory 96 is written in the sector management table. In particular, in the case of a flash memory, it is necessary to retain such an address because the characteristics of the memory cell deteriorate while repeated writing / erasing. The rewrite count management table holds information for managing the rewrite count of the memory cell in the flash memory 96 for each block of the flash memory, for example. The characteristics of the memory cell of the flash memory are guaranteed within a predetermined number of rewrites. The microcomputer 95 generally controls the inside of the card in accordance with an access request to the flash memory card 90. For example, the microcomputer 95 issues an operation instruction for the flash memory or the command to control access to the flash memory 96 or control the management table memory 97. To do.
[0045]
According to the above example, the following effects can be obtained.
[0046]
(1) When the input terminal 20 is supplied with a voltage V1 having a level higher than that of the high potential side power source Vdd, the operation of the pull-up control circuit 30 causes the potential Vin ′ of the input terminal of the inverter 22 to be changed to the high potential side power source Vdd. Therefore, the p-channel MOS transistor constituting the inverter 22 can be completely turned off, and a through current can be prevented there. Thereby, stable operation of the circuit is achieved.
[0047]
(2) The operation timing of the pull-up control circuit 30 can be optimized by setting the logic threshold voltage of the inverter lower than the logic threshold voltage of the input first stage circuit.
[0048]
(3) Since the capacitor C is provided between the coupling node of the resistor R and the pull-up p-channel MOS transistor 32 and the low-potential side power supply Vss, the pull-up p-channel MOS transistor 32 is turned off. When the pull-up p-channel MOS transistor 32 is turned on, the electric charge accumulated in the capacitor C in this state is supplied to the input terminals of the inverters 22 and 21 via the pull-up p-channel MOS transistor 32. Supplied promptly to every node. Thereby, the delay time characteristic at the time of waveform rise and the delay time characteristic at the time of waveform fall can be matched.
[0049]
(4) In the flash memory 96 including the input / output buffer 64 having the above-described effects (1) to (3), even if the power supply voltage is lowered to, for example, 2.5 V, the power supply voltage is Signals from peripheral LSIs operating at 3.3V or 5V can be accurately captured.
[0050]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0051]
In the above description, the case where the invention made mainly by the present inventor is applied to the input / output buffer 64 of the flash memory 96, which is the field of use behind it, has been described. However, a buffer for fetching control signals and an address signal are fetched. It can be applied to various input buffers such as buffers.
[0052]
The present invention can be applied on the condition that it includes a clamping element for clamping a signal input via at least an input terminal to a predetermined voltage level.
[0053]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0054]
That is, the pull-up control circuit raises the potential of the input terminal of the input first stage circuit to the power supply voltage level, so that the p-channel MOS transistor constituting the input first stage circuit can be completely turned off, thereby stabilizing the circuit. Operation can be achieved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a configuration example of a high voltage input interface circuit according to the present invention.
FIG. 2 is a circuit diagram of a configuration example of a circuit to be compared with the high withstand voltage input interface circuit;
FIG. 3 is a characteristic diagram of a simulation result of the high voltage input interface circuit shown in FIG. 1;
4 is a block diagram illustrating a configuration example of a flash memory to which the high withstand voltage input interface circuit illustrated in FIG. 1 is applied;
5 is a block diagram illustrating a configuration example of a file system to which the flash memory illustrated in FIG. 4 is applied.
[Explanation of symbols]
20 Input terminal 21 Clamping n-channel MOS transistors 22, 23, 24, 31 Inverter 30 Pull-up control circuit 32 Pull-up p-channel MOS transistor R Resistance C Capacitor

Claims (4)

An n-channel MOS transistor for clamping a signal input via the input terminal to a predetermined voltage level;
An input first stage circuit for capturing a signal transmitted through the n-channel MOS transistor ;
Depending on the signal transmitted to the input first stage circuit, wherein the pull-up control circuit for raising the input electric position of the input first stage circuit to the high potential power supply voltage level,
The pull-up control circuit includes a resistor coupled to a high-potential side power supply, a p-channel MOS transistor coupled to the resistor and an input unit of the input first stage circuit, and a signal transmitted to the input first stage circuit. And an inverter for controlling the p-channel MOS transistor in response,
The logic threshold voltage of the inverter is set lower than the logic threshold voltage of the input first stage circuit,
2. A high withstand voltage input interface circuit , wherein a gate electrode of the n-channel MOS transistor is connected to the high potential side power source . When the voltage level of the high potential side power source is Vdd, the voltage exceeding the high potential side power source is V1, the threshold voltage of the n-channel MOS transistor is Vth, and the logical threshold voltage of the inverter is VLT2.
When the input voltage supplied to the input terminal is at a potential level between VLT2 and Vdd-Vth, both the n-channel MOS transistor and the p-channel MOS transistor are turned on,
2. The n-channel MOS transistor is turned off and the p-channel MOS transistor is turned on when an input voltage supplied to the input terminal is at a potential level between Vdd−Vth and V1 . High voltage input interface circuit. Between the coupling node and the low potential side power supply of the resistor and the p-channel type MOS transistor, the p-channel type MOS transistor is formed by providing a capacitor which is charged according to claim 1 or 2, wherein in the off state high Withstand voltage input interface circuit. 4. A semiconductor integrated circuit formed on a single semiconductor substrate with a buffer for taking in a signal from the outside, wherein the buffer comprises the high withstand voltage input interface circuit according to any one of claims 1 to 3. A semiconductor integrated circuit.

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