JPH0482094A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To realize the high efficiency of erasure operation by executing the erasure operation against a memory cell array in which nonerasure memory cell is detected when the memory cell in a nonerasure state is detected at the time of executing verification operation. CONSTITUTION:When the one word verification of respective memory cell arrays 1A and 1B is finished, an erasure verification control circuit 7' controls respective source line switches 9A and 9B when at least one of registers 60A and 60B is set based on the respective set/reset state of the registers 60A and 60B, and performs erasure pulse application operation to memory cell arrays 1 (1A, 1B) on a set register 60 side. Thus, the erasure operation can be efficiently performed without generating overerasure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device such as a flash EEPROM that can be electrically erased all at once.

[Conventional technology]

FIG. 3 is a block diagram showing the basic configuration of a conventional flash EEPROM disclosed in I5SCC Digest of Technical Papers (1990) PP, 60-61. In the figure, reference numeral 1 denotes a memory cell array, in which memory cells (not shown) consisting of memory transistors having floating gates are arranged in a matrix, word lines (not shown) are arranged in rows, and bit lines (not shown) are arranged in columns. (not shown). Word line selection is performed by a row decoder 2, and bit line selection is performed by a column decoder 3. When in the active state, the row decoder 2 activates the selected word line based on the row address Ar taken in from the address buffer 4, and makes the other word lines floating. On the other hand, in the inactive state, all word lines are made floating. Further, the column decoder 3 selectively turns on the Y gate 5 based on the column address Ac taken in from the address buffer 4 when in the active state, and electrically connects the write circuit 6 or the sense amplifier 8 to one end of one bit line. Connect to. The source line switch 9 sets the potential of a source line (not shown) according to instructions from the erase control circuit 7. and,
Row decoder 2, address buffer 4, write circuit 6
and sense amplifier 8 are controlled by erase control circuit 7.

Address buffer 4 takes in external address signals AO to Ak based on the control signal of erase control circuit 7, and outputs row address A' and column address Ac to row decoder 2 and column decoder 3, respectively. Sense amplifier 8 is in an active state. At times, the stored data of the memory cells (memory transistors) in the memory cell array 1 obtained through the Y gate 5 is detected and its sense output is provided to the people output buffer 10.The people output buffer 10 receives data from the outside. The obtained 1-byte input (output) data I/OO~l107 is given to the write circuit 6 as write data, or the data read from the sense amplifier 8 is used as 1-byte (human) output data l.
It is output to the outside as 100~T/07. Further, the sense output of the sense amplifier 8 is also given to the erase control circuit 7.

The erase control circuit 7 gives instructions to each component 2, 4, 6, and 8 in accordance with instructions from the mode control circuit 11, and controls the pre-erase write operation and erase operation, which will be described later. The mode control circuit 1 gives instructions to the erase control circuit 7 based on various control signals including an erase enable signal EE, a chip enable signal CE, an output enable signal OE, and a program signal PGM.

FIG. 4 shows the details of the erase control circuit 7 of the flash EE.
FIG. 2 is a block diagram showing the basic configuration of FROM. As shown in the figure, the erase control circuit 7 includes a command signal latch 71,
It is composed of a sequence control circuit 70 (decoder control circuit 72, erase pulse generator 73, erase/verify control circuit 74, address counter 75), a verify voltage generator 76, and a voltage switch 77. The command signal latch 71 latches a command from the mode control circuit 11. The latched contents of this command signal latch 71 are transmitted to the erase/verify control circuit 74 and the address counter 75.
will be forwarded to.

The erase/verify control circuit 74 is a command signal latch 7
If the content of the latch 1 is a command instructing erasure, it becomes active and controls the command signal latch 71, decoder control circuit 72, erase pulse generator 73, address counter 75, and helify voltage generator 76, respectively. Furthermore, during verification, the sense output of the sense amplifier 8 is taken in to detect whether the selected memory transistor is in the erased state or not. In the case of a command instructing erasure of the latched contents of the command signal latch 71, the address counter 75 becomes active and in accordance with instructions from the erase/verify control circuit 74, sequentially increments the address value and outputs the incremented address value to the address buffer 4.

Erase pulse generator 73 is erase/verify control circuit 74
An erase pulse is applied to the source line switch 9 according to the instruction. The decoder control circuit 72 gives instructions to the row decoder 2, such as activation of the row decoder 2 and the potential level of the selected word line, in accordance with instructions from the erase/verify control circuit 74. The verify voltage generator 76 outputs a reference voltage VR (lower voltage than the power supply VCo), which is an H level voltage at the time of verification, to the voltage switch 77. The voltage switch 77 selectively applies the reference voltage VR of the verify voltage generator 76 to the sense amplifier 8 and the row decoder 2. The details of the erase control circuit 7 have been described above.

Figure 5 shows the flash EEPR shown in Figures 3 and 4.
2 is a circuit configuration diagram showing the periphery of a memory cell array 1 of an OM. FIG. As shown in the figure, memory transistors 30 (nine in the figure) are arranged in a matrix in the memory cell array 1.
3
In LI to BL3, the control gates are commonly connected to the 7-t lines WL1 to WL3 in row units, respectively, and the sources are all connected to the source line SL. Bit line BL1~
One end of each of BL3 is connected to Y gates YGI-YG3, one end of each of word lines WLI-WL, 3 is connected to row decoder 2, and source line SL is connected to source line switch 9. Y gate YGI~YG3
are controlled to be on/off by the output of the column decoder 3, and word lines WLI to WL3 are controlled to be active/inactive by the row decoder 2 during writing and reading, respectively. In addition, Y Kate YGI to YG3 have I10 in common.
It is connected to a sense amplifier 8 and a write circuit 6 via a line IOL. In addition, in FIG. 5, the word line WL and the bit line BL
Although only one memory transistor 30 is selected by activating the The configuration is such that eight (1 byte) memory transistors 30 are selected at the same time.

FIG. 6 is a cross-sectional view showing the structure of the memory transistor 30 shown in FIG. In the figure, 31 is a P-type semiconductor substrate, 32 is an N-type drain diffusion region, and 33 is an N-type semiconductor substrate.
type source diffusion region.

These drain diffusion regions 32. The surface portion of the P-type semiconductor substrate 31 between the source diffusion regions 33 is defined as a channel region 38 . Further, 34 is a floating cage, which connects the source diffusion region 3 from above a part of the drain diffusion region 32.
A gate oxide film 35 having a thickness of approximately 100.8 cm is formed over a portion of the gate 3 through which tunnel linking is possible. Further, a control gate 36 is formed on the floating gate 34 with a gate oxide film 37 interposed therebetween.

The operation of the flash EEFROM having the above configuration will be explained below mainly with reference to FIG. For convenience of explanation, it is assumed that the matrix configuration of the memory cell array 1 is 3×3 as shown in FIG.

First, a write operation will be described using as an example a write to the selected memory transistor 30 surrounded by a dotted line in FIG. 5.

During writing, under the control of a writing control means (not shown),
The write circuit 6 is activated and high voltages V and P are applied to the I10 line IOL. Then, the column decoder 2 boosts only the gate of Y gate Y01 to high voltage VPP,
The gate of the other Y gate oxide film, YO2, is set to L.

Further, the row decoder 3 connects only the word line WLI to the high voltage V1. Pressure increases to Then, the source line SL is set to L (grounded) by the source line switch 9.

With this setting, the high voltage VPP is applied to the drain and control gate of the selected memory transistor 30, and the source is grounded. Therefore, electrons flowing through the channel region 38 of the memory transistor 30 are accelerated by the drain-source voltage in the pinch-off region near the drain diffusion region 32, and become hot electrons due to avalanche collapse. The injection across the gap into floating gate 34 increases the threshold of selected memory transistor 30 (7V or higher). This state is defined as a "0" write state.

Next, the erase operation will be explained. The erase operation is performed on all memory transistors 30 at once, and under the control of the erase control means 7, the source line switch 9 switches the source line SL
is boosted to high voltage VPP, column decoder 2 applies L to the gates of all Y gates YG1 to YG3, and row decoder 3 sets all word lines WL1 to WL3 to L.

With this setting, all memory transistors 30
The drain of V1. is floating, the control gate is grounded, and the source is connected to a high voltage V1. is applied. Therefore, a high electric field is applied to the gate oxide film 35, and electrons accumulated in the floating gate 34 are extracted to the source diffusion region 33 due to a tunneling phenomenon, thereby lowering the threshold value of the memory transistor (about 1-V). In other words, the state is the same as that of an EFROM erased by ultraviolet rays. This state is defined as a "1" writing state.

Note that this operation is just an erase pulse application operation that is one of the erase operations, and in reality, the erase operation is a combination of the pre-erase write operation and the verify operation, which will be described later.

Next, the read operation will be described using as an example reading of the data stored in the selected memory transistor 30 surrounded by the dotted line in FIG.

Under the control of a readout control means (not shown), the column decoder 2 sets only the gate of the Y gate YG1 to H (power supply V
・approximately 5v) and other YK CC.

The gates of YG2 and YG3 are set to L. In addition, the row decoder 3 sets only the word line WLI to H,
Another word line WL2. Set WL3 to L. and,
The source line switch 9 grounds the source line SL.

With this setting, H is applied to the control gate of the selected memory transistor 30, and the source is grounded. Therefore, when "0" is stored in the selected memory transistor 1, the selected memory transistor 30 maintains the OFF state, so the selected memory transistor 30 is connected to the I10 line 1 via the bit line BLI.
If no current flows from 0L to the source line SL and "1" is stored in the selected memory transistor 30, the selected memory transistor 30 is turned on, so the bit line B
A current flows from the I10 line 10L to the source line SL via LI. The sense amplifier 8 detects the presence or absence of this current flow.
By detecting the selected memory transistor 3
Data stored in 0 can be read.

By the way, when the electrons accumulated in the floating gate are excited by ultraviolet rays and removed from the floating gate, as in ultraviolet erasing in EFROM, the emission of electrons ends when the floating gate becomes electrically neutral. On the other hand, the above-mentioned flash EEPRO
When the tunneling phenomenon is used for the erase operation as in M, if the erase time is long, the electrons accumulated in the floating gate 34 are extracted excessively and the floating gate 3
4 may become positively charged. When floating gate 34 becomes positively charged, the threshold voltage of memory transistor 30 becomes negative. This kind of over-erased memory transistor is always on, and leakage current flows through this over-erased memory transistor, making it impossible to read out the memory transistor that shares the bit line BL with the over-erased memory transistor. . Furthermore, even during writing, leakage current flows through over-erased memory transistors, which deteriorates the writing characteristics.
In the worst case, it becomes impossible to write.

Therefore, during the erase pulse application operation described above, the high voltage v1. The width of the erase pulse to be applied is shortened, and each time the erase pulse is applied, the data stored in all the memory transistors 30 is read out, and it is determined whether all the memory transistors 30 are in the erased (“1” written) state. Execute the verify operation to be confirmed in parallel. Thereafter, the erase pulse application operation and the verify operation are repeated, and once the erased state of all memory transistors 1 is confirmed by the verify operation, the erase operation is immediately terminated.

In this manner, by performing the verify operation in addition to the erase pulse application operation performed using a short erase pulse, generation of over-erased memory transistors is prevented. Such erase pulse application operation and verify operation (hereinafter referred to as
The erase operation with an automatic erase function consisting of the "erase/verify operation"
This is generally executed when erasing M.

Furthermore, the automatic deletion function will be explained in detail. After a high voltage "PP" with a pulse width of 10 m5 is generated from the source line switch 9 and an erase pulse application operation is executed, a verify operation is executed.The verify operation is generated by the address counter 75 in the erase control circuit 7. Based on the address signal selected by the selected address signal, the row decoder 2
Then, the memory contents of the memory transistor selected by the column decoder 3 are read out, and erase verification is performed in units of bytes.

The verify operation is performed on all memory transistors, but if it detects the existence of a memory transistor with a high threshold, that is, an unerased memory transistor, the address of that memory transistor is memorized, the verify operation is performed immediately, and the erase pulse application operation is started again. After that, the verify operation is executed again from the previously stored address. This is to perform the verify operation efficiently and shorten the erasing time.

Then, the erase/verify operation continues until the threshold values of all memory transistors have become low during the verify, that is, it is determined that they have been erased. When it is confirmed that all memory transistors have been erased normally, the erase/verify control circuit The command signal latch 71 is activated by the reset instruction of 74.
The process ends when H is output as the status signal SS.

Furthermore, before performing the erase/verify operation, a pre-erase write operation is performed. By this pre-erase write operation, "0" is written to all memory transistors and the threshold value is increased. By performing this pre-erase write operation, it is possible to avoid erasing a memory transistor with a low threshold value and causing over-erasing. This pre-erase write operation is performed by the address counter 75 in the erase control circuit 7.
The address signals are sequentially sent to the address buffer 4 from
The erase/herify control circuit 74 controls the row decoder 2.
, by appropriately controlling the column decoder 3 and the write circuit 6, the write operation is performed in the same manner as the write operation described above.

A full erase operation is executed by this pre-erase write operation and the erase/herify operation described above.

[Invention or problem to be solved]

Conventional non-volatile semiconductor memory devices, such as flash EEPROMs, that require an erase operation with an erase-to-reify function are configured as described above, and the erase operation consists of a pre-erase write operation and an erase/verify operation. was going through the motions.

By the way, the pulse width required for erasing (
There are variations in the erase characteristics, such as variations in the high voltage VPP application time. Therefore, when the erasure of the memory transistor that was the most difficult to erase is completed, the memory transistor that was the easiest to erase ends up being over-erased.

In order to alleviate this problem, the memory cell array within one chip is divided into multiple blocks, and the erase pulse application operation can be executed independently for each block, thereby minimizing the possibility that the memory transistors will become over-erased. There are ways to prevent this. In this case, the heli-verify operation is performed in parallel in units of one byte for each block in order to shorten the erase verify time.

When divided into blocks, the memory transistors in each block are verified in parallel in 1-byte units, and if an unerased memory transistor is detected, an erase pulse is applied or applied only to the memory cell array of the block where the unerased memory transistor is located. will be done.

However, if the erase pulse operation is applied independently for each block in this way, the number of memory transistors to be erased in one erase pulse application operation will be reduced. The number of applications (time) increases. For example, there are unerased memory transistors in memory cell array A and memory cell array B, and due to the difference in the addresses of these memory transistors, only the unerased memory transistors in memory cell array A are processed first in the verify operation performed in 1-byte units. When detected, the memory cell array A is erased by the erase pulse application operation that is executed subsequently.
Therefore, the erase operation of memory cell array B is not performed. Then, the erasing operation of the memory cell array B is finally performed when an unerased memory transistor of the memory cell array B is detected during the subsequent verify operation.

As described above, when a memory cell array is divided into a plurality of blocks in order to avoid over-erasing, there is a problem in that the erasing pulse application time and, by extension, the erasing time become longer.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can efficiently perform erasing operations without overerasing.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cells each having a floating gate and consisting of an electrically writable and erasable memory transistor, and the plurality of memory cells are divided into blocks to form a plurality of memory cells. A memory cell array is configured and reads and writes to and from the outside in units of a predetermined number of bits, and erasing means executes an erasing operation to erase the memory contents of memory cells in all of the plurality of memory cell arrays at the time of erasing; After the erase operation, performing a verify operation to verify whether the memory cells of each of the memory cell arrays have been erased in units of a number of bits exceeding the predetermined number of bits;
When an unerased memory cell is detected by the heli-fi operation, the erase verify means executes an erase operation only for the memory cell array in which the unerased memory cell is detected.

[Effect]

The erase verifying means in this invention performs the following operations after the erase operation:
A heliify operation is performed to verify whether or not each memory cell in the memory cell array has been erased in units of bits exceeding a predetermined number of bits, which is the bit length of input/output data during reading and writing. When an unerased memory cell is detected, the erase operation is performed only on the memory cell array in which the unerased memory cell is detected. Therefore, if there is an unerased memory transistor in the memory cell array, a single verify operation The probability of detecting an unerased memory transistor is higher than that in the unit of the predetermined number of bits.

[Embodiment] Fig. 1 shows a flash EEPR which is an embodiment of this invention.
FIG. 2 is a block diagram showing the basic configuration of OM.

As shown in the figure, the memory cell array IA is divided into two parts.
and IB exist independently.

In each memory cell array IA and IB, memory cells (not shown) consisting of memory transistors having floating gates are arranged in a matrix, with word lines (not shown) in rows and bit lines (not shown) in columns. (not shown). Word line selection is done by row decoder 2A,
Selection of bit lines 2B and 2B is performed by selectively turning on Y-gates 5A and 5B by column decoders 3A and 3B, respectively. When row decoders 2A and 2B are in an active state, they selectively activate word lines based on the row address A' fetched from the address buffer 52. On the other hand, when in an inactive state, all word lines are made floating. Column decoder 3A.

3B selectively controls the Y gates 5A and 5 based on the column address Ar fetched from the address buffer 51 in the active state.
Turn B on and off.

Address buffer 51 receives external column address signal AC as well as internal column address signal ac from address counter 53, and according to instructions from erase control circuit 7', internal column address signals a and C are sent during erasing, and internal column address signals a and C are sent at other times. External row address signal AC is output as column address signal Ac to column decoders 3A and 3B. On the other hand, the address counter 52 receives the external row address signal AR as well as the internal row address signal ar from the address counter 54, and according to instructions from the erase control circuit 7', the internal row address signal ar is sent during erasing and the internal row address signal ar is sent at other times. External row address signal AR is output to row decoders 2A and 2B as row address signal Ar.

In addition, the column address A fetched from the address buffer 51
Based on c, column decoders 3A and 3B selectively turn on Y gates 5A and 5B, respectively, to write circuits 6A and 6B or sense amplifiers 8A and 8B and memory cell array IA.

One end of each bit line of IB is electrically connected.

Source line switches 9A and 9B set potentials of source lines (not shown) according to instructions from erase control circuit 7'.

Sense amplifiers 8A and 8B each output Y at the time of reading.
Memory cells (memory transistors) in memory cell arrays IA and IB obtained through gates 5A and 5B, respectively
Detects the stored data in register 6 as a sense output.
0A and 60B, respectively, and also to the human output buffer 62 via the multiplexer 61. Also,
The write circuits 6A and 6B also each have a multiplexer 61.
is connected to the human output buffer 62 via. The multiplexer 61 is provided to selectively connect the human output buffer 62 and one of the sense amplifiers 8A and 8B during reading, and to selectively connect the human output buffer 62 and one of the write circuits 6A and 6B during writing. . The erase control circuit 7' is substantially equivalent to the erase control circuit 7 shown in the conventional example shown in FIGS. 3 and 4 except that the address counter 75 is removed.

In such a configuration, the write operation is performed almost in the same manner as in the conventional case. That is, hot electrons generated by avalanche breakdown are injected into the floating ink of the memory transistor selected by the row decoder 2A or 2B and the column decoder 3A or 3B of either the memory cell array IA or IB selected by the multiplexer 61-. , "0" is written and the threshold voltage becomes high.

Next, the erase operation will be explained.

First, a pre-erase write operation is performed, and the threshold values of all memory transistors are set high as in the conventional case.

Then, an erase pulse application operation is executed.

The erase pulse application operation is similar to the conventional one, in which the erase pulse is applied to the memory cell array IA via the source line switches 9A and 9B.
This is done by applying a high voltage VPP to the sources of all memory transistors of each IB.

Then, the erase/verify operation is executed under the control of the erase control circuit 7'. First, the erase control circuit 7' activates the (column) address counter 53 and outputs the internal column address aC to the address buffer 51. and,
The output of the address buffer 51 is the memory cell array IA,
The Y gates 5A and 5B are selectively turned on and off to select a column of memory transistors in each memory cell array IA and IB. At the same time, the row address counter 54 is also activated by the erase control circuit 7' and outputs the internal row address ar to the address buffer 52. Then, by applying the output of the address buffer 52 to the row decoders 2A, 2B of the memory cell arrays IA, 1B, a row of memory transistors in each memory cell array IA, IB is selected. At this time, address buffer 51. ．． External row and column address signals AR, AC input externally to 52 are ignored.

As a result, one memory transistor is selected in each memory cell array IA, IB, and the storage contents of this selected memory transistor are detected by sense amplifiers 8A, 8B. Thereafter, the value of the row address ar output from the address counter 54 is fixed, and the column address aC output from the column address counter 53 is sequentially incremented, and each memory cell array IA
.

Parallel processing is performed in each of 1B, and the stored contents of the memory transistors in the same row (connected to one word line) are sequentially detected by sense-up circuits 8A and 8B. Hereinafter, this will be referred to as one-wide verify eye operation.

During this period, sense outputs from each sense amplifier 8A, 8B are sequentially applied to registers 60A, 60B. The initial state of the registers 60A and 60B is a reset state, and they are set when at least one row-by-row sense output instructs to store "0" (unerased).

After that, when one word verification of each of memory cell arrays IA and IB is completed, erase verification control circuit 7
' is based on the set/reset status of registers 60A and 60B, respectively, and
If 0B is set, source line switches 9A, 9
The erase pulse application operation is performed only to the memory cell array 1 (IA, IB) on the set register 60 side by controlling each of B. For example, register 60A.

Of 60B, the register 60A is in the set state (that is, all of the read memory transistors in one row are in the erased state), and the register 60B is in the set state (that is, at least one of the read memory transistors in one row is in the unerased state). ), the erase pulse application operation is performed with only the source line switch 9B activated and the source line switch 9A inactivated. Then, when the erase pulse application operation is finished, a one-word verify operation is performed on the word line as in the previous time.

On the other hand, if both the registers 60A and 60B have been reset, the address counter 54 increments the row address ar by 1 according to the instructions from the erase verify control circuit 7', and the incremented row address ar is used to generate one word in the selected word line. Execute a double-verify operation.

Thereafter, since a one-word verify operation is not performed, each time an unerased memory transistor is detected, an erase pulse application operation is performed only to the memory cell array 1 in which the unerased memory transistor exists.

In this way, when the 17-verify operation for the final row address ar is completed, the entire erase operation is completed.

In this way, one helify operation for each memory cell array divided into multiple parts is performed for each memory transistor connected to one word line, instead of the conventional one-byte unit. , the detection sieve r of unerased memory transistors becomes extremely high, and as a result, the erase pulse can be applied efficiently to the memory cell array of each block. For example, if there are unerased memory transistors in each of memory cell array IA and memory cell array IB, even if the addresses of these memory transistors are different, if the memory transistors are in the same row, the memory cell array IA will be erased by the same verify operation.
It is detected whether the memory transistors A and IB are unerased,
The subsequent erase pulse application operation can be applied to both memory cell arrays IA and IB.

By the way, if one verify operation is performed in units of memory transistors connected to one word, it naturally takes time for one verify operation, so the erase pulse application operation that can be executed within a limited time takes that amount of time. It is assumed that the number of executions will decrease.

FIG. 2 shows the number of word lines connected to memory transistors that are simultaneously helified in one helifi operation (hereinafter referred to as "helifi word lines").

) is a graph showing the maximum number of times Y of erasing pulse application (operation executable) with respect to X.

In the figure, the memory cell array of each block has 256 column addresses and 1024 row addresses, the time required to read 1 byte of memory transistor is 200 ns, and the time to apply one erase pulse is 1.
This is a graph calculated from the following equation (1) based on the restriction that the erase/verify operation is executed within 1 second when the distance is 0 m5.

1(see)=lO(ms)*Y+256*200(n
s)*1024+258*200(ns)*X*(Y-
1) =11) In equation (1), the left side is the total erase operation time, the first term on the right side is the erase pulse application operation time, the second term on the right side is the initial verify operation time, and the third term on the right side is the period after re-erasing. This is the time for the second and subsequent Herifi operations.

As shown in FIG. 2, as the number of verify word lines X increases, the maximum number of erase pulse applications Y decreases;
The rate of decrease is low until X = 16 and Y - 90,
Considering that the conventional maximum erase pulse application number Y per one hide unit is approximately 100, this has not decreased much. Therefore, even if the number of verify word lines X is increased up to about 16 lines, the disadvantage that the maximum number of erase pulse applications Y decreases can be kept to an almost negligible level. On the other hand, as the probability of detecting an unerased memory transistor in one verify operation increases,
The erasing pulse application operation can be performed efficiently, which in turn leads to increased efficiency of the entire erasing operation.

In this embodiment, one verify operation was performed for each word line, but instead of each word line, one word line is subdivided and the memory transistors connected to the subdivided partial words are The helifi operation may be performed in units of multiple bytes such as numbers.

In addition, in this embodiment, the verification operation of the memory transistors of each block is performed in parallel or sequentially for each block, and after storing the verification results in the corresponding registers, it is determined whether or not to perform re-erasing. You may also do so.

Further, in this embodiment, one verify operation is performed in units of word lines (in units of rows), but it may also be configured to be performed in units of bit lines (in units of columns).

Although a flash EPROM is shown as the nonvolatile semiconductor memory device in this embodiment, the present invention is not limited to this, and can be applied to all nonvolatile semiconductor memory devices that require a heli-fi operation after erasing.

〔Effect of the invention〕

As described above, according to the present invention, after the erase operation, the erase verify means determines whether or not each memory cell in the memory cell array has been erased using a predetermined bit length of input/output data during reading and writing. If a verify operation is performed to verify the number of bits exceeding the number of bits, and an unerased memory cell is detected during the verify operation, the erase operation is performed only on the memory cell array in which the unerased memory cell was detected. Execute.

Therefore, if there is an unerased memory transistor in the memory cell array, the probability of detecting an unerased memory transistor during one verify operation is higher than when performing the verification operation in units of the predetermined number of bits, so that the erase operation can be performed efficiently. It can be performed.

[Brief explanation of drawings]

Figure 1 shows a flash EFRO which is an embodiment of this invention.
FIG. 2 is a graph showing the relationship between the number of vertical lines and the maximum number of erase pulses applied. FIG. 3 is a block diagram showing the basic configuration of a conventional flash EPROM. FIG. 3 is a block diagram showing the details of the erase control circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing the details of the memory cell array shown in FIGS. 3 and 4, and FIG. 6 is the memory cell array shown in FIG. 5. FIG. 2 is a cross-sectional view showing the structure of a transistor. In the figure, LA and IB are memory cell arrays, 2A
2B is a row decoder, 3A and 3B are column decoders, 7
' is an erase control circuit, 8A, 8B are sense amplifiers, 9A,
9B is a source line switch, 51.52 is an address buffer, 53.54 is an address counter, and 60A and 60B registers. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 2

Claims (1)

[Claims] (1) A plurality of memory cells each having a floating gate and consisting of an electrically programmable and erasable memory transistor are provided, and the plurality of memory cells are divided into blocks to form a plurality of memory cell arrays, and a predetermined A non-volatile semiconductor memory device that performs external read and write operations in units of bits, comprising an erase unit that executes an erase operation to erase the memory contents of memory cells in all of the plurality of memory cell arrays during erasing; After the operation, a verify operation is performed to verify whether or not the memory cells of each of the memory cell arrays have been erased in units of a number of bits exceeding the predetermined number of bits, and when an unerased memory cell is detected by the verify operation. , and erase verification means for performing an erase operation only on the memory cell array in which the unerased memory cell is detected.