JPH04132087A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize the efficiency design of circuit block area and low power consumption by incorporating a high voltage generation circuit generating the high voltage for write-in in a first nonvolatile generation storage block and commonly utilizing the high voltage to a second nonvolatile storage block. CONSTITUTION:The high voltage necessary for write-in to memory elements Y11 to Y22 is formed by a high voltage generation circuit VPPG equipped with a nonvolatile storage circuit MC2. In short, though the high voltage generation circuit VPPG is incorporated in one nonvolatile storage circuit MC2, it is commonly used in the other nonvolatile storage circuit MC1. Thus, the occupancy area of the nonvolatile storage part can be formed small by the sharing of the high voltage generation circuit VPPG, and the high voltage generation circuit VPPG includes an oscillation circuit and a boosting circuit so that its power consumption can become relatively high, the power consumption can be remarkably reduced comparing with the case providing the nonvolatile storage circuits MC1 and MC2 respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device. It's about technology.

[Conventional technology]

There is an l-chip microcomputer with a built-in EPROM (erasable and programmable read-only memory). As for such a one-chip microcomputer with a built-in EFROM, there is, for example, 'HD6301YJ' sold by Hitachi, Ltd.

[Problem to be solved by the invention]

The inventor of the present application considered developing a large-scale integrated circuit equipped with a plurality of EFROMs depending on the type of stored data. That is, by using EFROM-, the development period from program development to product completion can be shortened, and new products with desired circuit functions can be brought to market quickly.

A single-chip microcomputer as described above has a single built-in EFROM. However, as the required functions become more complex, EPROMs are also available in multiple types depending on the content of the stored information, such as programs indicating data processing procedures and data tables such as coefficients and variables corresponding to the data to be processed. It becomes necessary.

An object of the present invention is to provide a semiconductor integrated circuit device that has a plurality of nonvolatile memory blocks and achieves efficient design of circuit block area and low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a high voltage generation circuit that generates a high voltage for writing is built into the first nonvolatile memory block, and the high voltage is commonly used for the second nonvolatile memory block as well.

[For production]

According to the above-mentioned means, a high voltage generation circuit with a relatively large current consumption and occupied area can be shared, so it is possible to efficiently design the circuit block area and reduce consumption in a semiconductor integrated circuit device equipped with a plurality of nonvolatile memory blocks. Electricity can be realized.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a nonvolatile memory section configured in a semiconductor integrated circuit device according to the present invention. Each circuit block in the same figure.

It is formed together with other circuit blocks (not shown) on a single semiconductor substrate such as, but not limited to, single-crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The nonvolatile memory section of this embodiment is composed of two nonvolatile memory circuits MCI and MC2. One nonvolatile memory circuit MC2 is divided into two memory arrays MARY21 vertically centered around decoder DCR2 in the figure.
．． 22, and input/output circuits 11021.22 provided corresponding to each of the memory arrays MARY21.22.

The input/output circuit 11021.22 is connected to the memory array MA
A column switch is used to connect the data line selected by the address decode output of the column system from among the data lines corresponding to RY21.22 to the common data line to which the output terminal of the actual input circuit and the input terminal of the output circuit are coupled. It includes.

The control circuit C0NT receives an address signal supplied from the address bus AB and a control signal supplied from the control bus CB, and when it detects the address input assigned to the nonvolatile memory circuit MC2 from the address of the upper bit, it responds to the address signal supplied from the address bus AB and the control signal supplied from the control bus CB. The address of the lower bits is supplied to the decoder DCR2, and the memory array MARY21.
22 selection operations are performed. In addition, the operation mode such as write/read or verify is identified from the control signal,
Timing signals necessary for each operation are generated and transmitted to the selected memory array MARY21.22 and the corresponding input/output circuit l1021.22.

In an EFROM, when writing data to a memory cell, a high voltage is applied to the gate and drain electrodes of the memory element, and hot electrons generated due to the potential gradient between the source and drain are injected into the floating gate. By injecting electrons into the floating gate, the threshold voltage of the memory element is increased, and the threshold voltage of the memory element in which no electrons are injected is kept low. and “1
” corresponds to

In this embodiment, a high voltage generating circuit V provided internally generates the high voltage necessary for writing to the memory element.
Generated by PPG. This high voltage generation circuit VPPG
It is operated with a relatively low operating voltage of about 5V, and uses a built-in oscillation circuit or a periodic pulse signal such as the system clock of the semiconductor integrated circuit device in which it is mounted to perform charge sharing with the capacitor. A high voltage of about 15V is generated by a booster circuit using . By incorporating such a high voltage generating circuit VPPG, it is possible to eliminate the need for externally supplying a high voltage during the above-described write operation to the memory element.

In the semiconductor integrated circuit device of this embodiment, in order to diversify functions, etc., the nonvolatile memory section described above includes a nonvolatile memory used to store data of a different type from the nonvolatile memory circuit MC2. A circuit MCI is provided. This nonvolatile memory circuit MCI is a decoder DCR in the same figure.
Two memory arrays M divided vertically with 1 at the center
ARY11.12 and each of the above memory arrays MARY11
Input/output circuit 11011゜1 provided corresponding to ゜22
Contains 2. The input/output circuit 11011゜12 is
A column that connects the data line selected by the address decode output of the column system from among the data lines corresponding to the memory arrays MARY11 and MARY11 to the common data line to which the output terminal of the actual input circuit and the input terminal of the output circuit are coupled. It includes a switch.

The high voltage necessary for writing into the memory element as described above is generated by the high voltage generating circuit VPPG provided in the nonvolatile memory circuit MC2. That is, although the high voltage generation circuit VPPG is built in one nonvolatile memory circuit MC2, it is also commonly used for other nonvolatile memory circuits MCI. By sharing the high voltage generating circuit VPPG in this way, the area occupied by the nonvolatile memory section can be made small.

Since the high voltage generation circuit VPPG includes the oscillation circuit and booster circuit as described above, it consumes relatively large amount of power. Therefore, power consumption can be significantly reduced compared to the case where each of the nonvolatile memory circuits MC1 and MC2 is provided. and,
The high voltage generating circuit vpPG follows the periodic pulse signal as described above.

In order to charge and discharge a capacitor having a relatively large capacitance value, a relatively large pulse noise is generated at the ground potential point of the circuit and the power supply voltage line during the boosting operation. By sharing the high voltage generating circuit VPPG as described above, the above-mentioned pulse noise can be reduced and the operation can be stabilized.

In this embodiment, the address identification function of the control circuit C0NT provided in the nonvolatile memory circuit MC2 also identifies the address selection operation of the other nonvolatile memory circuit MCI. Nonvolatile memory circuit MCI from the upper bit of the address
When detecting the address assigned to
is supplied to the address decoder DCR1 of the address decoder DCR1 to perform an address selection operation on the nonvolatile memory circuit MCI side.

At this time, the operation mode such as write/read or verify is identified by the control signal supplied from the control bus CB, and timing signals necessary for each operation are generated, and the selected nonvolatile memory circuit MCI side The information is transmitted to the memory array MARY11-12 and the corresponding input/output circuits 11011 and 12.

By sharing the control circuit C0NT in this manner, the operation mode identification circuit, timing generation section, etc. can be made common, thereby making it possible to simplify the circuit.

Furthermore, the system addresses assigned to each of the nonvolatile memory circuits MC1 and MC2 are made such that they do not overlap, as shown in the address map of FIG. Therefore, there is no problem even if the control circuit C0NT as described above is shared. 'Also, in this embodiment, the nonvolatile memory circuit M
A dummy area is provided between CI and MC2. This dummy area is provided so that it can be used when increasing the storage capacity of the nonvolatile memory circuit MCI or MC2 due to changes or expansions in functionality.

Write operations are performed using an EFROM writer. In this case, as described above, two nonvolatile memory circuits MC
By assigning consecutive addresses to I and MC2 with a dummy area in between, the EPROM writer can perform writing and verification while apparently viewing them as one non-volatile memory circuit. That is, the nonvolatile memory circuit MCI is assigned addresses 0 to J, and the nonvolatile memory circuit MC2 is assigned addresses K to L, but by making the addresses continuous including the dummy area, address 0 is assigned. It can be regarded as one non-volatile memory circuit to which address spaces from to L are allocated. As a result, the nonvolatile memory circuit MCI
Since the write operations of MC2 and MC2 can be performed all at once by the EPROM writer, the write operation can be simplified. In such a write operation, no problem arises even if the high voltage generating circuit (PPG) as described above is shared.

The effects obtained from the above examples are as follows. That is, (1) a first nonvolatile memory circuit (block) has a built-in high voltage generation circuit that generates a high voltage for writing;
By using the same high voltage second non-volatile memory block, the high voltage generating circuit, which consumes relatively large current and occupies a large area, can be shared.
It is possible to achieve the effect of realizing efficient design of circuit block area and reduction of power consumption in a semiconductor integrated circuit device including a plurality of nonvolatile memory blocks.

(I) According to (1) above, only one high voltage generating circuit is required, which generates relatively large pulse noise during boosting operation, so that the operation can be stabilized.

(3) By sharing the control circuit, it is possible to simplify the circuit.

(4) By allocating consecutive addresses to a plurality of nonvolatile memory circuits via a dummy area, it is possible to easily write data using a program writer.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the number of nonvolatile memory circuits (blocks) may be three or more, instead of two as described above. In this case, as mentioned above, a booster circuit or control circuit is provided only in one nonvolatile memory circuit,
By making it common to other non-volatile memory circuits, it is possible to achieve even more efficient design of the occupied area and lower power consumption. It goes without saying that the above-mentioned EFROM may be a package in which the erasing function is disabled in the semiconductor integrated circuit device in which it is mounted, or the erasing window may be omitted. Even when using a one-time writing method, as mentioned above, the development period from program development to product completion can be shortened and the desired circuit I! It is possible to bring new products with high performance to the market as soon as possible. The nonvolatile memory circuit may be EEPROM (Electrically Erasable & Programmable Read Only Memory) in addition to EFROM.

The above-mentioned non-volatile memory circuit includes multiple types of basic blocks that are configured as macro cells and have built-in high voltage generation circuits and control circuits, and multiple types of expansion blocks that are configured as macro cells and have high voltage generation circuits and control circuits omitted. Various types of non-volatile storage units can be configured by combining one basic block and an extended block.

The present invention can be widely used in semiconductor integrated circuit devices including a plurality of nonvolatile memory circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by incorporating a high voltage generation circuit that generates a high voltage for writing into the first nonvolatile memory circuit and using it in common for the high voltage second nonvolatile memory circuit, it is possible to Since the high voltage generation circuit, which consumes a large amount of current and occupies a large area, can be shared, it is possible to realize an efficient design of the circuit block area and a reduction in power consumption in a semiconductor integrated circuit device equipped with a plurality of nonvolatile memory circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a non-volatile memory section provided in a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a memory map diagram showing an embodiment of address assignment thereof. MCI, MC2...Nonvolatile memory circuit, MARY11~
22...Memory array, DCRI, DCR2...Address decoder, l1011-22...I/O circuit, C0N
T: Control circuit, VPPG: High voltage generation circuit.

Claims (1)

[Scope of Claims] 1) A first nonvolatile memory block incorporating a high voltage generation circuit that generates a high voltage for writing, and the second nonvolatile memory block, the first nonvolatile memory block A semiconductor integrated circuit device characterized in that a high voltage generated by a high voltage generation circuit provided in a memory block is also commonly used for a second nonvolatile memory block. 2) The above-mentioned first and second non-volatile memory blocks are configured into macro cells, and are configured into one semiconductor integrated circuit together with macro cell circuit blocks having other circuit functions. A semiconductor integrated circuit device according to claim 1. 3) The first nonvolatile memory block is provided with a control circuit that is commonly used for a plurality of nonvolatile memory blocks mounted on a semiconductor integrated circuit device. A semiconductor integrated circuit device according to scope 1 or 2.