JPH0357049A - Microcomputer incorporating eeprom - Google Patents

Abstract

PURPOSE:To shorten the time required for backup by setting a flag corresponding to each address of a backup area on a RAM at the time of rewriting corresponding RAM data. CONSTITUTION:An address decoder 5 decodes the write address value to a RAM 7, and a flag register 6 to which the AND signal between the output of this decoder 5 and a write signal WB is inputted has bits corresponding to respective addresses of the backup area of the RAM 7. Consequently, the pertinent bit of the flag 6 is set only when data in the backup area is rewritten. The state of the flag 6 is tested in an EEPROM write interrupt routine, and data in the backup area to which set bits of the flag 6 correspond are read out, and the write instruction to an EEPROM 2 is executed, and the flag 6 is reset, and only rewritten parts in the backup area are always transferred to the EEPROM 2 by this programming. Thus, the time required for backup at the time of the occurrence of a break of power is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to electrically erasable non-volatile memory (EEPRO).
Regarding a single Chisso microcomputer with a built-in M).

[Conventional technology]

Conventionally, microcomputers with a built-in EEPROM (hereinafter referred to as microcomputers) have been configured to
EEPROM erase operation is started, and after a fixed erase time (usually about 5 msec) has elapsed, a write operation is started, and the write operation is performed for a fixed write time (usually about 5 msec). Write to EPROM.

[Problem to be solved by the invention]

The conventional EEPROM built-in microcomputer described above requires about 10 msec to write one byte, so it takes a very long time to write a large amount of data into the EEPROM. For example, in the case of a single-chip microcontroller, when the power is cut off, the
There are many cases where approximately 0 bytes of data is backed up. In this case, 100 bytes of data are transferred from RAM to EEP.
To transfer to ROM, 10ms x 100 bytes = I
Seconds of time are required. Therefore, in the conventional EEPROM microcomputer, data cannot be backed up unless the voltage applied to the microcomputer is maintained for at least one second after the power is turned off. The capacitor capacity required for this purpose is, for example, 10 mA for the current consumption of the microcontroller, and 0.5 V for the power supply voltage drop tolerance (the drawback is that it requires a large capacity that can operate even if the power supply voltage drops from 5 V to 4.5 µA). be.

As a countermeasure to this problem, it is possible to always transfer data in the area of RAM to be backed up to EEPROM, but it is difficult to know which data has been transferred to EEPROM, and EEPROM has a limit on the number of times it can be rewritten (usually 10,000 to 100,000 times), and a method of constantly writing is not practical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer with a built-in EEPROM that can shorten the time required for backup in the event of a power outage and is practical for limiting the number of times the EEPROM can be rewritten.

[Means to solve the problem]

The microcomputer of the present invention has EEPROM and RA.
A microcomputer incorporating M on the same chip has a flag corresponding to each address of the predetermined area of the RAM, and corresponds to the address when a write operation is performed to the predetermined area of the RAM. The present invention is characterized by comprising a flag register in which the flag is set, and means for writing data written in the predetermined area of the RAM to the EEPROM in response to the flag being set.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a book diagram for explaining a first embodiment of the present invention. The CPUI performs processing according to the contents of a program memory not shown in the figure. EEPROM2
are written and read by the CPU via the internal bus 4. The write control circuit 3 is an EEPROM2
When a write command is executed, an erasing operation of the EEPROM is started, the time required for erasing is measured, and after the erasing time has elapsed, a writing operation is started, and the time required for writing is measured, After the writing time has elapsed, the end of writing is notified to the CPU by an interrupt or the like. Address decoder 5 decodes the write address value to RAM 7. The flag register 6 which receives the AND signal of the output and the write signal (WR) has bits corresponding to the addresses of the backup area of the RAM 7, respectively. Therefore, when writing to RAM 7 is performed, 60 bits of the flag register corresponding to the written address are set. Flag 6 is CP via internal bus.
Writing/reading can be performed by U1. According to this structure, the corresponding bit of flag 6 is set only when data in the backup area is rewritten. Therefore, the state of flag 6 is tested in the EEPROM write interrupt routine, and if any bit is set, the data in the backup area corresponding to that bit is read, the write command to EEPROM 2 is executed, and flag 6 is set. If you program it to be reset, only the rewritten RAM in the backup area will become EE.
It will always be transferred to PROM2, and EEPROM
It is possible to provide a practical means for limiting the number of rewrites described in 2. In addition, it is possible to check which data in the backup area has been transferred to EEPROM2, so even if a power outage occurs, only the data that has not been transferred can be transferred to EBFROM.
2, the data backup time can be significantly reduced. In FIG. 1, it is preferable to read the flag 6 at a bit length that can be processed by the CPU 1, such as 8 bits, or 16 bits, so that a plurality of bits can be read out at once. This is because if flag 6 is tested bit by bit sequentially, the processing of the EEPROM write interrupt routine becomes long and the processing capacity of the CPU 1 is reduced. For example, when all bits are reset, there is a difference in processing time of approximately 16 times between testing each bit and reading every 16 bits.

FIG. 2 is a block diagram for explaining a second embodiment of the present invention. OR gate 8 outputs the logical sum of all outputs of flag 6. The AND gate 9 outputs the logical product of the output of the OR gate 8 and the signal IO indicating that the write control circuit 3 is not writing, and the output is CPtJ1.
is transmitted as an interrupt signal. According to this structure, when any of the flags 6 is set by rewriting any of the RAMs in the backup area, and no writing is performed to the EEPROM 2, an interrupt etc. occurs. By CPU1
can know that there is data to be transferred from the backup area to the EEPROM2. In the first embodiment, even if the backup is completed, the state of the flag 6 must be tested periodically, but in the second embodiment, once the backup is completed, the state of the flag 6 must be tested until the output of the AND gate 9 becomes active. This has the advantage of being able to greatly alleviate the reduction in processing power of the CPU 1 due to backup processing to the EEPROM 2.

〔Effect of the invention〕

As explained above, the present invention has a flag 6 corresponding to each address of the backup area on RAMT, and sets the flag 6 when the corresponding RAM data is rewritten. The data in the memory can be periodically saved to the EEPROM, so most of the data can be saved while the power is on, reducing the time required for backup in the event of a power outage. This has the effect of significantly reducing capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention, and FIG. 2 is a block diagram for explaining a second embodiment of the present invention. 1...CPU, 2...EEPROM,
3...Write control circuit, 4...Internal bus, 5...Address decoder, 6...
Flag, 7...RAM, 8...OR gate, 9...AND gate.

Claims (1)

[Claims] In a microcomputer that incorporates an EEPROM and a RAM on the same chip, there is a flag corresponding to each address of a predetermined area of the RAM, and when a write operation is performed to the predetermined area of the RAM, the flag is set to that address. a flag register in which the corresponding flag is set; and a flag register in which the corresponding flag is set;
The data written in the predetermined area of the EEPROM
An EEPROM characterized in that it has means for writing into the EEPROM.
Built-in microcomputer.