JPH08286998A - Address setting method, board and data processing system - Google Patents

Abstract

PURPOSE: To provide a board in which no address setting by the use of a DIP switch is required. CONSTITUTION: The addresses directed to themselves of the boards 21, 22, 23 are '0'. It is assumed that the address '2' is outputted from a CPU 20. The board 21 judges this address not to be directed to itself because the address is not '0', and also, it subtracts '1', and delivers the address '1' to the board 22. The board 22 subtracts similarly '1' from the given address, and delivers the address '0' to the board 23. The board 23 judges the address to be directed to itself because the address is '0', and executes the transfer of prescribed data in conformity with an instruction. Similarly, on the assumption that the addresses '0', '1' are outputted from the CPU 20, the boards 21, 22 judge the address to be directed to itself respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory board or an I / O board for determining whether or not an address given from a CPU via an address bus is an address addressed to itself.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional example of this type of board. When the address given to the address bus 42 and the address preset by the DIP switch 49 match, the address match detection circuit 45 determines that the address of the address bus 42 is addressed to itself. When it is determined that the address is addressed to itself, the gate circuit 46,
In accordance with the instructions RD and WR, 48 causes the buffer circuit 47 to exchange data with the data bus 44.

[0003]

In the above-mentioned conventional board, since the address of each board is individually set by the DIP switch, setting mistakes or forgetting of settings are likely to occur. Therefore, an object of the present invention is to provide a board that does not require address setting without using a DIP switch or the like.

[0004]

According to the address setting method of the present invention, when passing an address to the next board in a memory or an I / O board having a function of discriminating an address connected in cascade, this address has a constant value. By adding or subtracting with, the address is determined at the insertion point of the board. In the board of the present invention, the input end is connected to the input side address bus and the output end is connected to the output side address bus, and a predetermined value is added to or subtracted from the address input from the input side address bus to output the output side address bus. An address calculation circuit for outputting to the bus, an address judgment circuit for judging whether or not the address input from the input side address bus is addressed to itself, and an address judgment circuit for judging that the address is addressed to itself Has a processing circuit for exchanging data with the data bus and for performing a predetermined process.

[0005]

The self-address of each board is the same, and when connected in cascade, the address received by the head board undergoes an operation such as subtraction in each board. When the address reaches the corresponding board, the address is the self-address and the corresponding board accepts the access.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data processing system in which three boards of the present invention are connected in cascade, and FIG. 2 is a block diagram showing an internal circuit of the board. Via the connection buses 31, 32, 33, the board 21,
22 and 23 are connected to the CPU 20 in cascade. Since the boards 21, 22 and 23 have the same configuration, the board 22 shown in FIG. 2 will be taken as an example to explain the internal circuit of the board. The full adder circuit 1 has an input end connected to the input side address bus 2 and an output end connected to the output side address bus 3, respectively, and subtracts “1” from the address given via the input side address bus 2 to output Output to the side address bus 3. The address output from the board 22 is given to the input side address bus of the board 23 via the connection bus 33.

In the gate circuit 5, the address given to the input side address bus 2 is a predetermined value (in this embodiment, it is "0", so that it will be explained according to this example).
When it becomes, it judges that the address is addressed to itself and outputs "0". When the gate circuit 6 determines that the gate circuit 5 is addressed to itself and receives the read command RD, the gate circuit 6 switches the buffer circuit 7 to the data fetching state and transfers the data on the data bus 4 to the first via the buffer circuit 7. It is taken into the internal circuit 8 (input port). When the gate circuit 9 judges that the gate circuit 5 is addressed to itself and receives the write command WR, the buffer circuit 7 enters the data output state, so that the second internal circuit 1
Data of 0 (output port) is output to the data bus 4 via the buffer circuit 7.

On the input end side of the board 22,
The input side address bus 2, the data bus 4, and the control lines to which the read instruction and the write instruction are given are the connection bus 32.
On the output end side of the board 22, the output side address bus 3, the data bus 4, and the control line to which the read command and the write command are given are connected to the connection bus 33. Next, the operation of the embodiment shown in FIG. 1 will be described. It is assumed that the address “2” is output from the CPU 20. Since the address is not "0", the board 21 determines that this address is not addressed to itself, subtracts "1" by the full adder 1, and passes the address "1" to the board 22. Similarly, the board 22 subtracts "1" from the given address and passes the address "0" to the board 23. Since the given address is "0", the board 23 determines that the address is addressed to itself and according to the instruction,
Exchange of predetermined data is performed via the data bus 4.

[0009]

As described above, according to the present invention, it is not necessary to set individual addresses for a plurality of boards connected in a cascade with a dip switch or the like, and a setting error is eliminated. Further, since the same board may be used, it is only necessary to replace it with another board at the time of maintenance, and the maintenance can be performed in a short time and the reliability of the maintenance is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing system in which three boards of the present invention are connected in a cascade.

FIG. 2 is a block diagram showing an internal circuit of the board of the embodiment of FIG.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Full Adder 2 Input Address Bus 3 Output Address Bus 4 Data Bus 5, 6, 9 Gate Circuit 7 Buffer Circuit 8 First Internal Circuit 10 Second Buffer Circuit 20 CPU 21, 22, 23 Board 31, 32, 33 Connection bus

Claims (4)

[Claims] 1. A board characterized in that when an address or a memory I / O board having a function of discriminating an address connected in cascade is passed to the next board, addition or subtraction by a constant value is performed on this address. Address setting method that determines the address at the insertion point. 2. The input end is connected to the input side address bus, and the output end is connected to the output side address bus. The address input from the input side address bus is added or subtracted by a predetermined value and output to the output side address bus. Address calculation circuit for determining whether the address input from the input side address bus is addressed to itself, and the address determination circuit determines that the address is addressed to itself. A board having a processing circuit for exchanging data with the bus and performing a predetermined process. 3. The processing circuit is a memory circuit or an I / O.
The board according to claim 2, which is a circuit. 4. A data processing system in which a plurality of the boards according to claim 2 or 3 are connected in cascade.