JPH0828503B2 - MOS semiconductor device - Google Patents
MOS semiconductor deviceInfo
- Publication number
- JPH0828503B2 JPH0828503B2 JP63121104A JP12110488A JPH0828503B2 JP H0828503 B2 JPH0828503 B2 JP H0828503B2 JP 63121104 A JP63121104 A JP 63121104A JP 12110488 A JP12110488 A JP 12110488A JP H0828503 B2 JPH0828503 B2 JP H0828503B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- conductivity type
- region
- base layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000010410 layer Substances 0.000 claims description 103
- 239000000758 substrate Substances 0.000 claims description 27
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 230000002441 reversible effect Effects 0.000 description 9
- 238000011084 recovery Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、第一導電形の半導体基板の表面層に設けら
れた第二導電形ベース層の表面層にさらに第一導電形の
ソース層を設け、そのソース層と半導体基板の表面に露
出している第一導電形の層との間のベース層部分にチャ
ネルが生ずるように絶縁膜を介して形成される格子状の
ゲートが同一半導体基板上に設けられるゲートパッド部
と連結されていて、ゲート入力端子と接続されるMOS型
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a surface layer of a second conductivity type base layer provided on a surface layer of a semiconductor substrate of a first conductivity type, and a source layer of a first conductivity type. And a lattice-shaped gate formed through an insulating film so as to form a channel in the base layer portion between the source layer and the layer of the first conductivity type exposed on the surface of the semiconductor substrate is the same semiconductor. The present invention relates to a MOS semiconductor device connected to a gate pad portion provided on a substrate and connected to a gate input terminal.
近年電力用スイッチング素子として、自己整合拡散法
により電力用たて型MOSFETがその用途を広げており、市
場が急激に拡大している。第２図の左の部分は、通常の
電力用MOSFETの構造を示し、n-層１とn+層11からなるシ
リコン基板の表面層に高抵抗のp-層21と低抵抗のp+層22
からなるｐベース層２が設けられ、その表面にn+ソース
層３が形成されている。ｐベース層２のソース層３とn-
層１の間のp-層21の部分がチャネル領域となるもので、
ゲート酸化膜４を介して形成される多結晶Si層５がゲー
トとして働く。ソース層３の一部およびその間のp+層22
にはPSG層６の中のコンタクトホール61でAlからなるソ
ース電極７が接触している。図示しないがドレイン電極
はn+層11に接触している。このようなMOSFETが一つのシ
リコン基板内に多数形成されており、図示のMOSFETはそ
のうちの外周部に配置されたものである。このMOSFETの
ゲート多結晶Si層５は、酸化膜４の上に一面に形成され
た多結晶Si層をパターンニングしたもので、他のMOSFET
のゲート多結晶Si層と連結され、第２図の右の部分に相
当する基板の外周部の１個所でソース電極７と同様、PS
G層６の中のコンタクトホール62でAlからなるゲート電
極８に接触している。このゲート電極８がゲートパッド
部を形成する。外周部にあるMOSFETのソース電極７直下
のp+ベース層22は、ゲートパッド部の下側へも延在して
形成されている。なお、実際の製造工程では、ソース層
３はゲート多結晶シリコン層５のパターンをマスクにし
て自己整合により拡散形成される。In recent years, as a power switching element, a power vertical MOSFET is expanding its application by the self-aligned diffusion method, and the market is rapidly expanding. The left part of FIG. 2 shows the structure of a normal power MOSFET, in which a high resistance p − layer 21 and a low resistance p + layer are formed on the surface layer of the silicon substrate consisting of n − layer 1 and n + layer 11. twenty two
Is provided, and an n + source layer 3 is formed on the surface of the p base layer 2. source layer 3 of p base layer 2 and n −
The part of p − layer 21 between layers 1 becomes the channel region,
The polycrystalline Si layer 5 formed via the gate oxide film 4 functions as a gate. Part of the source layer 3 and the p + layer 22 between them
The source electrode 7 made of Al is in contact with the contact hole 61 in the PSG layer 6. Although not shown, the drain electrode is in contact with the n + layer 11. A large number of such MOSFETs are formed in one silicon substrate, and the illustrated MOSFETs are arranged on the outer peripheral portion thereof. The gate polycrystalline Si layer 5 of this MOSFET is formed by patterning the polycrystalline Si layer formed on the entire surface of the oxide film 4, and the
In the same way as the source electrode 7, PS is connected to the gate polycrystalline Si layer of the
The contact hole 62 in the G layer 6 is in contact with the gate electrode 8 made of Al. This gate electrode 8 forms a gate pad portion. The p + base layer 22 immediately below the source electrode 7 of the MOSFET on the outer peripheral portion is formed so as to extend to the lower side of the gate pad portion. In the actual manufacturing process, the source layer 3 is diffused by self-alignment using the pattern of the gate polycrystalline silicon layer 5 as a mask.
電子機器においては、過渡的な過電圧の可能性を完全
に除くのは困難である。大電流を高速で開閉する電力用
MOSFETでは、その電流変化率が数百A/μｓにも達し、僅
かな非クランプインダクタンスにも大きなスパイク電圧
を発生させ、ｐベース層２とN-基板１の間のPN接合の降
伏電圧を超えるので、アバランシェ領域でそのエネルギ
を吸収する必要が生じてきている。またパルス幅変調に
よるモータ駆動のように、電力用MOSFETの内蔵ダイオー
ドを積極的に使用する場合、このダイオードの逆回復時
に流れる電流に耐える必要がある。従来の電力用MOSFET
では、第２図に示すようにゲートパッド部直下にp+ベー
ス層22と同時にp+領域23が形成されており、通常ソース
電極と接続されていて、過電圧が加わった時のゲートパ
ッド近傍の電界集中を防止するようにしている。しか
し、この構造では、アバランシェ領域におけるゲートパ
ッド部直下の空乏層領域体積が大きく、この空乏層の充
電電流がｐベース層２とn-層１との間のPN接合によって
生ずる空乏層を通じてソース電極７に集中し、アバラン
シェ耐量を低下させる。また内蔵ダイオードを動作させ
た場合、ゲートパッド部直下のp+領域23に蓄積した正孔
電流が大きく、またこの正孔の吸い出し口になるソース
電極が遠いため、電流集中が増大し、逆回復耐量が低下
するという問題がある。In electronic equipment, it is difficult to completely eliminate the possibility of transient overvoltage. For electric power that opens and closes large current at high speed
In the MOSFET, the current change rate reaches several hundred A / μs, a large spike voltage is generated even with a slight unclamp inductance, and exceeds the breakdown voltage of the PN junction between the p base layer 2 and the N − substrate 1. Therefore, it is necessary to absorb the energy in the avalanche region. Further, when the diode built in the power MOSFET is positively used as in the case of driving a motor by pulse width modulation, it is necessary to withstand the current flowing when the diode reversely recovers. Conventional power MOSFET
Then, as shown in FIG. 2, the p + region 23 is formed at the same time as the p + base layer 22 immediately below the gate pad portion, which is normally connected to the source electrode, and in the vicinity of the gate pad when an overvoltage is applied. The electric field concentration is prevented. However, in this structure, the volume of the depletion layer region directly under the gate pad portion in the avalanche region is large, and the charging current of this depletion layer is generated by the PN junction between the p base layer 2 and the n − layer 1 and the source electrode is formed through the depletion layer. Concentrate on 7, reduce avalanche resistance. In addition, when the built-in diode is operated, the hole current accumulated in the p + region 23 directly below the gate pad is large, and the source electrode serving as the hole for discharging this hole is far, so current concentration increases and reverse recovery occurs. There is a problem that the withstand capacity is reduced.
本発明の課題は、上述の問題を解決し、ソース，ドレ
イン間の電圧に対するアバランシェ耐量および内蔵ダイ
オードの逆回復時の電流耐量の増大したMOS型半導体装
置を提供することにある。An object of the present invention is to solve the above problems and to provide a MOS type semiconductor device in which the avalanche withstand voltage against the voltage between the source and the drain and the current withstand voltage during reverse recovery of the built-in diode are increased.
上記の課題の解決のために、本発明は、第一導電形の
基板中の表面層に設けられた第一導電形の基板中の表面
層に設けられた第二導電形の島状のベース層の表面層に
さらに第一導電形の環状のソース層を設け、該ソース層
と半導体基板表面に露出している第一導電形領域との間
のベース層部分をチャネル領域としてその上に絶縁膜を
介してゲートが設けられるものにおいて、前記ベース層
は縦横の行列状に配置された多角形の複数領域であり、
該複数領域からなるベース層の外周側に第二導電形の環
状領域が配置され、該第二導電形の環状領域は、内周側
で前記複数領域と対峙する部分に凸部が設けられている
ものとする。あるいは、第一導電形の基板中の表面層に
設けられた第二導電形の島状のベース層の表面層にさら
に第一導電形の環状のソース層を設け、該ソース層と半
導体基板表面に露出している第一導電形領域との間のベ
ース層部分をチャネル領域としてその上に絶縁膜を介し
てゲートが設けられるものにおいて、前記ベース層は縦
横の行列状に配置された多角形の複数領域であり、該複
数領域からなるベース層の外周側に第二導電形の環状領
域が配置され、前記ゲートは前記第二導電形の複数領域
を取り囲むように格子状に形成されており、かつ該ゲー
トが同一半導体基板の前記第二導電形の環状領域より外
側の外周上の一部に設けられるゲートパッド部下まで延
在して、該ゲートパッド部と絶縁層を介して重ねられて
おり、そしてゲートパッド部とゲートとの一部が接触し
て電気的に連結されており、さらにゲートパッド部直下
のゲートに空乏層容積制限のための切断部を設け、少な
くとも該切断部下の半導体基板の表面領域は第一導電形
の不活性領域とするとよい。In order to solve the above problems, the present invention provides a second conductivity type island-shaped base provided on a surface layer of a first conductivity type substrate provided on a surface layer of a first conductivity type substrate. An annular source layer of the first conductivity type is further provided on the surface layer of the layer, and a base layer portion between the source layer and the first conductivity type region exposed on the surface of the semiconductor substrate is insulated as a channel region. In the case where a gate is provided through a film, the base layer is a plurality of polygonal regions arranged in rows and columns.
A second-conductivity-type annular region is arranged on the outer peripheral side of the base layer composed of the plurality of regions, and the second-conductivity-type annular region is provided with a convex portion on a portion facing the plurality of regions on the inner peripheral side. Be present. Alternatively, an annular source layer of the first conductivity type is further provided on the surface layer of the island-shaped base layer of the second conductivity type provided on the surface layer of the substrate of the first conductivity type, and the source layer and the semiconductor substrate surface. In which a gate is provided via a base layer portion between the exposed first conductivity type region as a channel region and an insulating film thereover, the base layer is a polygon arranged in a matrix in vertical and horizontal directions. A plurality of regions, a second conductivity type annular region is arranged on the outer peripheral side of a base layer composed of the plurality of regions, and the gate is formed in a lattice shape so as to surround the plurality of second conductivity type regions. And the gate extends below the gate pad portion provided on a part of the outer periphery of the second conductivity type annular region of the same semiconductor substrate, and is overlapped with the gate pad portion via an insulating layer. And the gate pad section The gate immediately below the gate pad portion is provided with a cutting portion for limiting the volume of the depletion layer, and at least the surface region of the semiconductor substrate below the cutting portion is formed into a first region. An inactive region of one conductivity type is preferable.
ゲートパッド部直下のベース層を縦横の行列状に配置
された多角形の複数領域とし、複数領域からなるベース
層の外周側に第二導電形の環状領域が配置されているの
で、環状領域により外周での電界集中が生じにくくな
り、かつ内側全体の複数領域が行列状であるので、内側
の全ての複数領域に均等に電界集中点を分散することに
よって、アバランシェ耐量と内蔵ダイオードの逆回復耐
量が高められる。そして、大きな面積部分に第二導電形
の層がないので、第二導電形のベース層と第一導電形の
半導体基板との空乏層はそこまで広がらず、空乏層領域
の体積は大幅に軽減し、アバランシェ電流、充電電流あ
るいは逆回復電流の集中が避けられる。しかし、ゲート
パッド部の内側でゲート電極に接触する導電性ゲート層
がフィールドプレートの働きをするので空乏層はその部
分までは広がり、耐圧が保持できる。The base layer immediately below the gate pad portion is made into a plurality of polygonal regions arranged in a matrix in the vertical and horizontal directions, and the second conductivity type annular region is arranged on the outer peripheral side of the base layer composed of the plurality of regions. Since the electric field concentration on the outer circumference is less likely to occur and the multiple areas on the entire inner side are arranged in a matrix, the avalanche resistance and the reverse recovery resistance of the built-in diode are distributed by evenly distributing the electric field concentration points in all the inner areas. Is increased. Since there is no layer of the second conductivity type in the large area, the depletion layer between the base layer of the second conductivity type and the semiconductor substrate of the first conductivity type does not spread to that extent, and the volume of the depletion layer region is greatly reduced. However, concentration of avalanche current, charging current or reverse recovery current can be avoided. However, since the conductive gate layer in contact with the gate electrode inside the gate pad portion functions as a field plate, the depletion layer spreads to that portion and the breakdown voltage can be maintained.
第１図は本発明の一実施例の電力用MOSFETのゲートパ
ッド部近傍の断面を示し、第２図と共通の部分には同一
の符号が付されている。第１図は第３図のＡ−Ａ線の部
分断面図である。第１図において、ｐベース層２は島状
にシリコン基板１の表面に複数設けられ、その表面に環
状のn+ソース層３が形成されている。そして、ゲートと
して働く多結晶Si層５は島状のｐベース層２を取り囲む
ように格子状の連続した層となっている。このうちゲー
トパッド部付近のｐベース層２はゲートパッド側がp+層
22となっており、このp+層22が環状部24につながってい
る。第３図は縦横の行列状に配置されたp+層22の分布を
示し、p-層21,ソース層３を省略してあるが、これらはp
+層22の部分に第２図のように形成される。第３図でゲ
ートパッド部の直下領域80には存在しない点が第２図と
異なり、各ソース電極に接触する部分にのみ存在し、外
周部では環状部24で連結されており、内側のp+層22に対
峙した部分が凸状となっている。そして、ゲートパッド
部の周辺において、ゲート電極８に接触する多結晶Si層
５がフィールドプレートの働きをし、ｐベース層２とn-
シリコン基板に逆バイアスがかかったときの空乏層領域
をこのフィールドプレートの下まで広げることにより耐
圧を保持するものである。空乏層容積の制限のため、多
結晶Si層には切断部51が設けられ、シリコン基板のゲー
トパッド部のない部分で各ゲート多結晶Si層と連結され
て基板外周をとり囲む多結晶Si層とほぼ同じ幅にされ
る。切離された多結晶Si層52はチャネルストッパとして
用いる。ゲートパッド部直下にはPN接合がないのでアバ
ランシェ電流も発生しないし、逆回復時にもダイオード
として全く動作しないので、アバランシェ耐量および逆
回復耐量を増大させることができる。FIG. 1 shows a cross section in the vicinity of a gate pad portion of a power MOSFET according to an embodiment of the present invention, and portions common to FIG. 2 are designated by the same reference numerals. FIG. 1 is a partial sectional view taken along the line AA of FIG. In FIG. 1, a plurality of p base layers 2 are provided in an island shape on the surface of a silicon substrate 1, and an annular n + source layer 3 is formed on the surface. The polycrystalline Si layer 5 serving as a gate is a continuous lattice-shaped layer surrounding the island-shaped p base layer 2. Of these, the p base layer 2 near the gate pad portion is the p + layer on the gate pad side.
22 and this p + layer 22 is connected to the annular portion 24. FIG. 3 shows the distribution of the p + layers 22 arranged in a matrix in the vertical and horizontal directions, and the p − layer 21 and the source layer 3 are omitted.
The + layer 22 is formed as shown in FIG. Unlike FIG. 2, the point that it does not exist in the region 80 directly below the gate pad part in FIG. 3 exists only in the part in contact with each source electrode, and is connected by the annular part 24 in the outer peripheral part. The part facing the + layer 22 is convex. Then, in the periphery of the gate pad portion, the polycrystalline Si layer 5 in contact with the gate electrode 8 functions as a field plate, and the p base layer 2 and n −
The withstand voltage is maintained by expanding the depletion layer region under the reverse bias of the silicon substrate to below the field plate. To limit the volume of the depletion layer, the polycrystal Si layer is provided with a cut portion 51, which is connected to each gate polycrystal Si layer in a portion of the silicon substrate where there is no gate pad portion and surrounds the substrate outer periphery. Is made almost the same width as. The separated polycrystalline Si layer 52 is used as a channel stopper. Since there is no PN junction immediately below the gate pad portion, no avalanche current is generated, and since it does not operate as a diode at the time of reverse recovery, the avalanche withstand capability and reverse recovery withstand capability can be increased.
本発明によれば、ベース層を縦横の行列状に配置され
た多角形の複数領域とし、複数領域からなるベース層の
外周側に第二導電形の環状領域が配置されているので、
環状領域により外周での電界集中が生じにくくなり、か
つ内側全体の複数領域が行列状であるので、内側の全て
の複数領域に均等に電界集中点を分散することによっ
て、アバランシェ耐量と内蔵ダイオードの逆回復耐量が
高められる。そして、ゲートパッド部の直下に半導体基
板との間にPN接合を形成する層を設けず、他の基板の周
縁部と同様にベース層のチャネル形成領域上に設けられ
るゲート層のフィールドプレート効果により、ベース層
と基板との間のPN接合による空乏層を広げて耐圧を保持
する。そのゲート層にゲートパッド部の電極を接触させ
る。このようにゲートパッド部直下にPN接合を設けない
で不活性領域とすることにより、アバランシェ増倍電流
も逆回復電流もほとんど零となり、電流集中を大幅に低
減する結果、アバランシェ耐量，逆回復耐量の向上した
MOS型半導体装置が得られる。According to the present invention, the base layer is a plurality of polygonal regions arranged in a matrix in the vertical and horizontal directions, and since the second conductivity type annular region is arranged on the outer peripheral side of the base layer composed of the plurality of regions,
Since the electric field concentration on the outer periphery is less likely to occur due to the annular region and the plural regions on the entire inner side are arranged in a matrix, the avalanche withstand capability and the built-in diode Reverse recovery tolerance is increased. A layer for forming a PN junction with the semiconductor substrate is not provided immediately below the gate pad portion, and the field plate effect of the gate layer provided on the channel formation region of the base layer is used as in the peripheral portion of the other substrate. , The depletion layer formed by the PN junction between the base layer and the substrate is expanded to maintain the breakdown voltage. The electrode of the gate pad portion is brought into contact with the gate layer. By making the inactive region without providing the PN junction directly under the gate pad, the avalanche multiplication current and the reverse recovery current become almost zero, and the current concentration is greatly reduced. Improved
A MOS type semiconductor device can be obtained.
第１図は本発明の一実施例の電力用MOSFETをゲートパッ
ド部付近で切断して示した斜視図、第２図は従来の電力
用MOSFETの同様の斜視図、第３図は第１図の実施例のp+
層の分布を示す平面図である。 1:n-シリコン基板、2:ベース層、21:p層22:p+層、3:ソ
ース層、4:ゲート酸化膜、5:多結晶Si層、6:PSG層、7:
ソース電極、8:ゲート電極。FIG. 1 is a perspective view showing a power MOSFET according to an embodiment of the present invention cut in the vicinity of a gate pad portion, FIG. 2 is a similar perspective view of a conventional power MOSFET, and FIG. Example p +
It is a top view showing distribution of layers. 1: n - silicon substrate, 2: base layer, 21: p layer, 22: p + layer, 3: source layer, 4: gate oxide film, 5: polycrystalline Si layer, 6: PSG layer, 7:
Source electrode, 8: gate electrode.
Claims (2)
第二導電形の島状のベース層の表面層にさらに第一導電
形の環状のソース層を設け、該ソース層と半導体基板表
面に露出している第一導電形領域との間のベース層部分
をチャネル領域としてその上に絶縁膜を介してゲートが
設けられるものにおいて、前記ベース層は縦横の行列状
に配置された多角形の複数領域であり、該複数領域から
なるベース層の外周側に第二導電形の環状領域が配置さ
れ、該第二導電形の環状領域は、内周側で前記複数領域
と対峙する部分に凸部が設けられていることを特徴とす
るMOS型半導体装置。1. A first-conductivity-type annular source layer is further provided on a surface layer of a second-conductivity-type island-shaped base layer provided on a surface layer in a first-conductivity-type substrate. In a device in which a base layer portion between the first conductivity type region exposed on the surface of a semiconductor substrate is used as a channel region and a gate is provided thereover via an insulating film, the base layers are arranged in a matrix in vertical and horizontal directions. A plurality of polygonal regions, a second conductivity type annular region is arranged on the outer peripheral side of a base layer composed of the plurality of regions, and the second conductivity type annular region faces the plurality of regions on the inner peripheral side. A MOS type semiconductor device characterized in that a convex portion is provided at a portion to be formed.
第二導電形の島状のベース層の表面層にさらに第一導電
形の環状のソース層を設け、該ソース層と半導体基板表
面に露出している第一導電形領域との間のベース層部分
をチャネル領域としてその上に絶縁膜を介してゲートが
設けられるものにおいて、前記ベース層は縦横の行列状
に配置された多角形の複数領域であり、該複数領域から
なるベース層の外周側に第二導電形の環状領域が配置さ
れ、前記ゲートは前記第二導電形の複数領域を取り囲む
ように格子状に形成されており、かつ該ゲートが同一半
導体基板の前記第二導電形の環状領域より外側の外周上
の一部に設けられるゲートパッド部下まで延在して、該
ゲートパッド部と絶縁層を介して重ねられており、そし
てゲートパッド部とゲートとの一部が接触して電気的に
連結されており、さらにゲートパッド部直下のゲートに
空乏層容積制限のための切断部を設け、少なくとも該切
断部下の半導体基板の表面領域は第一導電形の不活性領
域とすることを特徴とするMOS型半導体装置。2. An annular source layer of the first conductivity type is further provided on a surface layer of an island-shaped base layer of the second conductivity type provided on the surface layer of the substrate of the first conductivity type. In a device in which a base layer portion between the first conductivity type region exposed on the surface of a semiconductor substrate is used as a channel region and a gate is provided thereover via an insulating film, the base layers are arranged in a matrix in vertical and horizontal directions. A plurality of polygonal regions, an annular region of the second conductivity type is disposed on the outer peripheral side of a base layer composed of the plurality of regions, and the gate is formed in a lattice shape so as to surround the plurality of regions of the second conductivity type. And the gate extends below the gate pad portion provided on a portion of the outer periphery of the second conductivity type annular region of the same semiconductor substrate, and through the gate pad portion and an insulating layer. Overlaid, and gate pad section A part of the gate is in contact with and electrically connected to the gate, and a cut portion for limiting the volume of the depletion layer is provided in the gate immediately below the gate pad portion. A MOS-type semiconductor device having an inactive region of a conductive type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63121104A JPH0828503B2 (en) | 1988-05-18 | 1988-05-18 | MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63121104A JPH0828503B2 (en) | 1988-05-18 | 1988-05-18 | MOS semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01290265A JPH01290265A (en) | 1989-11-22 |
| JPH0828503B2 true JPH0828503B2 (en) | 1996-03-21 |
Family
ID=14802980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63121104A Expired - Lifetime JPH0828503B2 (en) | 1988-05-18 | 1988-05-18 | MOS semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828503B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0438065U (en) * | 1990-07-27 | 1992-03-31 | ||
| TWI236134B (en) * | 2001-04-04 | 2005-07-11 | Mitsubishi Electric Corp | Semiconductor device |
| JP6067957B2 (en) * | 2011-02-15 | 2017-01-25 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS545674A (en) * | 1977-06-15 | 1979-01-17 | Sony Corp | Semiconductor device |
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
| JPS58100460A (en) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | Vertical type metal oxide semiconductor device |
| JPS59195840U (en) * | 1983-06-13 | 1984-12-26 | 日産自動車株式会社 | load drive circuit |
| JPS618486A (en) * | 1984-06-21 | 1986-01-16 | Shuichi Kitamura | Pump |
| JPS6184865A (en) * | 1984-10-02 | 1986-04-30 | Nec Corp | Semiconductor device |
| JPS62224074A (en) * | 1986-03-26 | 1987-10-02 | Hitachi Ltd | Insulated-gate semiconductor device |
-
1988
- 1988-05-18 JP JP63121104A patent/JPH0828503B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01290265A (en) | 1989-11-22 |
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