JPH0828389B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0828389B2 JPH0828389B2 JP2319647A JP31964790A JPH0828389B2 JP H0828389 B2 JPH0828389 B2 JP H0828389B2 JP 2319647 A JP2319647 A JP 2319647A JP 31964790 A JP31964790 A JP 31964790A JP H0828389 B2 JPH0828389 B2 JP H0828389B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- aluminum
- bonding pad
- stabilizing film
- surface stabilizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置特にボンディングパッドに関する
ものである。The present invention relates to a semiconductor device, and more particularly to a bonding pad.
第２図は従来のボンディングパッドの形成フローを示
す工程断面図であり、図に於いて、（１）はレジスト、
（２）はボンディングパッドとなるアルミ、（３）はア
ルミと下地部を絶縁する層間絶縁膜、（６）は表面安定
化膜、（７）はボンディングワイヤである。FIG. 2 is a process cross-sectional view showing the flow of forming a conventional bonding pad, in which (1) is a resist,
(2) is aluminum that serves as a bonding pad, (3) is an interlayer insulating film that insulates the aluminum from the underlying portion, (6) is a surface stabilizing film, and (7) is a bonding wire.
次にボンディングパッド形成フローについて説明す
る。Next, a bonding pad forming flow will be described.
半導体基板表面に絶縁膜（３）を介しアルミ（２）を
形成し、ボンディングパッドを形成するために、レジス
ト（１）を塗布し、パターニングを行なう。（第２図
（ａ））。Aluminum (2) is formed on the surface of the semiconductor substrate through an insulating film (3), and a resist (1) is applied and patterned to form a bonding pad. (FIG. 2 (a)).
次にアルミ（２）をエッチングしレジストを除去する
（第２図（ｂ））。Next, the aluminum (2) is etched to remove the resist (FIG. 2 (b)).
表面安定化膜（６）を形成し、ボンディングパッドを
開孔するためにレジストを塗布し、パターニングを行な
う（第２図（ｃ））。A surface stabilizing film (6) is formed, a resist is applied to open a bonding pad, and patterning is performed (FIG. 2 (c)).
表面安定化膜をエッチングしてレジストを除去し、ボ
ンディングパッドが形成される。（第２図（ｄ））。The surface stabilizing film is etched to remove the resist, and a bonding pad is formed. (FIG. 2 (d)).
以上の様に構成されたボンディングパッドにボンディ
ングを行う場合、ボンディングワイヤの先端部が、ボン
ディングパッド開孔部の表面安定化膜の側壁に衝撃を与
え、クラックを生じせしめ、又、開孔部とボンディング
ワイヤ先端部との間に隙間が（第２図（ｅ））できるの
で、ワイヤを伝って水分がパッド開孔部に進入し、アル
ミ表面を腐食させるなどの問題点があった。また、これ
らを防ぐ為パッド開孔部を側ぐように、ボンディングを
行うとボンディング強度を強くせしめなければならず、
表面安定化膜にクラックを生じさせるなど信頼性に影響
を与えるなどの問題点があった。（第２図（ｆ）） 本発明は、上記のような問題点を解消するためになさ
れたもので、ボンディング構造をボンディングパッドの
高さをボンディング開孔部の表面安定化膜の高さとほぼ
同じにして、信頼性の向上を期待できる半導体装置を得
ることを目的とする。When performing bonding on the bonding pad configured as described above, the tip of the bonding wire gives a shock to the side wall of the surface stabilizing film of the bonding pad opening, causing a crack, and Since there is a gap between the tip of the bonding wire (FIG. 2 (e)), there is a problem that moisture penetrates into the pad opening through the wire and corrodes the aluminum surface. Also, in order to prevent these, when bonding is performed so that the pad opening part is located on the side, the bonding strength must be increased,
There is a problem that the surface stabilizing film is cracked and the reliability is affected. (FIG. 2 (f)) The present invention has been made to solve the above-mentioned problems, and the bonding structure has a height of the bonding pad substantially equal to the height of the surface stabilizing film of the bonding opening. In the same manner, it is an object to obtain a semiconductor device which can be expected to improve reliability.
本発明に於ける半導体装置はボンディングパッド下部
に凸部を設け、パッド表面の高さと、パッド開孔部の表
面安定化膜の高さをほぼ同一にしたものである。In the semiconductor device according to the present invention, a convex portion is provided below the bonding pad, and the height of the pad surface and the height of the surface stabilizing film at the pad opening portion are substantially the same.
本発明における半導体装置は、ボンディングパッド表
面の高さがパッド開孔部の表面安定化膜の高さとほぼ同
一なので、ボンディング時にボンディング強度を弱くす
ることができ、開孔部を塞ぐようにボンディングするの
で、表面安定化膜にクラックを生じさせず、且つワイヤ
を伝う水分などの進入を防ぐことができる。In the semiconductor device according to the present invention, since the height of the bonding pad surface is almost the same as the height of the surface stabilizing film of the pad opening portion, the bonding strength can be weakened at the time of bonding, and bonding is performed so as to close the opening portion. Therefore, it is possible to prevent cracks from being generated in the surface stabilizing film, and to prevent the penetration of moisture or the like that propagates through the wire.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は、この実施例のボンディングパッドの形成フ
ローを示す図で、（１）はレジスト、（２）は第１アル
ミ、（３）は第１アルミと下地を絶縁するための絶縁
膜、（４）は第１アルミと第２アルミを絶縁するための
絶縁膜、（５）は第２アルミ、（６）は表面安定化膜で
ある。FIG. 1 is a diagram showing a flow of forming a bonding pad of this embodiment. (1) is a resist, (2) is a first aluminum, (3) is an insulating film for insulating the first aluminum from the base, (4) is an insulating film for insulating the first aluminum and the second aluminum, (5) is the second aluminum, and (6) is a surface stabilizing film.
次にボンディングパッドの形成フローについて説明す
る。半導体基板表面に絶縁膜（３）を介し第１アルミ
（２）を形成する凸部を形成するためのパターニングを
行なう（第１図（ａ））。Next, a flow of forming the bonding pad will be described. Patterning is performed on the surface of the semiconductor substrate through the insulating film (3) so as to form a convex portion for forming the first aluminum (2) (FIG. 1 (a)).
アルミエッチングを行ないレジストを除去する（第１
図（ｂ））。Aluminum etching is performed to remove the resist (first
Figure (b).
上層アルミとの絶縁膜（４）を形成する（第１図
（ｃ））。An insulating film (4) with the upper aluminum layer is formed (FIG. 1 (c)).
第２アルミ（５）を形成し、ボンディングパッドを形
成するためにパターニングを行なう（第１図（ｄ））。
アルミエッチングを行ない、レジスト除去を行なう（第
１図（ｅ））。A second aluminum layer (5) is formed and patterned to form bonding pads (FIG. 1 (d)).
Aluminum etching is performed to remove the resist (FIG. 1 (e)).
表面安定化膜を形成しボンディングパッド部の開孔を
行なうが、この時、段差下側に安定膜をのこすようにパ
ターニングを行なう（第１図（ｆ））。A surface stabilizing film is formed and a hole is formed in the bonding pad portion. At this time, patterning is performed so as to extend the stabilizing film below the step (FIG. 1 (f)).
表面安定化膜のエッチングを行ないレジストを除去す
る。これでボンディングパッドの高さが表面安定化膜の
高さと同様のものが得られる。このようなボンディング
パッドでボンディングを行なう時、第１図（ｈ）ように
ボンディングワイヤと開孔部の表面安定化膜との余裕が
全くなくても表面安定化膜にクラックを生じさせない。
ボンディングは開孔部及び表面安定化膜を塞ぐように行
なう。The surface stabilizing film is etched to remove the resist. As a result, the height of the bonding pad is the same as that of the surface stabilizing film. When bonding is performed with such a bonding pad, cracks do not occur in the surface stabilizing film even if there is no margin between the bonding wire and the surface stabilizing film in the opening as shown in FIG. 1 (h).
Bonding is performed so as to close the opening and the surface stabilizing film.
なお、上記実施例は、第１アルミと第２アルミでの例
を示したが、多層アルミの場合も、下層アルミで凸部を
構成すれば同様の効果が得られ、１層アルミの場合は下
層のポリシリコンや、分離用酸化膜で凸部を構成するこ
とにより同様の効果が得られる。In the above-mentioned embodiment, the example of the first aluminum and the second aluminum is shown, but also in the case of multilayer aluminum, the same effect can be obtained by forming the convex portion with the lower layer aluminum, and in the case of single layer aluminum The same effect can be obtained by forming the convex portion by the lower layer polysilicon or the oxide film for isolation.
以上のようにこの発明によればボンディングパッド下
に凸部を形成し、ボンディングパッドの高さが表面安定
化膜の高さとほぼ同様になるように構成したので、ボン
ディングを行なったとき、ボンディングの先端とボンデ
ィングパッドの開孔部の表面安定化膜との余裕がなくて
も表面安定化膜にクラックを生じさせないのでパッドを
小さくできる効果がある。As described above, according to the present invention, the convex portion is formed under the bonding pad, and the height of the bonding pad is substantially the same as the height of the surface stabilizing film. Even if there is no margin between the tip and the surface stabilizing film in the opening portion of the bonding pad, the surface stabilizing film is not cracked, so that the pad can be made smaller.
第１図（ａ）〜（ｈ）は本発明の一実施例を示すボンデ
ィングパッド形成フローの工程断面図、第２図（ａ）〜
（ｆ）は従来のボンディングパッド形成フローの工程断
面図である。 図において、（１）はレジスト、（２）は第１アルミ、
（３）は層間絶縁膜、（４）は1AL−2AL間層間絶縁膜、
（５）は第２アルミ、（６）は表面安定化膜、（７）は
ボンディングワイヤである。 なお、図中、同一符号は同一、又は相当部分を示す。1 (a) to 1 (h) are process sectional views of a bonding pad forming flow showing one embodiment of the present invention, and FIGS.
(F) is a process sectional view of a conventional bonding pad forming flow. In the figure, (1) is the resist, (2) is the first aluminum,
(3) is the interlayer insulating film, (4) is the 1AL-2AL interlayer insulating film,
(5) is the second aluminum, (6) is the surface stabilizing film, and (7) is the bonding wire. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ッドを覆う表面安定化膜に開孔部を形成し、この開孔部
を介しボンディングワイヤが接続された半導体装置に於
いて、ボンディングパッド下層部に凸部を形成し、ボン
ディングパッド部と前記パッド開孔部及びそれらを覆う
表面安定化膜が半導体基板より同一の段差を有し、ボン
ディングワイヤによりそれらが全て塞がれていることを
特徴とする半導体装置。1. A semiconductor device in which a hole is formed in a surface stabilizing film covering a bonding pad provided on a surface of a semiconductor substrate, and a bonding wire is connected through the hole, and a bonding pad lower layer portion is provided. A convex portion is formed on the bonding pad portion, the pad opening portion and the surface stabilizing film covering them have the same level difference from the semiconductor substrate, and all of them are closed by a bonding wire. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319647A JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319647A JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04188739A JPH04188739A (en) | 1992-07-07 |
| JPH0828389B2 true JPH0828389B2 (en) | 1996-03-21 |
Family
ID=18112635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2319647A Expired - Fee Related JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828389B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517921A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4655137B2 (en) * | 2008-10-30 | 2011-03-23 | ソニー株式会社 | Semiconductor device |
-
1990
- 1990-11-21 JP JP2319647A patent/JPH0828389B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517921A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Bonded substrate and forming method thereof, and three-dimensional package structure and forming method thereof |
| CN104517921B (en) * | 2013-09-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | It is bonded substrate and forming method thereof, three-dimension packaging structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04188739A (en) | 1992-07-07 |
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