JPH04188739A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04188739A JPH04188739A JP2319647A JP31964790A JPH04188739A JP H04188739 A JPH04188739 A JP H04188739A JP 2319647 A JP2319647 A JP 2319647A JP 31964790 A JP31964790 A JP 31964790A JP H04188739 A JPH04188739 A JP H04188739A
- Authority
- JP
- Japan
- Prior art keywords
- stabilizing film
- aluminum
- bonding
- surface stabilizing
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052782 aluminium Inorganic materials 0.000 abstract description 26
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置特にボンディングパッドに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bonding pad.
第２図は従来のボンディングパッドの形成フローを示す
工程断面図であり、図に於いて、（１）はレジスト、（
２）はボンディングパッドとなるアルミ、（３）はアル
ミと下地部を絶縁する層間絶縁膜、（６）は表面安定化
膜、（７）はボンディングワイヤである。FIG. 2 is a process sectional view showing the conventional bonding pad formation flow. In the figure, (1) is a resist, (1) is a resist, (
2) is aluminum serving as a bonding pad, (3) is an interlayer insulating film that insulates the aluminum and the underlying portion, (6) is a surface stabilizing film, and (7) is a bonding wire.
次にボンディングパッド形成フローについて説明する。Next, a bonding pad formation flow will be explained.
半導体基板表面に絶縁膜（３）を介しアルミ（２）を形
成し、ボンティングバットを形成するために、レジスト
（１）を塗布し、パターニングを行なう。（第２図（ａ
））。Aluminum (2) is formed on the surface of the semiconductor substrate via an insulating film (3), and in order to form a bonding butt, a resist (1) is applied and patterned. (Figure 2 (a)
)).
次にアルミ（２）をエツチングしレジストを除去する（
第２図（ｂ））。Next, the aluminum (2) is etched and the resist is removed (
Figure 2(b)).
表面安定化膜（６）を形成し、ホンディングパッドを開
孔するためにレジストを塗布し、バターニングを行なう
（第２図（Ｃ））。A surface stabilizing film (6) is formed, a resist is applied to form a hole for a bonding pad, and patterning is performed (FIG. 2(C)).
表面安定化膜をエツチングしてレジストを除去し、ホン
ディングパッドが形成される。（第２図（ｄ））。The surface stabilizing film is etched and the resist is removed to form a bonding pad. (Figure 2(d)).
以上の様に構成されたボンディングパッドにポンデイン
クを行う場合、ボンディングワイヤの先端部が、ボンデ
ィングパッド開孔部の表面安定化膜の側壁に衝撃を与え
、クラックを生じせしめ、又、開孔部とボンディングワ
イヤ先端部との間に隙間が（第２図（ｅ））できるので
、ワイヤを伝って水分がバッド開孔部に進入し、アルミ
表面を腐食させるなどの問題点があった。また、これら
を防ぐ為バッド開孔部を塞ぐように、ボンディングを行
うとボンディング強度を強くせしめなければならず、表
面安定化膜にクラックを生じさせるなど信頼性に影響を
与えるなどの問題点があった。（第２図（ｆ））
本発明は、上記のような問題点を解消するためになされ
たもので、ボンディング構造をボンディングパッドの高
さをボンディング開孔部の表面安定化膜の高さとほぼ同
じにして、信頼性の向上を期待できる半導体装置を得る
ことを目的とする。When inking a bonding pad configured as described above, the tip of the bonding wire impacts the side wall of the surface stabilizing film in the bonding pad opening, causing cracks, and Since a gap is formed between the bonding wire and the tip of the bonding wire (FIG. 2(e)), there is a problem in that moisture flows along the wire and enters the pad opening, corroding the aluminum surface. In addition, if bonding is performed to close the openings of the pads in order to prevent these problems, the bonding strength must be increased, which causes problems such as cracks in the surface stabilizing film, which affects reliability. there were. (Fig. 2(f)) The present invention was made to solve the above-mentioned problems, and the bonding structure is such that the height of the bonding pad is approximately equal to the height of the surface stabilizing film of the bonding opening. It is an object of the present invention to obtain a semiconductor device which can also be expected to have improved reliability.
本発明に於ける半導体装置はボンディングパッド下部に
凸部を設け、バット表面の高さと、バット開孔部の表面
安定化膜の高さをほぼ同一にしたものである。In the semiconductor device of the present invention, a convex portion is provided below the bonding pad, and the height of the butt surface and the height of the surface stabilizing film in the butt opening are made almost the same.
（作用）
本発明における半導体装置は、ボンディングパッド表面
の高さがバット開孔部の表面安定化膜の高さとほぼ同一
なので、ホンディング時にボンディング強度を弱くする
ことができ、開孔部を塞ぐようにボンディングするので
、表面安定化膜にクラックを生じさせず、且つワイヤを
伝う水分などの進入を防ぐことができる。(Function) In the semiconductor device of the present invention, since the height of the surface of the bonding pad is almost the same as the height of the surface stabilizing film of the butt opening, the bonding strength can be weakened during bonding, and the opening can be blocked. Since the wires are bonded in this manner, cracks do not occur in the surface stabilizing film, and moisture and the like can be prevented from penetrating through the wire.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は、この実施例のボンディングパッドの形成フロ
ーを示す図で、（１）はレジスト、（２）は第１アルミ
、（３）は第１アルミと下地を絶縁するための絶縁膜、
（４）は第１アルミと第２アルミを絶縁するための絶縁
膜、（５）は第２アルミ、（６）は表面安定化膜である
。FIG. 1 is a diagram showing the formation flow of the bonding pad in this example, in which (1) is the resist, (2) is the first aluminum, (3) is the insulating film for insulating the first aluminum and the base,
(4) is an insulating film for insulating the first aluminum and second aluminum, (5) is the second aluminum, and (6) is a surface stabilizing film.
次にボンディングパッドの形成フローについて説明する
。半導体基板表面に絶縁膜（３）を介し第１アルミ（２
）を形成する凸部を形成するためバターニングを行なう
（第１図（ａ））。Next, a flow of forming a bonding pad will be explained. First aluminum (2) is applied to the surface of the semiconductor substrate via an insulating film (3).
), patterning is performed to form the convex portions (FIG. 1(a)).
アルミエツチングを行ないレジストを除去する（第１図
（ｂ））。The resist is removed by aluminum etching (FIG. 1(b)).
上層アルミとの絶縁膜（４）を形成する（第１図（Ｃ）
）。Form an insulating film (4) with the upper layer aluminum (Fig. 1 (C)
).
第２アルミ（５）を形成し、ボンディングパッドを形成
するためにパターニングを行なう（第１図（ｄ））。ア
ルミエツチングを行ない、レジスト除去を行なう（第１
図（ｅ））。A second aluminum (5) is formed and patterned to form bonding pads (FIG. 1(d)). Perform aluminum etching and remove resist (first step)
Figure (e)).
表面安定化膜を形成しボンディングパッド部の開孔を行
なうか、この時、段差下側に安定膜をのこすようにバタ
ーニングを行なう（第１図（ｆ））。Either a surface stabilizing film is formed and a hole is formed at the bonding pad portion, or at this time, buttering is performed so as to leave the stabilizing film on the underside of the step (FIG. 1(f)).
表面安定化膜のエツチングを行ないレジストを除去する
。これでボンデインクパッドの高さが表面安定化膜の高
さと同様のものが得られる。このようなボンディングバ
ットでボンティングを行なう時、第１図（ｈ）ようにボ
ンディングワイヤと開孔部の表面安定化膜との余裕か全
くなくても表面安定化膜にクラックを生じさせない。ボ
ンディングは開孔部及び表面安定化膜を塞ぐように行な
う。The surface stabilizing film is etched and the resist is removed. This allows the height of the bonde ink pad to be similar to the height of the surface stabilizing film. When bonding is performed using such a bonding bat, cracks do not occur in the surface stabilizing film even if there is no clearance between the bonding wire and the surface stabilizing film at the opening as shown in FIG. 1(h). Bonding is performed so as to close the openings and the surface stabilizing film.
なお、上記実施例は、第１アルミと第２アルミての例を
示したが、多層アルミの場合も、下層アルミで凸部を構
成すれば同様の効果が得られ、１層アルミの場合は下層
のポリシリコンや、分離用酸化膜で凸部を構成すること
により同様の効果が得られる。In addition, although the above example shows an example of the first aluminum and the second aluminum, the same effect can be obtained even in the case of multi-layer aluminum by forming the convex part with the lower layer aluminum, and in the case of single-layer aluminum, the same effect can be obtained. A similar effect can be obtained by forming the convex portion with the underlying polysilicon layer or the isolation oxide film.
以上のようにこの発明によればボンディングパッド下に
凸部を形成し、ボンディングパッドの高さが表面安定化
膜の高さとほぼ同様になるように構成したので、ボンデ
ィングを行なったとき、ボンディングの先端とボンディ
ングパッドの開孔部の表面安定化膜との余裕がなくても
表面安定化膜にクランクを生じさせないのでバットを小
さくできる効果がある。As described above, according to the present invention, a convex portion is formed under the bonding pad, and the height of the bonding pad is approximately the same as the height of the surface stabilizing film. Even if there is not enough space between the tip and the surface stabilizing film in the opening of the bonding pad, the surface stabilizing film does not crank, so the butt can be made smaller.
第１図（ａ）〜（ｈ）は本発明の一実施例を示すボンデ
ィングパッド形成フローの工程断面図、第２図（ａ）〜
（ｆ）は従来のポンティングパット形成フローの工程断
面図である。
図において、（１〉はレジスト、（２）は第１アルミ、
（３）は層間絶縁膜、（４）はＩＡＬ−２ＡＬ間層間絶
縁膜、（５）は第２アルミ、（６）は表面安定化膜、（
７）はホンディングワイヤである。
なお、図中、同一符号は同一、又は相当部分を示す。FIGS. 1(a) to (h) are process cross-sectional views of a bonding pad formation flow showing an embodiment of the present invention, and FIGS. 2(a) to 2(h) are
(f) is a process sectional view of a conventional ponting pad formation flow. In the figure, (1> is resist, (2) is first aluminum,
(3) is an interlayer insulating film, (4) is an IAL-2AL interlayer insulating film, (5) is a second aluminum, (6) is a surface stabilizing film, (
7) is a honding wire. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
表面安定化膜に開孔部を形成し、この開孔部を介しボン
ディングワイヤが接続された半導体装置に於いて、ボン
ディングパッド下層部に凸部を形成し、ボンディングパ
ッド部と前記パッド開孔部及びそれらを覆う表面安定化
膜が半導体基板より同一の段差を有し、ボンディングワ
イヤによりそれらが全て塞がれていることを特徴とする
半導体装置。An opening is formed in a surface stabilizing film that covers a bonding pad provided on the surface of a semiconductor substrate, and in a semiconductor device in which a bonding wire is connected through this opening, a protrusion is formed in the lower layer of the bonding pad. A semiconductor device characterized in that the bonding pad portion, the pad opening portion, and the surface stabilizing film covering them have the same level difference from the semiconductor substrate, and all of them are covered by the bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319647A JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319647A JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04188739A true JPH04188739A (en) | 1992-07-07 |
| JPH0828389B2 JPH0828389B2 (en) | 1996-03-21 |
Family
ID=18112635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2319647A Expired - Fee Related JPH0828389B2 (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828389B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109137A (en) * | 2008-10-30 | 2010-05-13 | Sony Corp | Semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517921B (en) * | 2013-09-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | It is bonded substrate and forming method thereof, three-dimension packaging structure and forming method thereof |
-
1990
- 1990-11-21 JP JP2319647A patent/JPH0828389B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109137A (en) * | 2008-10-30 | 2010-05-13 | Sony Corp | Semiconductor device |
| JP4655137B2 (en) * | 2008-10-30 | 2011-03-23 | ソニー株式会社 | Semiconductor device |
| US8456014B2 (en) | 2008-10-30 | 2013-06-04 | Sony Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0828389B2 (en) | 1996-03-21 |
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