JPS63208225A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63208225A JPS63208225A JP62041878A JP4187887A JPS63208225A JP S63208225 A JPS63208225 A JP S63208225A JP 62041878 A JP62041878 A JP 62041878A JP 4187887 A JP4187887 A JP 4187887A JP S63208225 A JPS63208225 A JP S63208225A
- Authority
- JP
- Japan
- Prior art keywords
- pad electrode
- aluminum pad
- film
- aluminum
- alumina
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 53
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 230000001681 protective effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000007772 electrode material Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 2
- 238000002161 passivation Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000007789 sealing Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 241001441724 Tetraodontidae Species 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にアルミ−パッド電極に
おけるスルー・ホール開口部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and more particularly to the structure of through-hole openings in aluminum pad electrodes.
従来、半導体装置のパッド電極にはアルミ材が多用され
、また、その保護膜にはシリコン酸化膜（Ｓｉｎｓ）、
リン硅酸ガラス（ＰＳＧ）等の酸化物系の無機膜か或い
はポリイミド系樹脂の有機膜が使用される。従って、ス
ルー・ホールの開口部はこれらの絶縁膜をアルミ・パッ
ド電極上で開孔することによって形成される。周知の通
り、パッド電極は半導体装置の外部取出電極であって半
導体基板の最上層に位置しているので水分の侵入を受は
易い。この場合、水分はスルー・ホール開口部から侵入
してパッド電極のアルミ材を腐食しコロージ嘗ンを発生
せしめるので信頼性が著しく阻害される。このように、
アルミ・パッド電極の信頼性は外部からの水分の侵入に
よって著しく低下せしめられるので保護膜面をシリコン
窒化膜の如き耐湿性膜質で再被覆することが通常行なわ
れている。Conventionally, aluminum material is often used for pad electrodes of semiconductor devices, and silicon oxide films (Sins), silicon oxide films (Sins), etc. are used as protective films.
An oxide-based inorganic film such as phosphosilicate glass (PSG) or an organic film made of polyimide-based resin is used. Therefore, the openings of the through holes are formed by opening these insulating films on the aluminum pad electrodes. As is well known, the pad electrode is an external electrode of the semiconductor device and is located on the top layer of the semiconductor substrate, so it is easily susceptible to moisture intrusion. In this case, moisture enters through the through-hole opening and corrodes the aluminum material of the pad electrode, causing collage, which significantly impairs reliability. in this way,
Since the reliability of aluminum pad electrodes is significantly reduced by the intrusion of moisture from the outside, it is common practice to recoat the protective film surface with a moisture-resistant film such as a silicon nitride film.
しかしながら、保護膜の表面にシリコン窒化膜（Ｓｉｓ
ＮＬ）を被覆して複合膜とした構造であってもスルーΦ
ホール開口部はこの複合膜の一部を開孔することによっ
て形成されるのでこの開口端面には必ず下層の絶縁膜が
露出される。しかもこの下層絶縁膜はアルミ・パッド電
極の縁端部を直接被覆しているので封止用樹脂膜を通し
てチップ表面に到達した水分はこの開口端面の露出した
絶縁膜から易々と内部に侵入して従来と同じようにアル
ミ・パッド電極を侵蝕するようになる。すなわち、従来
の如く保護膜の上表面のみに耐湿性をもたせただけでは
アルミ拳パッド電極におけるスルー・ホール開口部の耐
湿性は期待する程には向上せず信頼性も改善されない。However, a silicon nitride film (Sis) is formed on the surface of the protective film.
Even if the structure is a composite film coated with NL), the through Φ
Since the hole opening is formed by opening a part of this composite film, the underlying insulating film is always exposed at the end face of this opening. Moreover, since this lower layer insulating film directly covers the edge of the aluminum pad electrode, moisture that reaches the chip surface through the sealing resin film easily enters the inside through the exposed insulating film on the open end surface. As with the conventional method, the aluminum pad electrode will be eroded. That is, if only the upper surface of the protective film is made moisture resistant as in the past, the moisture resistance of the through-hole opening in the aluminum fist pad electrode will not be improved as much as expected, and the reliability will not be improved either.
本発明の目的は、上記の状況に鑑み、アルミ−パッド電
極の耐湿性を著しく向上せしめることのできる構造のス
ルー・ホール開口部を備えた半導体装置を提供すること
である。SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide a semiconductor device having a through-hole opening with a structure that can significantly improve the moisture resistance of an aluminum pad electrode.
本発明によれば、半導体装置は、半導体基板と、前記半
導体基板のフィールド絶縁膜上に形成されるアルミ・パ
ッド電極と、前記アルミ・パッド電極の縁端部を被覆す
る前記アルミ・パッド電極材のアルミナ変換膜と、前記
アルミナ変換膜上で縁端部を被覆して前記アルミ・パッ
ド電極のスルー・ホール開口部を形成する絶縁保護膜と
を含む。According to the present invention, a semiconductor device includes a semiconductor substrate, an aluminum pad electrode formed on a field insulating film of the semiconductor substrate, and the aluminum pad electrode material covering an edge of the aluminum pad electrode. an alumina conversion film; and an insulating protection film covering an edge on the alumina conversion film to form a through-hole opening for the aluminum pad electrode.
すなわち、本発明によれば、従来、下層絶縁膜が直接被
覆していたアルξ・パッド電極の縁端部には電極材のア
ルミナ変換膜が形成され下層絶縁膜はこのアルミナ変換
膜を介して間接的にアルミ・パッド電極の縁端部を被覆
しスルー・ホールの開口部を形成するよう設けられる。That is, according to the present invention, an alumina conversion film, which is an electrode material, is formed on the edge of the Alξ pad electrode, which was conventionally directly covered with a lower insulating film, and the lower insulating film is coated via this alumina conversion film. It is provided to indirectly cover the edge of the aluminum pad electrode and form the opening of the through hole.
このアルミナ変換膜はアルミ・パッド電極面を高周波に
よるスパッタ・エツチング等で清浄にした後温水または
酸素プラズマで選択酸化すれば容易に形成できるので製
造１糧を特に複雑化することはない。This alumina conversion film can be easily formed by cleaning the aluminum pad electrode surface by high-frequency sputtering, etching, etc., and then selectively oxidizing it with hot water or oxygen plasma, so that the manufacturing process is not particularly complicated.
このアルミナ変換膜はアルミ・パッド電極縁端部のバッ
ジページ璽ン効果を高めるよう作用する。This alumina conversion film acts to enhance the badge page seal effect at the edge of the aluminum pad electrode.
すなわち、封止用樹脂膜を通してチップ表面に到達した
水分が開口端面を伝わってパッド電極面に侵透するのを
阻止するので従来問題とされたアルミ・パッド電極のコ
ロージ胃ン発生事故は確実に防止され信頼性が著しく改
善される。以下図面を参照して本発明の詳細な説明する
。In other words, since moisture that has reached the chip surface through the sealing resin film is prevented from penetrating the pad electrode surface through the open end surface, the conventional problem of corrosion caused by aluminum pad electrodes is definitely avoided. prevention and reliability is significantly improved. The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示すアルミ・パッド電極部
の断面構造図である。本実施例によれば、本発明の半導
体装置は、半導体基板１と、その表面を被覆するフィー
ルド絶縁膜２と、アルミ・パッド電極３と、アルミ・パ
ッド電極３０緑端部に形成されたアルミナ変換膜４と、
このアルミナ変換膜４上で縁端部を被覆してアルミ・パ
ッド電極３のスルー・ホール開口部を形成するリン硅酸
ガラス（ＰＳＧ）などからなる絶縁保護膜５と、ボンデ
ィング・ワイヤ６と、封止用樹脂膜７とを含む。FIG. 1 is a cross-sectional structural diagram of an aluminum pad electrode section showing one embodiment of the present invention. According to this embodiment, the semiconductor device of the present invention includes a semiconductor substrate 1, a field insulating film 2 covering the surface thereof, an aluminum pad electrode 3, and an alumina film formed on the green end of the aluminum pad electrode 30. A conversion membrane 4,
An insulating protective film 5 made of phosphosilicate glass (PSG) or the like covers the edge of the alumina conversion film 4 to form a through-hole opening of the aluminum pad electrode 3, and a bonding wire 6. and a sealing resin film 7.
本実施例によれば、アルミ・パッド電極３の縁端部には
絶縁保護膜５の形成に先立ちアルミナ変換膜４が選択的
く形成される。この形成には公知の選択的アルミナ変換
手段を用い得るので製造上側等問題となることはなくボ
ンディング・ワイヤ６のボールが接着変形する領域だけ
を残しその他の領域がアルミ素地を露出しないように形
成することができる。すなわち、アルミナ変換膜４は第
１図が示すようにアルミ・パッド電極３の縁端部をその
側壁を含み且つボンディング領域のみを残す程度にまで
広範囲にわたシ形成される。従って、アルミ拳ハツト電
極３上に形成されるスルー・ホールの開口部は絶縁保護
膜５がアルミ素地を直接被覆する従来のものとは異なシ
このアルミナ変換膜４を介し間接的に被覆する構造のも
のとなる。According to this embodiment, the alumina conversion film 4 is selectively formed on the edge of the aluminum pad electrode 3 prior to the formation of the insulating protective film 5. Since a known selective alumina conversion means can be used for this formation, there will be no manufacturing problems, and only the area where the ball of the bonding wire 6 is bonded and deformed is formed so that the aluminum substrate is not exposed in other areas. can do. That is, as shown in FIG. 1, the alumina conversion film 4 is formed over a wide range of areas including the sidewalls of the aluminum pad electrode 3 and leaving only the bonding area. Therefore, the opening of the through hole formed on the aluminum fist electrode 3 has a structure in which the insulating protective film 5 covers the aluminum substrate indirectly through the alumina conversion film 4, which is different from the conventional structure in which the aluminum substrate is directly covered. Becomes the property of
この際、アルミナ変換膜４はアルミ・パッド電極３の被
覆面に対しバッジベージ曹ン膜として働き封止用樹脂膜
７に生じたクラックまたはビン・ホールを通して侵入す
る水分がアルミ・パッド電極３内に侵透してコロージ璽
ン化するのをきわめて有効に阻止することができる。す
なわち、アルミ・パッド電極３におけるスルー・ホール
開口部の耐湿性を著しく向上せしめ半導体装置の信頼性
を大きく高めることができる。At this time, the alumina conversion film 4 acts as a badge-base carbon film on the covered surface of the aluminum pad electrode 3, and moisture that enters through cracks or holes formed in the sealing resin film 7 is absorbed into the aluminum pad electrode 3. Penetration and formation of collage can be very effectively prevented. That is, the moisture resistance of the through-hole opening in the aluminum pad electrode 3 can be significantly improved, and the reliability of the semiconductor device can be greatly improved.
第２図（ａ）〜（ｄ）は本発明半導体装置の一つの製造
工程図で第１図の実施例に対応するものである。FIGS. 2(a) to 2(d) are one of the manufacturing process diagrams of the semiconductor device of the present invention, and correspond to the embodiment shown in FIG. 1.
この製造工程によれば、半導体基板１のフィールド絶縁
膜２上にはアルミ・パッド電極３がまずパターニング形
成され、このアルミ・パッド電極３上にはレジストの残
しパターン８が形成すべきスルｍ−ホール開口部の径よ
シ若干小さめに被着される。〔第２図（ａ）参照〕。つ
いでアルミ−パッド電極３の露出面は高周波によるスパ
ッタ・エツチング等で清浄化され温水浸漬または酸素プ
ラズマ等の処理を受けてアルミナ変換膜４に変質される
。According to this manufacturing process, an aluminum pad electrode 3 is first patterned on a field insulating film 2 of a semiconductor substrate 1, and a resist pattern 8 is to be formed on this aluminum pad electrode 3. The diameter of the hole opening is slightly smaller than the diameter of the hole. [See Figure 2(a)]. The exposed surface of the aluminum pad electrode 3 is then cleaned by high frequency sputtering, etching, etc., and transformed into an alumina conversion film 4 by immersion in hot water or treatment with oxygen plasma.
〔第２図（ｂ）参照〕。ここでレジストの残しパターン
８は除去されついで絶縁保護膜５が全面に被覆された後
スルー・ホール開口部形成のためのレジスト膜９が改め
て被着される。〔第２図（ｃ）参照〕。[See Figure 2(b)]. Here, the remaining resist pattern 8 is removed, and after the entire surface is covered with the insulating protective film 5, a resist film 9 for forming through-hole openings is deposited again. [See Figure 2(c)].
その後公知の写真蝕刻技術を用い絶縁保護膜５を開孔す
ればワイヤ・ボンディングすべき領域のみにアルミ素地
を残し且つ縁端部のアルミナ変換膜４上に絶縁保護膜５
を設けたスルー・ホール開口部１０が第２図（ｄ）の如
く形成される。従りて、算出するアルミ素地にボンディ
ング・ワイヤ６をボンディングし更に封止用樹脂膜７で
封入すれば第１図の実施例構造を得ることができる。Thereafter, holes are formed in the insulating protective film 5 using a known photolithography technique, leaving the aluminum base only in the area where wire bonding is to be performed, and leaving the insulating protective film 5 on the alumina conversion film 4 at the edge.
A through-hole opening 10 having a diameter is formed as shown in FIG. 2(d). Therefore, by bonding the bonding wire 6 to the calculated aluminum base material and further encapsulating it with a sealing resin film 7, the structure of the embodiment shown in FIG. 1 can be obtained.
以上詳細に説明したように、本発明によれば、アルミ・
パッド電極のスルー・ホール開口部は下層絶縁保護膜が
アルミナ変換膜を介してパッド電極の縁端部を被覆する
構造とされているので、封止用樹脂膜を通して侵入する
水分のパッド電極面への侵入径路を完全に遮断し得る。As explained in detail above, according to the present invention, aluminum
The through-hole opening of the pad electrode has a structure in which the lower insulating protective film covers the edge of the pad electrode via the alumina conversion film, so moisture that enters through the sealing resin film will not reach the pad electrode surface. can completely block the entry route.
従って、従来の如きアルミ・パッド電極のコロージ冒ン
化が防止されるので信頼性高き半導体装置を得ることが
できる。Therefore, since the conventional aluminum pad electrode is prevented from being damaged by collage, a highly reliable semiconductor device can be obtained.
第１図は本発明の一実施例を示すアルミ・パッド電極部
の断面構造図、第２図（ａ）〜（ｄ）は本発明半導体装
置の一つの製造工程図である。
１・・・・・・半導体基板、２・・・・・・フィールド
絶縁膜、３・・・・・・アルミ・パッド電極、４・・・
・・・アルミナ変換膜、５・・・・・・絶縁保護膜、６
・・・・・・ボンディング・ワイヤ、７・・・・・・封
止用樹脂膜、８，９・・・テ・・レジスト膜、１０・・
・・・・スルー・ホール開口部。
１２ 半’！ 社＠ ｌ ：ｔｉ’＜
フグ。ソイや？ニ フィールド奪ぎＪ−（月ヂ〔７；
側５Ｌ用４吉十月−月臭３二 了ルミ、パッド「木（
４、アルミナ変換膜
５ ミ シｆｉ＃（Ｚ 意ｊ［
（の
ｉ２図
／θズルー・水−ル開ロ音昏
箔２目FIG. 1 is a cross-sectional structural diagram of an aluminum pad electrode portion showing an embodiment of the present invention, and FIGS. 2(a) to 2(d) are diagrams of one manufacturing process of the semiconductor device of the present invention. 1... Semiconductor substrate, 2... Field insulating film, 3... Aluminum pad electrode, 4...
...Alumina conversion film, 5...Insulating protective film, 6
...Bonding wire, 7... Sealing resin film, 8, 9... Te... Resist film, 10...
...Through hole opening. 12 and a half'! Company@l :ti'<
Pufferfish. Soi? 2 field stealing J-(Tsukiji [7;
Side 5L for 4 Yoshi October - Tsuki odor 32 Rumi, pad ``wood ( 4, alumina conversion film 5 Mishi fi # (Z intention j [ (i2 figure / θ Zuru / water - open low sound faint foil) 2nd eye
Claims (1)
形成されるアルミ・パッド電極と、前記アルミ・パッド
電極の縁端部を被覆する前記アルミ・パッド電極材のア
ルミナ変換膜と、前記アルミナ変換膜上で縁端部を被覆
して前記アルミ・パッド電極のスルー・ホール開口部を
形成する絶縁保護膜とを含むことを特徴とする半導体装
置。a semiconductor substrate, an aluminum pad electrode formed on a field insulating film of the semiconductor substrate, an alumina conversion film of the aluminum pad electrode material covering an edge of the aluminum pad electrode, and the alumina conversion film. A semiconductor device comprising: an insulating protective film covering an edge of the aluminum pad electrode and forming a through-hole opening of the aluminum pad electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62041878A JPS63208225A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62041878A JPS63208225A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63208225A true JPS63208225A (en) | 1988-08-29 |
Family
ID=12620528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62041878A Pending JPS63208225A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63208225A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11354797A (en) * | 1999-06-02 | 1999-12-24 | Semiconductor Energy Lab Co Ltd | Mis type semiconductor device and its manufacture |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| EP3182443A4 (en) * | 2014-08-11 | 2017-08-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
-
1987
- 1987-02-24 JP JP62041878A patent/JPS63208225A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US6984551B2 (en) | 1993-01-18 | 2006-01-10 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| US7351624B2 (en) | 1993-01-18 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| JPH11354797A (en) * | 1999-06-02 | 1999-12-24 | Semiconductor Energy Lab Co Ltd | Mis type semiconductor device and its manufacture |
| EP3182443A4 (en) * | 2014-08-11 | 2017-08-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
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