JP2979948B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing disconnection of a wiring layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional multi-chip module (MC)
In the M) element, as shown in JP-A-4-233266, a semiconductor chip is buried in a concave portion formed on the surface side of a substrate, and a wiring layer is formed after an interlayer insulating film is formed.
FIG. 15 shows a plane of this conventional example, and FIG.
FIG. 17 shows an enlarged cross-sectional view of FIG. 15 to 17, the surface 51 of the substrate 51 is shown.
The recesses 52 and 53 are formed by performing the alkali etching on “a”. The surface 51a is a (100) plane. The semiconductor chip 54 has a chip pedestal portion 52 a of the concave portion 52.
On the other hand, on the other hand, the semiconductor chip 55 is
3a are respectively fixed by an adhesive. The insulating layer 56 such as a polyimide layer is formed by a spin coating method (spin coating method), and covers the substrate 51 and the semiconductor chips 54 and 55. Wiring layer (for example, aluminum deposited film) 57
Are disposed on the insulating layer 56, and the semiconductor chips 54, 55
It is connected to the. In the case of a multilayer wiring, the insulating layer 56 and the wiring layer 57 are formed so as to be sequentially laminated.

[0003]

However, in the above-described conventional example, as shown in FIG. 17, since the etching hole width a is wide, the liquid insulating layer material such as polyimide dropped by the spin coating method is used to form the concave portion 52. Easy to escape from.
The etching hole width a is (tan5) of the depth b of the concave portion 52.
5 °) ⁻¹ times, so when b is 200 μm, a is 1
It becomes 40 μm. Normally, the coating thickness of the insulating layer 56 is 10 μm.
And it is impossible to fill the etching holes having such a large etching hole value a at one time.
For this reason, since the depression 56a of the insulating layer 56 remains in the gap between the concave portion 52 and the semiconductor chip 54, a stepped portion 57a may be generated in the wiring layer 57 in some cases. The disconnection of the wiring layer 57 also occurs in the gap between the recess 53 and the semiconductor chip 55. In order to prevent the disconnection, the insulating layer 56 is applied several times so that the surface of the insulating layer 56 is flattened.
Since it is necessary to perform the etch back, the manufacturing process becomes extremely complicated. Therefore, an object of the present invention is to provide a semiconductor device which eliminates the above-described disadvantages of the conventional example, and which can prevent a disconnection of a wiring layer by a simple manufacturing process in which the surface of an insulating layer covering the surface of a semiconductor chip is flat and which prevents disconnection of a wiring layer. It is to provide a manufacturing method.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor device having a surface area smaller than an opening area of a recess by a predetermined amount. In a semiconductor device, a chip is provided, an insulating layer is provided on the surface of the semiconductor chip, a recess around the semiconductor chip, and a surface side of the substrate, and a wiring layer is formed on the insulating layer. That is, it protrudes from the surface of the substrate. Further, according to a second aspect of the present invention, a concave portion is formed on the surface side of the substrate, and a semiconductor chip having a surface area smaller than the opening area of the concave portion by a predetermined amount is disposed in the concave portion. In a method of manufacturing a semiconductor device in which an insulating layer is provided on a concave portion around a chip and a surface side of the substrate and a wiring layer is formed on the insulating layer, the surface of the semiconductor chip is projected from the surface of the substrate;
Forming the insulating layer by rotating the substrate around a rotation center axis perpendicular to the surface thereof, and dropping and solidifying a liquid insulating layer material on the surface side of the substrate and the surface of the chip. .

Further, according to a third aspect of the invention, a semiconductor chip having a surface area smaller than the opening area of the recess by a predetermined amount is disposed in the recess formed on the front surface side of the substrate, and In a semiconductor device in which an insulating layer is provided on a concave portion around a semiconductor chip and a surface side of the substrate, and a wiring layer is formed on the insulating layer, a gap between the periphery of the opening of the concave portion of the substrate and the periphery of the surface of the semiconductor chip is formed. That is, a shielding portion that covers a part is formed. Further, according to a fourth aspect of the present invention, a concave portion is formed on the surface side of the substrate, and a semiconductor chip having a surface area smaller than the opening area of the concave portion by a predetermined amount is disposed in the concave portion. In a method for manufacturing a semiconductor device in which an insulating layer is provided on a concave portion around a chip and on a surface side of the substrate and a wiring layer is formed on the insulating layer, (1) forming a part of the insulating layer on the surface of the substrate (2) forming an opening in the second insulating layer; and (3) forming an opening in the second insulating layer using the second insulating layer as a mask. (4) forming an opening having a larger area than the opening of the second insulating layer in the first insulating layer by isotropically etching the first insulating layer; and (4) forming the first and second insulating layers. The substrate is etched from the openings of both using the layer as a mask to form the recesses. And a step of

[0006]

According to the structure of the first aspect of the present invention, since the surface of the semiconductor chip is projected from the surface of the substrate, a liquid insulating layer material is dropped on the surface side of the substrate and then solidified to form an insulating layer. When the semiconductor chip becomes a weir of the liquid insulating layer material, the formation of the insulating layer becomes easy, and dents are not easily formed in the gap between the semiconductor chip and the concave portion formed on the surface side of the substrate. . As a result, the surface of the insulating layer becomes smooth and tends to be flat, so that disconnection of a wiring layer formed on the insulating layer can be prevented. Further, according to the configuration of the second aspect, the surface of the semiconductor chip is projected from the surface of the substrate, and the substrate is rotated around a rotation center axis perpendicular to the surface, so that the liquid insulating layer material is transferred to the surface of the substrate. Since the insulating layer is formed by being dropped on the side and the surface side of the semiconductor chip and then solidified, it is a method particularly suitable for manufacturing the semiconductor device of the first invention described above.

Further, according to the structure of the third aspect of the present invention, since the shielding portion that covers a portion between the periphery of the opening of the concave portion of the substrate and the periphery of the surface of the semiconductor chip is formed, the above-mentioned liquid insulating layer material is formed. Becomes difficult to get outside when it enters between the concave portion of the substrate and the semiconductor chip. As a result, dents on the surface of the insulating layer are reduced, so that the surface of the insulating layer becomes smooth and flattened, whereby disconnection of a wiring layer formed on the insulating layer can be prevented. Further, according to the structure of the fourth invention, in the step (1), a first insulating layer and a second insulating layer are sequentially formed on the surface of the substrate, and then in the step (2), the second insulating layer is formed. An opening is formed in the layer, and then the opening of the first insulating layer formed in step (3) is wider than the opening of the second insulating layer. Is formed, and in the step (4), the recesses formed in the substrate from both the openings become the locations where the semiconductor chips are arranged. As a result, the overhang portion becomes a shielding portion that covers a portion between the periphery of the opening of the concave portion of the substrate and the semiconductor chip.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a sectional structure of one embodiment of the first invention. In FIG. 1, a concave portion 1 is provided on the surface 11a side of the substrate 11.
2 and 13 are formed by alkali etching.
The semiconductor chip 14 is fixed to the chip pedestal portion 12b of the concave portion 12 by bonding or the like. In addition, the semiconductor chip 14
Is formed smaller by a predetermined amount than the area of the opening 12a of the concave portion 12. On the other hand, the semiconductor chip 15 is fixed to the chip pedestal portion 13b of the concave portion 13 by bonding or the like. Also, the surface 15a of the semiconductor chip 15
Is formed smaller than the area of the opening 13a of the recess 13 by a predetermined amount. The surfaces 14a and 15a of the semiconductor chips 14 and 15 project from the surface 11a of the substrate 11. The insulating layer 16 is formed on the surface 11 a of the substrate 11 so as to cover the substrate 11 and the semiconductor chips 14 and 15. Further, a wiring layer 17 is formed on the insulating layer 16.

With the above configuration, the semiconductor chip 14,
Since the surfaces 14a and 15a of the substrate 15 protrude from the surface 11a of the substrate 11, the insulating layer 16 is coated by the spin coating method (the substrate 1).
1 is rotated around a rotation center axis perpendicular to its surface 11a, and a liquid insulating layer material 16b such as polyimide is
The semiconductor chips 14 and 15 serve as weirs for the liquid insulating layer material 16b. Therefore, the liquid insulating layer material 16 is formed in the gap between the concave portions 12 and 13 and the semiconductor chips 14 and 15.
Since b easily gathers, no dent of the insulating layer 16 is formed in this gap. As a result, the surface 16a of the insulating layer 16 can be made flat. Therefore, the surface 1 of the insulating layer 16
The disconnection of the wiring layer 17 formed on 6a can be prevented. Further, photolithography, etching, and resist removal of the wiring layer 17 are facilitated. Further, as described above, since the surfaces 14a and 15a of the semiconductor chips 14 and 15 are projected from the surface 11a of the substrate 11,
The depth of 2 and 13 becomes shallow. For this reason, the etching time of the substrate 11 can be shortened and the warpage of the substrate 11 can be reduced.

FIGS. 2 to 4 show a manufacturing process of an embodiment of the second invention. 2 to 4 correspond to FIG. First, in FIG. 2, concave portions 12 and 13 are formed on the surface 11a side of the substrate 11 by etching. Surface 11a
Is a (100) plane, and the concave portion 12 is formed by etching.
The side surface of 13 is expanding upward. Next, the semiconductor chip 14 is fixed to the chip pedestal portion 12b of the concave portion 12 by bonding or the like. Further, the semiconductor chip 15 is fixed to the chip pedestal portion 13b of the concave portion 13 by bonding or the like. At this time, the surfaces 14a, 15a of the semiconductor chips 14, 15 are made to protrude from the surface 11a of the substrate 11. Next, as shown in FIG. 3, the liquid insulating layer material 16b is dropped on the rotating substrate 11 as described above. Next, as shown in FIG. 4, the dropped liquid insulating layer material 16b is solidified by heat treatment to form the insulating layer 16.

FIG. 5 shows a sectional structure of the first embodiment of the third invention. In FIG. 5, the surface 21a of the silicon substrate 21
Recesses 22 and 23 are formed on the side by alkali etching. The bottom surfaces of the recesses 22 and 23 are
b and 23b. The semiconductor chip 24 is the chip base 2
2b is fixed with an adhesive 26. Here, the area of the surface 24a of the semiconductor chip 24 is
It is formed smaller than the area of a by a predetermined amount. The semiconductor chip 25 is fixed to the chip pedestal 23b with an adhesive 26. Similarly, the area of the surface 25 a of the semiconductor chip 25 is formed smaller than the area of the opening 23 a of the recess 23 by a predetermined amount.

A first insulating layer 27 such as silicon oxide and a second insulating layer 2 such as silicon nitride
8 are sequentially laminated. In the second insulating layer 28, an overhang portion 28b is formed at the opening 22a, and an overhang portion 28c is formed at the opening 23a. The insulating material layer 29 of polyimide or the like
2, 23, semiconductor chips 24, 25 and second insulating layer 28
Is formed so as to cover the surface 28a. The wiring layer 30 of aluminum or the like is provided on the surface 29 a of the insulating material layer 29 and is connected to the semiconductor chips 24 and 25.

With the above configuration, the concave portions 22 of the substrate 21
23 around the openings 22a, 23a and the semiconductor chip 24;
The overhang portions 28b, 28c of the second insulating layer 28 as a shielding portion covering a portion between the surfaces 24a, 25a of the second insulating layer 28.
Are formed. As a result, when the liquid insulating material is spin-coated, the overhang portions 28b and 28c serve as weirs of the liquid insulating material, so that the liquid insulating material that enters the gaps between the semiconductor chips 24 and 25 and the concave portions 22 and 23 is formed. Since the material does not easily flow out, the liquid insulating material easily accumulates in the gap. When this liquid insulating material is solidified by heat treatment, it becomes an insulating material layer 29. As a result, the dent of the insulating material layer 29 can be reduced.
Surface 29a can be improved in flatness. Therefore, disconnection of the wiring layer 30 can be prevented.

FIGS. 6 to 9 show a manufacturing method according to the first embodiment of the fourth invention. This manufacturing method corresponds to the above-described first embodiment of the third invention (see FIG. 5). First, as shown in FIG. 6, on the surface 21a of the silicon substrate 21,
The first insulating layer 27 and the second insulating layer 28 are sequentially stacked. Next, as shown in FIG. 7, the first insulating layer 27 and the second
The insulating layer 28 is dry-etched, and the surface 21 of the substrate 21 is
The portions 21b and 21c of a are exposed. At this time, the area of the portions 21b and 21c is the same as that of the semiconductor chip 2 described above.
4 and 25 are larger than the areas of the surfaces 24a and 25a by a predetermined amount. Next, as shown in FIG. 8, the first insulating layer 27 is side-etched by wet etching using the second insulating layer 28 as a mask. Here, the wet etching is one type of isotropic etching, and another isotropic etching may be used. As a result, the second insulating layer 28 is
An opening having a larger area than the opening is formed, and overhang portions 28b and 28c are formed in the second insulating layer 28.
The amount of side etching at this time is controlled in consideration of the taper angle of the substrate 21 due to alkali etching.
Next, as shown in FIG.
The recesses 22 and 23 having a depth corresponding to the thickness of the substrate 5 are formed by alkali etching of the surface 21 a of the substrate 21. FIG. 10 shows the relationship between the amount of overhang of the overhang portions 28b and 28c and the amount of depression when the depths of the concave portions 22 and 23 are 300 μm. When the overhang portions 28b and 28c are not present, the dent amount is 100 μm or more. However, the dent amount decreases as the overhang amount increases, and the insulating material layer 2
9 improves the flatness of the surface 29a. If the amount of overhang is excessive, voids are generated in the insulating material layer 29 and the reliability is reduced. Therefore, it is necessary to prevent the amount of overhang from becoming excessive.

FIG. 11 shows a sectional structure of a second embodiment of the third invention. In FIG. 11, concave portions 32 and 33 are formed on the surface 31a side of the substrate 31. Semiconductor chip 34
Are fixed to the chip pedestal portion 32b of the concave portion 32 with an adhesive or the like. Here, the surface 34a of the semiconductor chip 34
Project from the surface 31 a of the substrate 31. An overhang portion 34b is formed around the surface 34a of the semiconductor chip 34, and the area of the surface 34a is smaller than the area of the opening 32a of the recess 32 by a predetermined amount. Semiconductor chip 35
Is fixed to the chip pedestal portion 33b of the concave portion 33 with an adhesive or the like. Here, the surface 35a of the semiconductor chip 35
Project from the surface 31 a of the substrate 31. An overhang portion 35b is formed around the surface 35a of the semiconductor chip 35, and the area of the surface 35a is smaller than the area of the opening 33a of the recess 33 by a predetermined amount.

With the above structure, when the liquid insulating material is spin-coated on the concave portions 32 and 33, the overhang portion 3
4b and 35b are the above-mentioned overhang portions 28b and 28c.
(See FIG. 9). Therefore, disconnection of a wiring layer (not shown) (similar to the wiring layer 30 shown in FIG. 5) can be prevented.

FIGS. 12 to 14 show a manufacturing method according to a second embodiment of the fourth invention. This manufacturing method corresponds to the above-described second embodiment of the third invention (see FIG. 11).
FIG. 12 shows a step of dicing the semiconductor wafer 41. In FIG. 12, when the dicing blade 42 rotating at high speed in the direction of the arrow 42a advances in the direction of the arrow 42b, the wafer 41 fixed by a device (not shown) is diced along the dicing lines 41a, 41b, 41c. FIG. 13 shows a front view of the dicing blade 42. FIG. 14 shows the semiconductor chips 43a, 43b, 43c and 43d formed by the above dicing. The semiconductor chips 43a to 43d correspond to the above-described semiconductor chips 34 and 35 (see FIG. 11).

[0018]

As described above in detail, according to the semiconductor device and the method of manufacturing the same of the present invention, the surface of the insulating layer covering the surface of the semiconductor chip can be flattened.
Disconnection of the wiring layer formed on the insulating layer can be prevented, and photolithography, etching, and resist removal of the wiring layer can be facilitated. Further, the etching time of the substrate can be reduced, and the warpage of the substrate can be reduced. Therefore, the reliability of the semiconductor device can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of the first invention.

FIG. 2 is a cross-sectional view showing a manufacturing process according to an embodiment of the second invention.

FIG. 3 is a cross-sectional view showing a manufacturing step of the embodiment of the second invention, which is a continuation of FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing step of the embodiment of the second invention, which is a continuation of FIG. 3;

FIG. 5 is a sectional view of the first embodiment of the third invention.

FIG. 6 is a sectional view showing a step of the first embodiment of the fourth invention.

FIG. 7 is a sectional view showing a step of the first embodiment of the fourth invention, which is a continuation of FIG. 6;

FIG. 8 is a sectional view showing a step of the first embodiment of the fourth invention, and is a continuation of FIG. 7;

FIG. 9 is a sectional view showing a step of the first embodiment of the fourth invention, which is a continuation of FIG. 8;

FIG. 10 is a graph showing characteristics of the fourth invention.

FIG. 11 is a sectional view of a second embodiment of the third invention.

FIG. 12 is an explanatory view of a second embodiment of the fourth invention.

FIG. 13 is a front view of a dicing blade according to a second embodiment of the fourth invention.

FIG. 14 is an explanatory diagram of a semiconductor chip according to a second embodiment of the fourth invention.

FIG. 15 is a plan view of a conventional example.

16 is a sectional view taken along line AA of FIG.

FIG. 17 is a partially enlarged view of FIG. 16;

[Explanation of symbols]

REFERENCE SIGNS LIST 11 substrate 11a substrate surface 12, 13 concave portion 12a, 13a concave portion 12, 13 opening portion 14, 15 semiconductor chip 14a, 15a semiconductor chip 14, 15 surface 16 insulating layer 16b liquid insulating layer material 17 wiring layer 21 Substrate 21a Surface 22, 23 of substrate 21 Depression 22a, 23a of substrate 21 Opening 24, 25 of semiconductor substrate 24, 25a Semiconductor chip 24a, 25a Surface of semiconductor chip 24, 25 27 First insulating layer 28 Second insulating layer 28b, 28c Overhanging portion of second insulating layer 28 29 Insulating material layer 30 Wiring layer 31 Substrate 31a Surface of substrate 31 32, 33 Depression 32a, 33a of substrate 31 Opening of depression 32, 33 Semiconductor chip 34a, 35a Surfaces 34b, 35b of semiconductor chips 34, 35 Bahangu part

Claims (4)

(57) [Claims] A semiconductor chip having a surface area smaller than an opening area of the concave part by a predetermined amount in a concave part formed on the front surface side of the substrate; 2. A semiconductor device comprising: an insulating layer provided on a surface side of a semiconductor device; and a wiring layer formed on the insulating layer, wherein a surface of the semiconductor chip is projected from a surface of the substrate. 2. A concave portion is formed on the front surface side of a substrate, and a semiconductor chip having a surface area smaller than the opening area of the concave portion by a predetermined amount is disposed in the concave portion. A method for manufacturing a semiconductor device, comprising: providing an insulating layer on a surface side of the substrate, and forming a wiring layer on the insulating layer; protruding a surface of the semiconductor chip from a surface of the substrate; A method for manufacturing a semiconductor device, comprising forming an insulating layer by rotating the liquid insulating layer material around a rotation center axis and dropping and solidifying a liquid insulating layer material on a surface side of the substrate and a surface of the chip. 3. A semiconductor chip having a surface area smaller than the opening area of the concave portion by a predetermined amount in a concave portion formed on the front surface side of the substrate, and a concave portion on the surface of the semiconductor chip and around the semiconductor chip and the substrate. A semiconductor device having an insulating layer provided on the surface side of the semiconductor device and a wiring layer formed on the insulating layer, wherein a shielding portion is formed to cover a portion between the periphery of the opening of the concave portion of the substrate and the periphery of the surface of the semiconductor chip. A semiconductor device characterized by the following. 4. A concave portion is formed on the surface side of the substrate, and a semiconductor chip having a surface area smaller than the opening area of the concave portion by a predetermined amount is disposed in the concave portion. In a method for manufacturing a semiconductor device, wherein an insulating layer is provided on a surface side of the substrate and a wiring layer is formed on the insulating layer, (1) a first insulating layer constituting a part of the insulating layer on a surface of the substrate And (2) forming an opening in the second insulating layer; and (3) forming the first insulating layer through the opening using the second insulating layer as a mask. Forming an opening having a larger area than the opening of the second insulating layer in the first insulating layer by isotropic etching, (4) using the first and second insulating layers as masks, Etching the substrate from the opening to form the recess. The method of manufacturing a semiconductor device, characterized by Bei.