JPH08279295A - Storage system including nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE: To enable a refreshing control means to hold correct data by reading out all the data belonging to a storage area including the read-out data as the count subject of an information storing part when the data read-out count exceeds a read-out reference and re-writing all the data in the storage area via an error-correcting circuit. CONSTITUTION: A readout counter 13 counts readout count from a nonvolatile memory cell array 1 by CPU 16, and outputs a signal to start up refreshing operation when the count is equal to or higher than a preset reference value for comparison. A refreshing command is supplied to a command input/output buffer 8 of a main memory body 10 and the refreshing is operated. In the refreshing operation, the data written in the memory are read out and errors are corrected before re-written in the memory. Refreshing of nonvolatile semiconductor memory is thereby performed at an effective time of ECC correction, and correct data are held.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of an electrically rewritable non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a stored data refresh function to improve reliability of held data. Regarding the device.

[0002]

2. Description of the Related Art As an electrically rewritable nonvolatile semiconductor memory device, for example, as shown in FIGS. 15 and 16, a highly integrated NAND type EEPROM (Electri) can be used.
cally Erasable PROM) is known. FIG.
FIG. 15A shows a pattern of memory cells for one column of the EEPROM, and FIG. 15B shows an electrically equivalent circuit thereof. In the figure, SG1 and SG2 are selection lines, CG1 to CG8 are control gate lines, BL is a bit line, S1 and S2 are selection transistors, and M1 to
M8 is a memory cell. 16 (a) and FIG.
6 (b) shows A-, which are shown in FIG. 15 (a), respectively.
FIG. 2 schematically shows cross-sectional views of the semiconductor device along the A ′ direction and the BB ′ direction. In both figures, 211 is a semiconductor substrate, 212 is an insulating film for element isolation, 213 is an insulating film (tunnel oxide film) for a channel portion, 214 is a floating gate, 215 is an inter-gate insulating film, 216 is a control gate, and 217 is a control gate. The insulating film 218 is a metal bit line (B
L) and 219 are high-concentration impurity regions for forming source / drain regions. The NAND type EEPROM has a plurality of memory cells M as shown in FIGS.
1 to M8 are connected in series so that their sources and drains 219 are shared by adjacent ones, and these are connected as one unit to the bit line BL.

Each memory cell M usually has a FETMOS structure in which a charge storage layer and a control gate 216 are laminated. The memory cell array includes a P-type or N-type substrate 211.
Integrated in the P-type well formed in the above. NAND
The drain side of the cell is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously connected in the row direction to form word lines. A plurality of such memory cell columns are provided to form an actual memory cell array of the EEPROM as shown in FIG.

Next, the operation of the NAND type EEPROM will be described. As shown in FIG. 17, writing and reading of data are performed for each memory cell sharing a word line (CGi). This unit is called a page.
Data is erased for each memory cell transistor sharing all word lines (for example, CGi01 to CGi16) between two drain-side and source-side select gates (for example, SGi1 and SGi2). This unit is called a block.

To write data, a high voltage of about 20 V is applied to the control gate of the selected memory cell transistor, and 10 is applied to the control gate of the non-selected memory cell transistor of the selected block and the drain side selection gate of the selected block.
An intermediate voltage of about V is applied. In addition, 0V is applied to the source side select gate of the selected block and the select gate of the non-selected block.
Is applied, and 0 V is applied to the bit line BL according to the write data.
Alternatively, it is performed by applying an intermediate voltage of about 8V, respectively. The voltage applied to the bit line BL is transmitted to the channel of the selected memory cell transistor,
When V is applied, electrons are injected from the channel to the floating gate, and the threshold voltage of the selected memory cell transistor shifts in the positive direction. When 8V is applied, electron injection does not occur and the threshold voltage of the memory cell transistor does not change.

To erase data, 0V is applied to all control gates of the selected block, and a high voltage of about 20V is applied to all control gates of the P-type substrate or N-type substrate and P-type well, all selection gates and non-selected blocks. It is performed by applying each. The bit line and the source line are set in a floating state. As a result, electrons in the floating gate are emitted to the channels in all the memory cell transistors in the selected block, and the threshold voltage shifts in the negative direction. On the other hand, the threshold voltage of the memory cell transistor in the non-selected block does not change.

For reading, 0V is applied to the control gates of the selected memory cell transistors, and the power supply voltage is applied to the control gates and the selection gates of the other memory cell transistors, so that the transistors other than the selected memory cell transistors are turned on. Then, it is performed by detecting whether or not a current flows through the selected memory cell transistor.

In a conventional nonvolatile semiconductor memory device, an error detection / correction circuit (EC
C) is provided, and the data read from the memory is error-corrected by ECC.

[0009]

However, as is apparent from the above description of the operation, the NAND type EEP is used.
In the ROM, since the non-selected memory cell transistor is used as a transfer gate during the read operation, the electric field applied between the gate of the non-selected memory cell transistor and the charge storage layer and between the charge storage layer and the channel which are not read out. The signal charge stored in the charge storage layer escapes between the gates or the channels, or on the contrary, the charge is injected into the charge storage layer, so that the signal data stored in the memory cell transistor is inverted (threshold value). Transition)
Can happen.

FIG. 2 is a graph of the number of read times versus the number of error bit occurrences, showing a state in which error bits appear in the data held in all the memories when the data in the memory cell at a specific address is continuously read. It represents. From this figure, if these data are read while the number of errors that can be corrected is small, the ECC
It turns out that it is possible to restore the original correct data. However, it can also be seen that when only a specific address is accessed, data inversions overlap in the same block of memory cells, and finally error correction by ECC becomes impossible.

Therefore, according to the present invention, in the conventional nonvolatile semiconductor memory device, the data read from the memory is E
Although the error is corrected by the CC, the error is accumulated in the data of the memory cell which is not read,
The purpose is to solve the problem that correction by ECC becomes impossible in due course.

[0012]

To achieve the above object, a storage system including a non-volatile semiconductor storage unit of the present invention is
An information storage unit having one or a plurality of storage regions each composed of a non-volatile memory cell group in which data can be rewritten, and an error in data read from the information storage unit is detected,
An error detection / correction circuit that corrects and outputs an error in read data, a read number counter that counts the reading of data from the information storage unit, and a refresh control unit that rewrites data held in the information storage unit. When the count value for reading the data exceeds a read reference value, the refresh control means reads all data belonging to a storage area including the read data that is the target of the count from the information storage unit, The read data is rewritten in the storage area via the error detection / correction circuit.

Further, a storage system including a nonvolatile semiconductor storage unit of the present invention includes an information storage unit having one or a plurality of storage regions each composed of a data rewritable nonvolatile memory cell group, and the information storage unit. An error detection / correction circuit that detects an error in the data read from the data and corrects and outputs the error in the read data, an error number counter that counts the error in the detected data, and an error number counter that stores the data stored in the information storage unit. Refresh control means for performing rewriting, wherein the refresh control means includes read data which has been subjected to the error correction from the information storage section when the error count value of the data exceeds an error reference value. All the data belonging to the storage area is read, and the read data is rewritten in the storage area via the error detection and correction circuit. That.

Further, a storage system including a nonvolatile semiconductor storage unit of the present invention includes an information storage unit having one or a plurality of storage regions each composed of a rewritable nonvolatile memory cell group, and reading from the information storage unit. Error detection / correction circuit that detects an error in the data to be read and corrects and outputs the error in the read data, an error number counter that counts the error in the detected data, and a count of the data read from the information storage unit. Read counter and refresh control means for rewriting the data held in the information storage section, wherein the refresh control means has a read count value of the data exceeding a read reference value and the data When the count value of the error exceeds the error reference value, all the data belonging to the storage area including the read data targeted for each count from the information storage unit Read, the read data via the error detecting and correcting circuit writes again written in the storage area, and wherein the.

Further, a storage system including a nonvolatile semiconductor storage unit of the present invention includes an information storage unit having one or a plurality of storage regions each composed of a data rewritable nonvolatile memory cell group, and the information storage unit. A read counter for counting the reading of data from the memory, a buffer memory for temporarily storing the data, and a refresh control unit for rewriting the data held in the information storage unit. When the count value of the data read exceeds the read reference value, all the data belonging to the storage area including the read data which is the target of the count is read from the information storage unit to the buffer memory, and the read data is all the data. It is characterized in that the data is rewritten to the read storage area or another storage area other than this storage area.

[0016]

According to the present invention, since all data or partial data written in the non-volatile semiconductor device is rewritten (refreshed) when the ECC correction is effective, the data which has not been read is retained. Even if an error has occurred in the memory cell due to the read stress of other data, the number of errors is less than the number of ECC correctable errors, so the data is corrected and re-recorded.

According to another aspect of the present invention, the data written in the non-volatile semiconductor device is refreshed at a time when the error occurrence rate which does not require ECC correction is extremely low.

As a result, the frequency of errors that exceed the error correction capability of the ECC can be reduced to a level that does not pose a problem in actual use.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 1 is a NAND, for example.
Memory cell array consisting of a type EEPROM, 2 is a word line drive circuit for driving a designated word line, 3 is a row decoder for instructing the word line drive circuit 2 to drive a word line corresponding to a given address signal, and 4 is a row decoder. A control circuit for driving the instructed bit line, 5 a column decoder for instructing the drive of a bit line corresponding to an applied address signal, 6 an address buffer for temporarily holding an address signal, and 7 for temporarily holding input / output data. A data input / output buffer 8 is a command input / output buffer for temporarily holding a command given to the memory. These components 1 to
The main body 10 of the non-volatile semiconductor memory device, which is an information storage unit, is constituted by 8.

Further, 11 is an ECC (error detection / correction circuit) for performing error check and error correction of read data. The ECC 11 includes, for example, Reed Solomon (Reed
-An error correction method using a Solomon code can be used. Of course, various other error correction schemes including parity check can be used. ECC
Reference numeral 11 has a function of adding additional bits or information for restoring the original data by error correction to the data and storing it in the memory cell array. Further, in order to determine whether or not the error correction is executed, , An error number counter for counting the number of errors. Reference numeral 12 is a main memory of the CPU or a buffer memory provided between the CPU and a nonvolatile memory in the IC memory card, and 13 is a memory cell array 1
A read number counter for counting the number of read times from the CPU, 16 is a CPU of a computer system having a function of controlling an EEPROM for data processing, 14 is a data line (data bus) for transmitting data between the ECC 11 and the CPU 16, and 15 Is the command input / output buffer 8 and the CPU 1.
A control line for transferring a control signal between 6 and 17, an address line for transmitting an address signal from the CPU 16 to the address buffer 6, and a signal line for connecting 18 among the ECC 11, the buffer memory 12 and the read number counter 13.

The data transmission between the ECC 11 and the CPU 16 can be performed via the buffer memory 12 as shown by the dotted line in FIG. Further, the data line 14 can be configured by a common data bus that connects the ECC 11, the buffer memory 12, other functional parts, and the CPU 16 to each other.

The CPU 16 may be a CPU that processes data in a computer system,
It is also possible to use a dedicated CPU (control device) to control writing and reading of data to and from the storage device. The CPU 16 constitutes refresh control means.

Next, the operation of the storage system will be described. The CPU 16 is usually the main body portion 1 of the non-volatile memory.
For 0, the following three modes of operation are performed.

For data writing, data to be written in the data input / output buffer 7 is supplied from the CPU 16 via the data line 14 and the ECC 11. In addition, the CPU 16
From, the write command is supplied to the command input / output buffer 8 via the control line 15, and the write address is supplied to the address buffer 6 via the address line 17, respectively. As a result, data is written in the memory cell corresponding to the specified address in the memory cell array 1.

Data is erased by the CPU 16 supplying an erase command to the command input / output buffer 8 via the control line 15 and an address signal to the address buffer 6 via the address line 17. , The data of the corresponding memory cell in the addressed memory cell array 1 is cleared.

Data reading is performed by supplying a read command from the CPU 16 to the command input / output buffer via the control line 15 and supplying a read address to the address buffer 6 via the address line 17. The data read from the memory cell of the corresponding address in the memory cell array 1 is output to the data line 14 via the bit line control circuit 4, the data input / output buffer 7 and the ECC 11, and taken into the CPU 16.

Next, a refresh operation for preventing an error in stored data (change in threshold value of a set transistor) due to a read stress and correcting an error will be described.

The read number counter 13 used in the refresh operation is a counter (not shown) that counts the number of times of reading from the memory cell array 1, and a comparator (not shown) that compares the count value with a comparison reference value set in a register (not shown). , And outputs a signal for activating the refresh operation when the read count value is equal to or exceeds a preset reference value for refresh. There are various modes of counting the reading. For example, as described above, the memory body 10
When the read commands to the memory are simply accumulated, the memory body 10
When the access is divided for each block in the memory cell array 1 and the number of read accesses for each block is counted in consideration of the read command and the designated address, For example, the number of readings is counted for each cluster, the number of readings is counted for each cell in the memory cell array 1, or the number of times of reading is appropriately combined. Appropriate ones are selected from the viewpoints of required accuracy and cost. First
In this embodiment, the read accesses to the memory body 10 are integrated and the total number of read times (or the number of read commands) is monitored.

The read count value in the read number counter 13 at the end of use of the computer system is stored in a predetermined position of the memory cell array 1 together with the parameter data to be saved, for example, when a power shut-down routine (not shown) is executed. It Then, when the computer system is started up next time, it is read and input to the read number counter 13 via the ECC 11, and the total read number from the previous refresh to the present is set as the initial value of the present counter. Every time the CPU 16 reads from the memory cell array 1, the value of the read number counter 13 is incremented by one. When the total read number becomes equal to the reference value, the read number counter 13 outputs a refresh command. This refresh command is supplied to the command input / output buffer 8 of the memory body 10. The memory body 10 performs a refresh operation in response to the refresh command. During this refresh operation, writing of data from the outside and reading to the outside cannot be performed. Therefore, the memory body 10 sends a busy signal indicating that it does not accept another command from the command input / output buffer 8 via the control signal line 15 to the CP.
Supply to U16. In the refresh operation, the data written in the memory is read, the error is corrected, and the data is written again in the memory. By this processing, the threshold value of each cell transistor of the EEPROM is reset.

First, according to a read mode in which a read command and a series of addresses are sequentially given to the memory body 10, data of all memory cells to be refreshed is transferred from the memory cell array 1 through the data input / output buffer 7 and the ECC 11. Are sequentially read into the buffer memory 12. EC
Data is corrected for errors when passing through C11.
After that, the data held in all the memory cells of the memory cell array 1 are erased and reset. Next, a write mode is performed in which a write command and a series of addresses are sequentially given to the memory body 10. All the data held in the buffer memory 12 is rewritten in the memory cell array 1 via the ECC 11 and the data input / output buffer 7. In the refresh operation, since the error is corrected by the ECC 11, if there are few error bits, error-free data is restored and rewritten in the memory cell array 1. When the writing of all data is completed, a ready signal indicating that the refresh operation is completed is output from the command input / output buffer 8 and input to the CPU 16 and the read number counter 13. The count value of the read number counter 13 is reset by this signal, and the total read number is set to zero.

Immediately before the end of the computer system or the storage system, as described above, the previous total read number stored in the memory cell 1 is rewritten to the total read number of the present read number counter 13 ( Will be updated).

FIG. 3 is a block diagram for explaining the second embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

This embodiment differs from the first embodiment shown in FIG. 1 in that a read number counter 13 is provided in the memory body 10 and a storage area corresponding to the buffer memory 12 is provided in the memory cell array 1. The external buffer memory 12 is unnecessary by allocating the buffer memory 12 in a partial area. With such a configuration in which a plurality of memory bodies 10 are provided, it is possible to easily cope with a configuration that employs so-called memory interleaving.

The ECC 11 and the plurality of memory bodies 10
In addition to the bus connection, can be connected via a multiplexer. It is also possible to provide the ECC 11 and the CPU 16 for each memory body 10.

A refresh algorithm for refreshing each cluster of the memory cell array according to the third embodiment of the present invention will be described with reference to the flow chart shown in FIG. In this example, the read count is recorded in the non-volatile memory for each cluster. The cluster is a unit for refreshing the memory cell array, and corresponds to, for example, one or a plurality of blocks or chips in the memory cell array 1.

First, the semiconductor memory device is powered on,
When a power-on reset circuit (not shown) is activated, FIG.
As shown in (a), the total number of read times of n is read for each of the first to nth clusters held in the nonvolatile memory 1 by the output (S2). Total read count Y of the i-th cluster
i represents the total number of read times from the previous refresh to the present, and is stored in, for example, a specific area in the i-th cluster. The total read number Y1 to Yn of each read cluster is preset in a plurality of counting registers of the counter 13 that counts the total read number (S4).

Next, as shown in FIG. 4B, the reading of data from the nonvolatile memory device is monitored. Every time data is read to the cluster i (S12), the counter 13 sets the total read count number Yi of the cluster i to 1
Only (S14), and it is determined whether the total number of times of reading Yi has reached the preset maximum number of times of reading Yc (S16).

When the total read number Yi is equal to or exceeds the reference value Yc, the refresh operation is performed (S1).
6). At the time of refresh, a busy signal (flag) indicating that access to the storage device is impossible is set and output to the CPU 16. After that, ECC is sequentially performed for each block belonging to the cluster i in the memory cell array 1 from the first page.
Sequentially, if there is an error, the corrected data is written, and if there is no error, the data is written into the buffer memory of the same size as the cluster sequentially (S
18). When all the data in the i-th cluster are written in the buffer memory, all the blocks in the cluster i are forcibly erased (S20), and the corrected data is written again in the same cluster (S22). Total read count Yi is “0”
And the read number counter corresponding to the i-th cluster is reset (S24). Finally, the ready signal (flag) is set, the busy signal is reset, and the refresh operation ends (S24).

In step S18, the data in the block can be sequentially written in the buffer memory without being corrected by the ECC. Reference value Yc
If is set to a value with which the probability of error occurrence is small, the refresh is simply repeated, and the level transition of the held data is prevented with a simpler circuit configuration. In addition, in step S22, when writing data, it is possible to change the memory location and write to another vacant cluster or block. In this case, for example, the block address is corrected by the operating system of the computer system or by the address changing function prepared in the hardware of the memory body.

When an operation of turning off the power supply of the apparatus of the computer system is performed, a power-off reset command is input, or an operation of ending the program is performed, FIG.
As shown in (c), the shutdown routine is executed. The total number of times of reading Y1 to Yn for each cluster of the memory written in the nonvolatile memory 1 is updated to the current value of the counter and held (S6).

A method of setting the reference read number Yc which is a reference for starting the refresh operation in the embodiment of the present invention will be described with reference to FIG. When the memory data of a specific address is continuously read, the expected value of the number of times X of reading, which is erroneous by one bit for the first time, is about 100,000 times in the case of the EEPROM. Set to 10,000 times. This gives 1
ECC with correction capability for 1-bit error in page
Even when using, the frequency of errors that exceed the error correction capability of ECC, that is, the error frequency of 2 bits or more, can be reduced to such an extent that it does not pose a problem in practical use. Of course, it is possible to set a large refresh reference value by using a ECC having a higher error bit correction capability.

On the contrary, if the reference number of times of reading Yc is set to a value with a sufficiently low probability of error occurrence, even in a system having no ECC, refresh is performed before the error occurs and bit error occurrence is performed. It is possible to prevent it in advance.

FIG. 5 is a block diagram showing the configuration of the fourth embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and description of such parts will be omitted.

When the reference read number Yc is set to be sufficiently smaller than the expected value of the read number in which a 1-bit error occurs for the first time when the memory data of the specific address is continuously read, the total read number Yi is set in advance. It is not necessary to execute the refresh operation every time when it becomes equal to the reference value Yc. This is because the probability of error within the total number of times of reading Yi is sufficiently low, and the read data is error-corrected by the ECC. On the other hand, since refreshing requires a certain amount of time, it may be desirable to reduce the number of process execution waits depending on the work content of the computer system.

Therefore, in this embodiment, the total number of readings Y
When i becomes equal to the reference value Yc, when the data in the i-th cluster has an error, or when the number of errors Ei exceeds the preset error tolerance Ec,
The refresh operation is performed. When the total reading number Yi becomes equal to the reference value Yc, the reading number counter 1
3 issues a signal to the memory body 10 to read all the data of the i-th cluster. These data are sequentially
It is read into the buffer memory 12 via CC11.
The syndrome calculation ends at the same time when all the data is output. This result is input to the error number comparator 101,
It is compared with a preset error count tolerance. If the number of errors is smaller than the reference value, the read number counter 13 is only reset and the refresh operation for the data is not performed. If the number of errors is equal to or larger than the reference value, refresh is executed. That is, the read counter 13 is reset and the contents of all memory cells of the i-th cluster are stored in the buffer memory 1.
Evacuated in 2 After the data of all the memory cells in the cluster are reset, the data error-corrected by the ECC 11 is rewritten in the memory cell array 1.

In this way, even when the total number of readings Yi of the cluster i is equal to or exceeds the reference value Yc,
When the number of data errors Ei in the i-th cluster is smaller than the preset allowable error value Ec, the original data can be restored by the ECC, and the refresh operation is not performed on the data, so data erasing and rewriting are omitted. it can.

FIG. 6 is a flow chart showing the refresh algorithm of the non-volatile semiconductor memory device according to the fourth embodiment.

As shown in FIG. 4 (a), when the power is turned on, the total number of readings Yi from the previous refresh of all clusters to the previous reading is automatically read (S2), and the total number of readings is counted. The counter is preset (S4). After that, the CPU 16 monitors the reading of data from the nonvolatile semiconductor memory device 10. When the data is read (S12), the total read count number Yi is incremented by 1 by the counter (S14), and it is determined whether or not the total read number Yi reaches a preset reference read number Yc (S16). When the total number of times of reading Yi becomes equal to the reference value Yc, all the data are read and the ECC
It is stored in the buffer memory 12 via 11 (S1
8). The error in these data is judged by the ECC 11, and the number Ei is counted by the error number counter in the ECC 11. The error count Ei is the error count comparator 10
1 is compared with a preset allowable value Ec of 1 (S1
9). It should be noted that the allowable value Ec can be changed as appropriate, as will be described later with reference to FIG. If the number of errors Ei exceeds the allowable value Ec, all blocks in the i-th cluster are erased (S20), the error-corrected data is written again in the same cluster, and the data is refreshed ( S22). After that, the total read number Yi for the cluster i is rewritten to “0”,
It is reset (S24). On the other hand, if the number of errors does not exceed the allowable value (S19), the data is not erased and rewritten (S20, S22), and the total read number Yi is rewritten to 0 and reset (S24).

Such a monitor routine (S12-S)
24) is repeated and executed so that the cluster i
The write data of ~ n are refreshed.

When the operation of turning off the power of the apparatus or the operation of ending the program is performed, the shutdown routine shown in FIG. 4C is executed. The CPU 13 updates the total read number Yi of each cluster in the non-volatile memory to the current value of the counter for each cluster, and holds the data (S6).

FIG. 7 is a block diagram showing the configuration of the fifth embodiment of the present invention. In particular, the memory cell array 1 and a plurality of clusters 102a-102c (one or a plurality of data blocks therein) are formed. In the embodiment, although three are provided for convenience of description, an arbitrary number is provided), the sense amplifier / latch circuit-equipped bit line control circuit 103, the ECC 11, the read number counter 13, and the error number comparator 101 are shown.

Of these, the memory cell array 1 includes, in addition to the plurality of clusters 102a to 102c, a temporary storage block 102d and a read count error number storage block 10.
2e. Further, the read number counter 13 has a plurality of counters R1 to R3 corresponding to the number of clusters 102a to 102c. When the addition operation is performed by a separate part (for example, the CPU 16 or the operation unit of the ECC 11), the counters R1 to R3 may be registers that hold the addition value. The error number comparator 101 also includes the cluster 102a.
A plurality of error comparators C1 ...
Have C3.

In this embodiment, the total number of readings Yi for each of the plurality of clusters up to now and the number of errors Ei generated at the time of the previous writing or erasing are associated with the cluster address i and the number of errors is increased. All clusters are stored in the number storage block 102e, and such data is read from the number-of-times error number storage block 102e. Further, the total number of readings Yi and the number of errors Ei of each cluster are stored in the plurality of clusters 102a to 102c, and the total number of readings Yi and the number of errors Ei of the cluster i are read from each cluster. You can

The total number of readings Yi and the number of errors Ei
Data is input to the read number counter 13 and the error number comparator 101 via the ECC 11, respectively. The total read number Yi that has been read is preset in the read number counters R1 to R3 corresponding to the read cluster i. The read error count Ei is set as the comparison reference value Eci in the error count comparators C1 to C3 corresponding to the read cluster i. It should be noted that a fixed value is stored in advance in the read count error number storage block 102e as the comparison reference value Ec, and this is stored in the error number comparator 1.
Can be set to 01. In this case, it is not necessary to provide the same number of error number comparators as the number of clusters, and only one is required.

The count value of each cluster of the read number counter 13 is written every time when reading is performed for each cluster, and the comparison reference value Ec of the error number comparator 101 is written,
Alternatively, it is updated each time the number of errors after erasure is checked. By doing so, whether or not a data error has occurred due to the read stress can be determined by comparing the number of errors Ei with the comparison reference value Eci. The total read number Yi becomes equal to the reference value Yc,
Further, when the number of errors Ei in the data in the i-th cluster exceeds the error allowable value Eci, the refresh operation is performed.

The target cluster is, for example, the cluster 10.
2b, the data in the cluster 102b is stored in the bit line control circuit 1 with a sense amplifier / latch circuit for each page.
03, and the error is corrected via the ECC 11. Further, the corrected data is stored in the cluster 10 for temporary storage.
One page is written in 2d. In this way, all the data in the cluster 102b is error-corrected and stored in the temporary storage cluster 102d. Then cluster 1
02b is erased, and the data in the temporary storage cluster 102d is copied to the cluster 102b. Furthermore, after that,
The temporary storage cluster 102d is deleted. Here, the temporary storage cluster 102d may be fixed as a dedicated block for refreshing, or an empty cluster may be used. However, in the latter case, it is necessary to change the block address as the data moves. Furthermore, the last temporary storage cluster 102d does not need to be erased immediately, but may be erased during the idle time of the CPU 16 to save time.

FIGS. 8 and 9 are flowcharts showing the refresh algorithm of the nonvolatile semiconductor memory device according to the above embodiment.

When the power of the apparatus is turned on or the execution of the initialization routine is instructed by the operating system, application program, etc., FIG.
The initialization routine shown in is executed.

For all clusters 1 to n of the non-volatile memory, the total number of read times Y from the last refresh to the present is Y.
i and the number of errors Ei generated when the previous writing or erasing was performed
Is read (S3). As described above, the total read count Yi and the error count Ei for the cluster i can be recorded in advance in the read count error count storage block 102e. Further, the total number of readings Yi and the number of errors Ei of each cluster can be stored in advance in the data blocks 102a to 102c for each cluster. The total read number Yi for each read cluster is preset in the counter for each cluster of the counter 13 that counts the total read number. The read error count Ei of each cluster is set as an error reference value Eci in the error count comparator corresponding to cluster i (S5). By setting the previous error count Ei as the current error reference value, it is possible to determine that the current error has increased compared to the previous time.

Thereafter, the read number monitor routine shown in FIG. 9 is executed. Every time data is read, the CPU 16 increments the total read count by 1 by the counter (S34) and determines whether the total read count Yi has reached the preset maximum read count Yc (S).
36). When the total read number Yi becomes equal to the reference value Yc, all the data of the i-th cluster is read (S3
8) The error is corrected by the ECC 11 (S4
0) and stored in the cluster for temporary storage (S42). The error count Ei of these data is compared with the allowable value Ec (S44). If the number of errors Ei exceeds the allowable value Ec, all blocks in the cluster are erased (S46), and the corrected data stored in the temporary storage cluster is copied to the i-th cluster (S48). . After that, the data in the temporary storage cluster is erased (S5).
0). The total read number Yi is rewritten to "0" and reset (S52).

On the other hand, if the number of errors does not exceed the allowable value (S44), the data is not erased and rewritten, and the total read number Yi is rewritten to "0" and reset (S52). .

After writing or erasing (S32), the written or erased data is read via the ECC 11 and the number of errors is checked (S62). The reference value of the error number set in the error number comparator 101 is updated (S64).

Such processing (S32 to S64) is repeated for clusters 1 to n. When an operation to turn off the power to the device or a command to end the program is issued,
The shutdown routine shown in (b) is executed. The CPU 16 determines the total number of readings Yi and the number of errors Ei for each cluster, which are stored in the nonvolatile memory, before the power is turned off, by using the data cluster 102.
a-102c or the read count error count storage block 102e, the total read count Yi is the current value of the counter 13, and the error count Ei is the value currently held as the comparand of the error count comparator. To each (S
7).

As described above, when the error count Ei is set as the error reference value Eci (S5), the error count Ei should not exceed the error correction capability of ECC (for example, 3 bits).

FIG. 10 is a block diagram showing a sixth embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and description of such parts will be omitted. Also,
FIG. 11 is a flowchart showing the refresh algorithm of this embodiment.

In this embodiment, by performing refreshing every time the power is turned on, the read number counter 13 becomes unnecessary, and the operation associated with this is rewritten in advance, for example, the total read number Yi before turning off the power ( You can eliminate operations such as saving. Further, by providing the parity checker 200 in the memory body 10, it is possible to confirm whether or not there is an error in the write data or the read data without outputting the data to the outside of the memory body. Furthermore, when data is rewritten, the presence or absence of an error is checked, and if an error occurs, the data rewrite destination is an empty cluster, so it is possible to reduce errors during rewriting as much as possible.

First, when the power is turned on, the program shown in FIG. 11 is automatically started. This can be realized by the functions of the IPL (Initial Program Loader) and the operating system. For example, data is sequentially read from the first-valued cluster in page units (S7
2) The parity checker 200 confirms whether or not there is an error in the read data (S74). When it is determined that an error has occurred (S76), the data reading is stopped. All the data in the cluster i to which the error data belongs are
The data is read out by the ECC 11 provided outside the memory body 10 and subjected to error correction, and then stored in the buffer memory 12 (S78). A plurality of memory bodies 10 can be provided as shown in FIG.

Thereafter, the data of all blocks in the cluster i is erased (S80), and the corrected data is transferred from the buffer memory 12 and rewritten (S8).
2). The rewrite data is read from the cluster i, and the parity checker 200 confirms whether or not there is an error in the read data (S84). If there is an error (S86), the address is changed to an empty cluster or a spare cluster of the memory body 10 (S88) and the data is written again (S82). Here, the data to be rewritten is obtained from the buffer memory 12. This operation is continued until it is confirmed that the rewritten data has no error (S82 to S86). If there is no space for rewriting in the memory, in S88, a code indicating a memory error is output to the CPU 16, and if necessary, the CPU 1
Let 6 handle interrupts and take countermeasures against errors. In this way, the CPU 16 can access the memory body 10 for the first time after refreshing all the memory data from the cluster 1 to the cluster n (S90 to S92).

The technique SA (steps S78 to S88) for writing data in a cluster different from the cluster in which the error check is performed, which is disclosed in this embodiment, stops the use of the faulty data block and causes a malfunction. This is an important technique of using a non-existent data block, and can be incorporated into the above-described embodiments, for example, the embodiments shown in FIGS. 4B, 6 and 9. In the above algorithm, the power is turned on, but this can be executed when a power-off command is received.

The embodiment shown in FIG. 12 shows an application example of the technique SA for changing the memory location to another location in the routine, and the total number of read times during the operation from power-on to power-off. When Yi becomes the setting reference Yc, the refresh operation is started. In addition, error detection is ECC
Instead of 11, the parity checker 200 of the memory body is used.

When the memory is accessed and read from the cluster i (S104), the total read number Yi for the cluster i is incremented by 1 by the read number counter 13 (S106). Total read count Yi
If the value does not exceed the reference value Yc, the routine exits. If the value exceeds the reference value Yc (S108), a parity check is performed on the data of the cluster i (S11).
0), it is determined whether an error has occurred (S11).
2). When an error occurs, the refresh operation is executed for the i-th cluster (S114). Here, like SA shown in FIG. 11, when a rewrite error occurs in the cluster i, writing is performed in another free cluster. When the rewriting is completed, in order to newly count the number of readings in response to the data refresh,
The read number counter 13 is reset (S116).

FIG. 13 shows another example of refreshing the nonvolatile semiconductor memory when the power is turned on or off. First, when the power-on or power-off is instructed, the program shown in FIG. 13 is automatically started. This can be realized by the functions of the IPL (Initial Program Loader) and the operating system. From the first cluster, for example, data is sequentially read in page units (S122), the presence or absence of an error in the data read by the ECC 11 is detected, and the error number Ei in the cluster i is counted by the error number counter of the ECC (S124). ). The number of errors Ei is the error reference number Ec
When it exceeds (S126), the cluster I is refreshed as in steps S20 and S22. Cluster i
All the data in E are stored in the outside of the memory body 10.
The data is read out to CC11, subjected to error correction, and then stored in the buffer memory 12. All data in cluster i is erased and error-corrected data is stored in buffer memory 1
From 2 onward, the cluster i is rewritten (S128). Note that it is possible to apply the technique of writing in a free cluster different from the cluster i shown in SA of FIG. 11 described above.

After step S128, or if the number of errors Ei is less than the reference (S126), it is determined whether the cluster is the final address (S130). If it is not the final address, address the next cluster (S
132), error detection, refresh (step S12)
4 to S128) is repeated.

In step S126, "Yi
= Yc? By appropriately inserting the read number counter reset as in step S116 of FIG. 12, it is possible to perform the refresh based on the read number as shown in FIG. 4B when the power is turned on or off. .

FIG. 14 shows still another example of refreshing the nonvolatile semiconductor memory when the power is turned on or off. First, when the power-on or power-off is instructed, the program shown in FIG. 14 is automatically started. This can be realized by the functions of the IPL (Initial Program Loader) and the operating system.

First, when the power is turned on, the total number of readings Yi from the previous refresh of all the clusters to the previous reading is automatically read and preset in the counter for counting the total number of readings. The first cluster is designated (S142), and the number of readings Y1 stored in the predetermined location is Y1.
Is compared with the reference value Yc (S14).
4). If it does not exceed, it is determined whether it is the final cluster (S156), and if it is not the final cluster, the next cluster is designated (S158).

When the number of readings Yi of the i-th cluster exceeds the reference value Yc (S148), all data of the cluster i is read and stored in the buffer memory 12 via the ECC 11 (S146). The error in these data is E
It is determined by CC11, and the error number Ei is counted by the error number counter in the ECC11. The error count Ei is compared with the allowable value Ec preset in the error count comparator 101 (S148). As described above, the allowable value Ec can be appropriately changed to a fixed value or the previous Ei or the like. If the number of errors Ei exceeds the allowable value Ec, all blocks in the i-th cluster are erased (S150), the error-corrected data is written again in the same cluster, and the data is refreshed ( S1
52). After that, the total read count Y for cluster i
i is rewritten to "0", and the read number counter is reset (S154). On the other hand, if the number of errors does not exceed the allowable value (S148), data erasing and rewriting (S150, S152) are not performed, and the total read number Yi is rewritten to 0 and reset (S154).

Such a routine (S144 to S15)
8) is repeated and executed, so that the cluster 1
The n write data are refreshed.

In this way, the error check of all the data in the non-volatile memory body is performed immediately after the power is turned on or immediately before the power is turned off, and all the data in the cluster in which the number of errors exceeds the allowable value is read and refreshed. It

Further refreshing routines can be formed by further combining the characteristic portions and elements in each of the above-described embodiments. The illustrated memory body 10 and EC
It is possible to form C11 to CPU16 on the same chip. For example, it can be formed as a one-chip microcomputer including a non-volatile memory.

Further, the memory body 10 and the ECCs 11 to CP
It is possible to form U16 on a separate chip and store them in one package by a multi-chip module. Of course, the memory body 10 and the ECC 11 to CPU 1
6 and 6 can be modularized on the wiring board.

Further, in the embodiment, the refresh subroutine such as the read count monitor routine is executed upon the turning on of the power source, but the present invention is not limited to this. For example, when a power-off command is received, a command from the operating system of the computer system, or a subroutine call (or function call) from an application program can be performed to appropriately refresh the nonvolatile memory. is there.

As described above, according to the embodiment of the present invention, the following effects can be obtained.

First, since the total number of readings up to the previous time can be counted even if the power is turned off, the correct data can be rewritten when the maximum number of readings is reached.

Secondly, since the correction data can be temporarily stored in the memory area dedicated to the temporary storage, the empty memory area, or the buffer memory in the non-volatile memory body, the original data can be erased and rewritten.

Thirdly, since the error count condition is added to the refresh operation by using the error count comparator, that is, whether the error count is greater than or equal to the set allowable value, the error count is smaller than the reference value. In this case, the refresh operation which is unnecessary in some cases can be prevented.

Fourth, by setting the maximum number of readings to be less than or equal to the expected value of the number of readings that makes a 1-bit error for the first time, even if errors due to read stress occur, the number of errors is less than the number of ECC correctable errors. You can refresh to the correct data in a while. As a result, the frequency of errors that exceed the error correction capability can be reduced to such an extent that it does not pose a problem in practical use.

Fifth, by storing the total number of readings and the number of errors in a dedicated cluster, it is possible to update these numbers with one access.

Sixth, by making the reference value of the number of errors equal to the number of errors that occurred during data rewriting, the number of errors can be divided into the number of errors due to reading and the number of errors due to rewriting, and thus reading You can refresh when an error occurs due to.

Seventh, by changing the cluster address to a free cluster until the number of errors becomes less than the allowable number at the time of refreshing, the cluster that has failed to be written can be erased in the free time, and the refresh condition is satisfied. Since the reference value for error count comparison can be fixed, it is not necessary to read or update the error count reference value.

Eighth, by always performing the refresh operation when the power is turned on or off, it is possible to eliminate the need to store the read number in the memory body.

[0092]

As described above, according to the present invention, in a rewritable non-volatile memory in which the held data has not been refreshed conventionally, an error occurs due to the state transition of the held data due to the threshold change of the memory cell transistor. Rewrite (refresh) before it occurs or restore the retained data to the correct data within the error-correctable error range, and then rewrite, so that the correct data is retained without being affected by the read count. A non-volatile semiconductor memory system that can continue is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a graph illustrating the relationship between the number of read times and the number of error bit occurrences.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 (a) is a flowchart illustrating an initialization routine in the embodiment. FIG. 4B is a flowchart explaining the refresh operation of the embodiment. FIG. 4C is a flowchart illustrating the shutdown routine in the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a flowchart illustrating a refresh operation of the embodiment.

FIG. 7 is a block diagram showing another embodiment of the present invention.

8 (a) is a flowchart explaining an initialization routine in the embodiment shown in FIG. 7. FIG. FIG.
(B) is a flow chart for explaining a shutdown routine in the embodiment shown in FIG. 7.

9 is a flowchart illustrating a refresh operation of the embodiment shown in FIG.

FIG. 10 is a block diagram showing another embodiment of the present invention.

FIG. 11 is a flowchart illustrating a refresh operation after power is turned on in the embodiment shown in FIG.

FIG. 12 is a flowchart illustrating a refresh operation based on the number of read times of the embodiment shown in FIG.

13 is a flowchart illustrating another refresh operation after the power is turned on in the embodiment shown in FIG.

FIG. 14 is a flowchart illustrating still another embodiment after power is turned on.

FIG. 15 is an explanatory diagram illustrating a configuration of a conventional nonvolatile semiconductor memory.

FIG. 16 is a cross-sectional view illustrating a configuration of a conventional nonvolatile semiconductor memory.

FIG. 17 is an explanatory diagram illustrating a memory cell array configuration of a conventional nonvolatile semiconductor memory.

[Explanation of symbols]

 1 memory cell array 2 word line drive circuit 3 row decoder 4 bit line control circuit 5 column decoder 6 address buffer 7 data input / output buffer 8 command input / output buffer 10 memory body 11 error detection and correction (ECC) circuit 12 buffer memory 13 read counter 14 data line 15 control line 16 CPU 17 address line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaki Tomoki, Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa 1 Stock company Toshiba Tamagawa factory

Claims (16)

[Claims] 1. An information storage section having one or a plurality of storage areas made up of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to detect read data. An error detection / correction circuit that corrects and outputs an error, a read number counter that counts the reading of data from the information storage unit, and a refresh control unit that rewrites the data held in the information storage unit. When the count value for reading the data exceeds a read reference value, the refresh control unit reads all the data belonging to the storage area including the read data that is the target of the count from the information storage unit and reads the read data. Is rewritten in the storage area via the error detection and correction circuit. A storage system including a non-volatile semiconductor storage unit. 2. An information storage section having one or a plurality of storage areas made up of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to detect read data. An error detection / correction circuit that corrects and outputs an error, an error number counter that counts errors in detected data, and a refresh control unit that rewrites data held in the information storage unit, the refresh When the count value of the error of the data exceeds the error reference value, the control means reads all the data belonging to the storage area including the read data which is the object of the error correction from the information storage unit, and reads the read data. A storage system including a non-volatile semiconductor storage unit, which is rewritten to the storage area via an error detection / correction circuit. 3. An information storage section having one or a plurality of storage areas each composed of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to read out the read data. An error detection / correction circuit that corrects and outputs an error, an error number counter that counts an error in detected data, a read number counter that counts the reading of data from the information storage unit, and the information storage unit holds Refresh control means for rewriting data, wherein the refresh control means, when the read count value of the data exceeds a read reference value and the error count value of the data exceeds an error reference value, All the data belonging to the storage area including the read data that is the object of each count is read from the information storage unit, and the read data is read by the error detection and correction circuit. Storage system including a nonvolatile semiconductor memory unit that writes again written in the storage area via, characterized in that the. 4. An information storage section having one or a plurality of storage areas each composed of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to read the read data. An error detection / correction circuit that corrects and outputs an error, a read number counter that counts the reading of data from the information storage unit, a buffer memory that temporarily stores data, and a rewrite of data that the information storage unit holds. Refresh control means for performing, when the read count value of the data exceeds a read reference value, the refresh control means changes from the information storage section to a storage area including the read data to be counted. Reading all data belonging to the buffer memory, and writing the read data to the storage area again via the error detection and correction circuit; Storage system including a nonvolatile semiconductor memory unit according to claim. 5. An information storage section having one or a plurality of storage areas made up of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to detect read data. An error detection / correction circuit that corrects and outputs an error, an error number counter that counts errors in detected data, a buffer memory that temporarily stores data, and a refresh that rewrites data held in the information storage unit. Control means, the refresh control means, when the count value of the error of the data exceeds an error reference value, the refresh control means belongs to the storage area including the read data which is the error correction target from the information storage unit. Reading the data into the buffer memory and rewriting the read data into the storage area via the error detection and correction circuit. Storage system including a nonvolatile semiconductor memory unit to symptoms. 6. An information storage section having one or a plurality of storage areas each composed of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to detect the read data. An error detection / correction circuit for correcting and outputting an error, an error number counter for counting errors in detected data, a read number counter for counting data read from the information storage unit, and a buffer for temporarily storing data A memory and refresh control means for rewriting the data held in the information storage section are provided, wherein the refresh control means counts an error in the data when the count value for reading the data exceeds a read reference value. When the numerical value exceeds the error reference value, all the data belonging to the storage area including the read data targeted for each counting from the information storage unit Storage system including reading Ffamemori, writes again written in the storage area via the error detecting and correcting circuit to read data, a nonvolatile semiconductor memory unit, characterized in that. 7. An information storage section having one or a plurality of storage areas each composed of a non-volatile memory cell group in which data can be rewritten, a read number counter for counting the reading of data from the information storage section, and data. A buffer memory for temporarily storing, and a refresh control unit for rewriting data held by the information storage unit, wherein the refresh control unit, when the count value for reading the data exceeds a read reference value, All the data belonging to the storage area including the read data that has been the object of counting from the information storage unit is read into the buffer memory, and the read data is stored in the storage area in which all the data is read or another storage area other than this storage area. A storage system including a non-volatile semiconductor storage unit, which is characterized by rewriting to a storage area. 8. An information storage section having one or a plurality of storage areas each composed of a non-volatile memory cell group in which data can be rewritten, and an error of data read from the information storage section is detected to detect the read data. An error detection / correction circuit that corrects and outputs an error, and a refresh control unit that rewrites data held in the information storage unit are provided, and the refresh control unit turns on or off the power to the storage system. At this time, all the data is read from the storage area, and the read data is rewritten to the storage area via the error detection and correction circuit. A storage system including a nonvolatile semiconductor storage unit. 9. The refresh control means rewrites the data held in the information storage unit when the storage system is powered on or off. A storage system including the nonvolatile semiconductor storage unit according to claim 1. 10. The refresh control means reads all data belonging to a storage area including read data which is a target of each count from the information storage portion, and reads the read data through the error detection and correction circuit. 7. The data is written in a storage area specified for refreshing or a free storage area, which is another storage area other than the storage area from which all the data has been read out. Item 10. A storage system including the nonvolatile semiconductor memory unit according to any one of items 8 and 9. 11. The refresh counter is provided for each one or a predetermined number of storage areas consisting of the memory cell group so as to correspond to a division of the storage area, and one or a predetermined number of the read counters are provided. The control means sets all data belonging to a storage area divided into one of the storage areas or a predetermined number of storage areas as a data rewriting unit. 9. The nonvolatile semiconductor memory device according to any one of 9 and 9. 12. A comparator for comparing an output of the error number counter with an error reference value is adapted to correspond to a section of the storage area for each one or a predetermined number of storage areas consisting of the memory cell group. One or a predetermined number of the storage areas are provided, and the refresh control unit sets all data belonging to each of the storage areas or a predetermined number of storage areas as a unit for rewriting data. The non-volatile semiconductor memory device according to claim 2, 3, 5, or 6. 13. The refresh control means sets an error count value of previous data as a reference for error comparison of this time when starting a control program for monitoring a timing of rewriting data held in the information storage section. 13. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is set as a value. 14. Each count value of the read number counter or the error number counter is prepared in a storage area for holding the data to be counted in the information storage section or for holding the count value. A storage system including the nonvolatile semiconductor storage unit according to claim 11 or 12, wherein the storage system is stored in a storage area. 15. The refresh control means re-detects an error in read data in a storage area in which data has been rewritten, and when an error is detected again in this storage area, all data in this storage area is re-detected. The storage system including the non-volatile semiconductor storage unit according to claim 10, wherein the storage system is moved to another storage area. 16. The read reference value is determined based on a distribution characteristic of the number of read times versus the number of error bits of the non-volatile memory cell group, according to claim 1, 3, 4, 6, and 7. A storage system including the nonvolatile semiconductor storage unit according to any one of claims.