JP3482543B2 - Semiconductor memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a semiconductor memory, and is a technique applicable to, for example, a flash memory, an IC card, an expansion memory of a notebook personal computer and the like.

[0002]

2. Description of the Related Art Semiconductor memories are extremely reliable. Therefore, conventionally, a memory having a parity bit has been proposed, but a memory having the memory itself to check data has not been proposed. On the other hand, a magnetic disk is less reliable than a semiconductor memory, and therefore there is a magnetic disk provided with a so-called ECC (error collecting code) circuit for checking and correcting data.

The ECC circuit detects and corrects data when the stored data is destroyed. The logic is "Memory application from the basics" issued by CQ Publishing Co., Ltd.
It can be represented by a combination of exclusive ORs, as is widely known.

[0004]

Certain semiconductor memories have the drawback that the reliability of data decreases depending on the environment and the situation of use. As an example of such a semiconductor memory, for example, an excessively written non-volatile memory or a structure vulnerable to soft error, that is, used in a place with excessively strong radiation, at high temperature, or at a low voltage lower than the product's ability is used. There are DRAMs, SRAMs used at low temperature (0 ° C. or lower) or low voltage lower than the product's ability, and the like.

An object of the present invention is to provide a semiconductor memory in which retained data is highly reliable. Another object of the present invention is to provide a technique capable of realizing a non-volatile memory with high reliability of held data without complicating the manufacturing process. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the semiconductor memory is provided with an ECC circuit having an error check and correction function. In addition, in the case of a non-volatile memory, a spare bit is provided in the memory array section and a redundant circuit having a defective address storage means is provided in the peripheral circuit in preparation for the occurrence of an unwritable address, and the defective address is held. The means is configured using the same element as the non-volatile storage element in the memory array.

[0007]

According to the above-mentioned means, the correct data can be recovered by the ECC circuit even if some data in the memory array is destroyed, so that the reliability of the memory can be improved. In addition, in the non-volatile memory, a spare bit is provided in the memory array section and a redundant circuit is provided in the peripheral circuit, and the defective address storage means uses the same element as the non-volatile storage element in the memory array. By configuring, it is possible to replace a defective bit due to an increase in the number of rewrites with a spare bit, and to retain the defective address even after the power is turned off. It becomes possible to realize a nonvolatile memory with high data reliability.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall circuit block diagram of an embodiment in which the present invention is applied to a flash memory. The flash memory of this embodiment is formed as a semiconductor integrated circuit on a single semiconductor chip.

In the figure, 11 is a memory mat composed of insulated gate field effect transistors having a two-layer gate structure arranged in a matrix, for example, eight memory mats M capable of batch erasing in units of 512 bytes.
It is a memory array unit composed of AT0 to MAT7.
1-byte data and 1-bit error correction bit (described later) can be simultaneously written in and read from each memory mat.

Further, 12 is an address terminal Add from the outside.
Address buffer & latch circuit for fetching and holding the address signals A0 to Ai given to the address buffers, 13a and 13b are Y and X decoders for decoding the address signal fetched to the address buffer & latch circuit 12, and 13c is fetched. A mat selector that selects one of the eight memory mats in the memory array 11 based on the address signal, and a Y gate (column switch row) 14 provided on a data line in the memory array 11.

Reference numerals 15 and 16 denote sense amplifiers and control buffer circuits for write data, which are connected to the selected data line in the memory array section 11 by the Y gate 14. Reference numerals 17a and 17b denote data input / output terminals I.
A data output buffer and a data input buffer connected to / O, a latch circuit 18 for fetching and holding a chip selection signal CE, an output timing control signal OE and a write control signal WE as control signals input from the outside, 19 The buffer circuit 17b and the latch circuit 1
8 is a control circuit that forms an internal control signal and a write control signal based on the control signal and the write data that are taken in.

Although not particularly limited, the flash memory of this embodiment has eight data input / output terminals I / O,
8-bit parallel input / output is possible. Also,
Writing is 8 bits (1 byte) for each memory mat.
All mats are simultaneously written, that is, 64 bits (8 bytes) are simultaneously written. The reading is configured so that a mat can be selected and can be read in 1-byte units.

Further, 21 is a voltage detection circuit for detecting the level of the voltage applied to the power supply voltage terminal Vcc and the write voltage terminal Vpp, and 22 is the memory array section 11 based on the write voltage applied to the voltage terminal Vpp. Voltage generation circuit for generating write / erase voltage required in
Reference numeral 3 denotes a driver circuit for forming a word line selected through the X decoder circuit 12a and a driving signal by the write / erase voltage formed by the voltage generating circuit 22.

Although not particularly limited, the flash memory of this embodiment adopts a command system, and is provided with a command decoder 24 for decoding a command supplied from an external microcomputer to the data input / output terminal I / O. The writing and erasing of data are performed by inputting a command.

When the erase command is input, the command decoder 24 collectively erases the memory cells in block units such as 512 bytes, and when the write command is input, the command decoder 24 fetches the data in 1-byte units. A control signal is applied to each of the control circuits 19 so that 11 bytes are simultaneously written. Further, when the erase command and the write command are input, the internal state and the operation result are reflected in the status register 25. Moreover, the status register 25 is connected to the data input / output terminal I / O so that the external microcomputer can read the contents.

In this embodiment, the data input / output terminal I
An ECC circuit 31 is provided which forms an error correction bit of write data input from / O, checks whether the data read from the memory array 11 is correct, and corrects it when it is incorrect. . E when writing data
The error correction bit formed by the CC circuit 31 is written in the memory array 11 together with the write data, and at the time of data reading, the data is checked and corrected based on the data and the error correction bit read from the memory array 11, The correct data is output to the data input / output terminal I / O. When the ECC circuit 31 detects and corrects the error bit, the error detection signal ED is formed and output from the terminal 34 to the outside.

Further, in this embodiment, the memory array 1
A spare memory column 32 is provided adjacent to 1, and when a defective bit is found in the memory array 11, defective address storage means for storing an address corresponding to the memory column including the defective bit. A redundant circuit 33 including an address switching means for forming a signal for selecting the spare memory column 32 in place of the memory column in the memory array 11 when the defective address is inputted is provided.

Although not particularly limited, in this embodiment, the defective address storage means is composed of the same FAMOS (floating avalanche MOSFET) as the elements forming the memory cells in the memory array 11. As a result, a flash memory having a redundant circuit can be realized without complicating the manufacturing process, and a large increase in cost can be avoided.

Next, the ECC circuit 31 will be specifically described. In the flash memory of this embodiment,
As an example, an ECC circuit for performing 1-bit error correction / 2-bit error detection of 8-bit data is provided.
When 64 bits (8 bytes) are simultaneously written as in this embodiment, 4-bit operation data (error correction bit) is required. Therefore, as the configuration of the memory array unit 11, for example, 32 Mbits are prepared as a user use area, 4 Mbits are prepared for accommodating the ECC operation result, and 8 mats are configured to read and write 9-bit data for each mat. To configure.

Further, although not particularly limited, the flash memory of this embodiment is provided with the command E from the outside by a command.
It is configured so that it can be instructed whether or not to operate the CC circuit 31, and the ECC circuit 31 functions only when an external request is made at the time of data writing and reading. If there is a request, the write data will be written to the memory array unit 1
Before being written to 1, it is input to the ECC circuit 31, an error correction bit is formed and written together with the data (write data is 8 bytes and the ECC operation result is 1 byte). Although the number of data input / output terminals I / O is eight, the number of data signal lines inside the LSI is nine.

On the other hand, when the block reading is designated by the command input from the microcomputer, the flash memory reads the data of one block at the same time or with some time difference and inputs it to the ECC circuit 31. At this time, if there is an error, it is corrected, and the signal E indicating the correction is made.
D is output from the terminal 34 to the outside, and information indicating data having an error bit is written to the status register 25 (which data among 8 data (64 bits + 8 bits) has an error). 8 I / O terminals are enough to output or).

Therefore, the microcomputer can easily know that the error has been corrected by the signal ED. Then, the address of the defective bit can be known by reading the contents of the status register 25 inside the flash memory with a command. Instead of providing the terminal 34 for outputting the signal ED indicating the error correction to the outside, a bit indicating the error correction may be provided in the status register 25.

The ECC circuit 31 can be operated only when the power is turned on. As a result, it is possible to prevent access delay due to the use of the ECC circuit during normal access, and to ensure high speed of the system.

Next, the redundant circuit 33 will be described. The configuration and operation of the redundant circuit 33 of this embodiment are almost the same as those of a generally known redundant circuit. The characteristic of this circuit is that a nonvolatile memory element is used instead of or in combination with a fuse that constitutes defective address storage means, and a control system circuit for writing data is provided in the nonvolatile memory element (see FIG. 1). (Provided in the control circuit 19 of the above).

However, the operation of writing data in the nonvolatile memory element forming the defective address storage means is no different from the operation of writing data in the memory array section 11. The write operation is performed by selecting a redundant set mode (defective address setting mode) by a command and designating a memory element to be written by using an address pin.

2 to 5 show examples of the configuration of defective address storage means. In the figure, the symbol M is a nonvolatile memory element (FAMOS). In the defective address storage means of FIG. 2, when the nonvolatile memory element M1 is written (charge injection) and its threshold voltage is raised, the output signal Rout is fixed at a high level, and when the writing is not performed, the output signal Rout is output. Is fixed at a low level. The MOSFET Q1 connected in series with the nonvolatile memory element M1 is turned off only when writing to M1. A write boosted voltage Vppw higher than the normal power supply voltage Vcc is supplied to the terminal V when writing to the nonvolatile memory element M1.

The defective address storage means of FIG. 3 uses a nonvolatile memory element M1 and a fuse F1 in combination.
When a defective address is found and repaired (defective address setting) before the chip is encapsulated in a package, the fuse F1 is cut to fix the output signal Rout to a high level, and the fuse F1 is left uncut. That is, the output signal Rout is fixed at a low level. Note that the nonvolatile memory element M1 is written in advance.

On the other hand, when the defective address is found after the chip is encapsulated in the package and the relief is performed (the fuse is not cut at this time), the non-volatile memory element M1 is erased (the charge is extracted). The output signal Rout is fixed at a high level when the threshold voltage is lowered by the threshold voltage, and the output signal Rout is fixed at a low level when erasing is not performed. The MOSFET Q1 connected in series with the nonvolatile memory element M1 is turned off only when writing and erasing M1. Terminal V
Is supplied with a write boost voltage Vppw higher than the normal power supply voltage Vcc when writing to the non-volatile memory element M1, and a negative voltage when erasing.

In the defective address storage means of FIG. 4, the output signal Rout is fixed at a low level by writing (injecting charge) into the nonvolatile memory element M1 and leaving M2 in an erased state, and M1 is placed in an erased state. The output signal Rout is fixed at a high level by writing to. The MOSFET Q1 connected to the connection node between the non-volatile memory elements M1 and M2 is turned on only when the relief address data is latched when the power is turned on. A write boosted voltage Vppw higher than the normal power supply voltage Vcc is supplied to the terminal V when writing to the nonvolatile memory element M1.

The defective address storage means of FIG. 5 is such that the nonvolatile memory element M1 and the fuse F1 are used together to determine the output level by resistance division of the fuse and the memory element. When a defective address is found and repaired (defective address setting) before the chip is sealed in the package, the fuse F1 is cut to output the output signal Rout.
Is fixed to the high level, and the output signal Rout is fixed to the low level if the fuse F1 is left uncut. Note that the nonvolatile memory element M1 is written in advance.

On the other hand, when the defective address is found after the chip is encapsulated in the package and the relief is performed (the fuse is not cut at this time), the non-volatile memory element M1 is erased (the charge is extracted). The output signal Rout is fixed at a high level when the threshold voltage is lowered by the threshold voltage, and the output signal Rout is fixed at a low level when erasing is not performed. The MOS connected to the connection node between the nonvolatile memory element M1 and the fuse F1
The FET Q1 is turned on only when the relief address data is latched when the power is turned on. Further, Vcc is supplied to the terminal Vc1 when Q1 is on, and Vss is supplied when Q1 is on.

Next, a redundancy setting method for replacing a defective bit with a spare bit when the defective bit occurs in the memory array due to an increase in the number of times of rewriting will be described.

In the flash memory of this embodiment, when the ECC circuit 31 detects a data error, an error detection signal ED is output from the terminal 34, and information indicating which data has an error is stored in the status register 25.
Stored in. Therefore, when the microcomputer knows that an error has occurred, it reads the contents of the status register 25 and stores the address of the data including the error bit. For example, if the same address causes an error a plurality of times in succession. If determined, the address is recognized as a defective address, and the defective address setting command and the defective address are given to the flash memory.

Flash memory command decoder 24
When the defective address setting command is received, the control circuit 19
To the internal redundant circuit 33 to set a defective address. Then, after setting the defective address, the data at the original address position is written in the spare bit replaced with the defective bit. After that, read the written data and check it, and if it is correct, shift to the normal operation mode,
If wrong, the fact that there is an error is written in the write / erase error bit of the status register 25. By doing so, the defective bit can be automatically relieved without removing the flash memory from the system board.

The function of detecting the defective address and setting the defective address in the redundancy circuit 33 is provided in the control circuit 1 provided in the flash memory instead of the microcomputer.
It is also possible to configure the memory so that it is carried out by 9.

In the above embodiment, the redundant circuit 33 is provided in the flash memory to repair the defective bit. However, instead of providing the spare memory 32 and the redundant circuit 33, the microcomputer generates the defective bit. If it is determined that the defective address has been confirmed, the defective address can be detected and stored by referring to the status register 25, and then the defective address can be prevented from being accessed. Further, instead of holding in the status register 25 the information indicating which erroneous data is, the address terminal Add may be used to output the information to the outside.

As described above, in the above embodiment, the semiconductor memory is provided with the ECC circuit having the error check and correction function. Therefore, even if a part of the data in the memory array is destroyed, the ECC circuit corrects the data. Since it is possible to recover the memory, it is possible to improve the reliability of the memory.

Moreover, the ECC circuit detects an error,
Since the terminal for outputting the error detection signal when the correction is made is provided, the microcomputer can know that the defective bit has occurred in the memory array section and prevent the address of the defective bit from being used. By (moving the data including the defective bit to another address), the reliability of the system can be improved and the memory replacement time can be known.

Further, in the nonvolatile memory of the above embodiment, the spare bits are provided in the memory array portion and the redundant circuit is provided in the peripheral circuit, and the defective address storage means is provided in the nonvolatile storage element in the memory array. Since it is configured by using the same element as the above, it is possible to replace a defective bit due to an increase in the number of times of rewriting with a spare bit and to retain a defective address even after the power is turned off. There is an effect that it becomes possible to realize a nonvolatile memory with high reliability of held data without complicating the process. Moreover, there is an advantage that the usable storage capacity does not decrease for the user.

Further, since it is configured such that the ECC circuit is used or not and the address is set in the defective address storage means by a command,
There is an effect that the function can be improved while avoiding an increase in the number of pins.

Although the method of using the present invention has been described above, it goes without saying that the present invention can be used to simplify a small scale system. In addition, as a system application, all the circuits and the like shown in the present invention may be placed outside the LSI and assembled as a module or a wafer scale.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, although the 64-bit ECC circuit has been mainly described in the above embodiments, it goes without saying that the present proposal can be similarly applied to an ECC circuit other than 64-bit. Further, in the embodiment, the command is used to specify whether to use the ECC circuit. However, instead of the command, it is specified whether to use the ECC circuit with an external control signal. It can also be configured to do so.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory which is the field of application which is the background of the invention has been described. However, the present invention is not limited to this, and an EPROM or an EEP.
Non-volatile memory such as ROM, structure that is vulnerable to soft errors, that is, used in places with excessive radiation or high temperatures,
DRAM used at low voltage lower than product capability, low temperature (0
S) to be used at low voltage below the
It can also be used for RAM and the like.

[0044]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to realize a semiconductor memory with highly reliable retained data. Further, it is possible to realize a nonvolatile memory with high reliability of held data without complicating the manufacturing process.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a flash memory to which the present invention is applied,

FIG. 2 is a circuit diagram showing an embodiment of an address setting means of a redundant circuit,

FIG. 3 is a circuit diagram showing a second embodiment of the address setting means of the redundant circuit,

FIG. 4 is a circuit diagram showing a third embodiment of the address setting means of the redundant circuit,

FIG. 5 is a circuit diagram showing a fourth embodiment of the address setting means of the redundant circuit.

[Explanation of symbols]

11 Memory array section 12 Address buffer & latch circuit 13a Y decoder 13b X decoder 14 Y gates (column switch row) 15 sense amplifier 16 Write data latch circuit 17a data output buffer 17b Data input buffer 19 Control signal forming circuit 31 ECC circuit 33 redundant circuit

Continuation of front page (56) Reference JP-A-4-167300 (JP, A) JP-A-4-157700 (JP, A) JP-A-61-217999 (JP, A) JP-A-3-162798 (JP , A) JP-A-6-139154 (JP, A) JP-A-6-111589 (JP, A) Actual development 5-4266 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G11C 29/00 G11C 16/00-16/34

Claims (6)

(57) [Claims] 1. A memory array section having a plurality of non-volatile memory elements, and an error correction code is formed based on input write data, written in the memory array section together with the write data, and read from the memory array section. EC for checking data with error correction code and correcting errors
A semiconductor memory having a C circuit, wherein the semiconductor memory selects a defective address setting mode when a data error is detected by the ECC circuit under a predetermined condition when mounted on a system board. By doing so, the address in which the error of the data is detected is stored as a defective address in the nonvolatile memory element, and the nonvolatile memory element corresponding to the defective address cannot be accessed in the normal operation mode. Characteristic semiconductor memory. 2. The semiconductor memory according to claim 1, further comprising a terminal for outputting a signal indicating that an error has been corrected. 3. The semiconductor memory according to claim 1, further comprising a register for storing an address of data including a bit in which an error has been corrected. 4. A spare memory element, a defective address storing means for storing the defective address, and a nonvolatile memory element in the memory array section when the same address as the address set in the defective address storing means is inputted. , A redundant circuit including an address switching means for forming a signal for selecting the spare memory element, and the defective address storage means has a non-volatile memory element, and an arbitrary address is provided by writing to the non-volatile memory element. The semiconductor memory according to claim 1, 2 or 3, wherein an address can be set. 5. The apparatus according to claim 1, further comprising a function for decoding a command given from the outside, wherein the command is used to specify whether or not to operate the ECC circuit. 2. The semiconductor memory described in 2, 3, or 4. Further comprising: a function to decrypt the given from external command, the command of claim 4, characterized in that it is configured to set the address to the defective address storage means is performed Semiconductor memory.