JP2017097909A - Control device and control method of semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control device and a control method of a semiconductor memory, capable of suppressing deterioration in reliability of read data.SOLUTION: A storage device 2 has: a failure detection correction determination unit that detects whether a failure occurs in a read data piece read from a memory cell group, and when a failure occurs determines whether it is correctable; a reading control unit which, when the failure detection correction determination unit determines that no failure occurs in the read data piece or does therein but it is correctable, repeatedly reads the read data piece from the memory cell group only at an invalid determination frequency; and a determination unit which, when at least one of the read data pieces repeatedly read only at the invalid determination frequency by the reading control unit is determined to be uncorrectable by the failure detection correction determination unit, determines that the read data piece is invalid data to be subjected to refresh processing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor memory control device, and more particularly, to a semiconductor memory control device that performs error detection on read data and a control method thereof.

  Currently, NAND flash memories are widely used as nonvolatile semiconductor memories.

  By the way, in the NAND flash memory, if the power is cut off while data is being written to the memory cell, there is a possibility that the data of the memory cell to be written is destroyed. Therefore, when writing data with an error correction code added is written and an error is detected at the time of reading, it is determined that a power interruption has occurred during data writing, and the read data is not yet read. There has been proposed a writing determination method managed as usage data (see Patent Document 1).

  However, when power is cut off during data writing, depending on the power cut-off timing or element characteristics, the remaining state of the charge in the memory cell is halfway, that is, near the threshold value for determining the logic levels 1 and 0. There was a case. Therefore, when data is read from the memory cell, an unstable state in which normal data is read and illegal data is read is mixed, and the entire system using the NAND flash memory is in an unstable state. There was a problem that reliability was lowered.

JP2007-241618A

  It is an object of the present invention to provide a semiconductor memory control device and control method capable of suppressing a decrease in reliability of read data.

  A semiconductor memory control device according to the present invention is a semiconductor memory control device that performs data writing and reading in units of a memory cell group including a plurality of memory cells, and is a read data piece read from the memory cell group. And an error detection / correction determination unit for determining whether or not the error can be corrected when the error occurs, and the error detection / correction determination unit A read control unit that repeatedly reads out the read data piece from the memory cell group as many times as the invalidity determination number when it is determined that no error has occurred or an error has occurred but is correctable; and the read control unit Therefore, at least one of the read data pieces read repeatedly by the number of invalidity determinations cannot be corrected by the error detection / correction determination unit. If it is determined has, a determination unit to be invalid data the read data pieces are subject to refresh operation.

  The semiconductor memory control method according to the present invention is a semiconductor memory control method for performing data writing and reading in units of a memory cell group composed of a plurality of memory cells, wherein the read out from the memory cell group is performed. It is detected whether or not an error has occurred in the data piece, and if there is an error, it is determined whether or not the error can be corrected, and no error has occurred in the read data piece or an error has occurred. However, if it is determined that correction is possible, the read data piece is repeatedly read from the memory cell group as many times as the invalidity determination number, and at least one of the read data pieces read cannot be corrected. If it is determined that the read data piece is present, it is determined that the read data piece is invalid data to be refreshed.

1 is a block diagram showing an information processing system including a semiconductor memory control device according to the present invention. 5 is a diagram illustrating an example of the contents stored in a register 244. FIG. It is a flowchart which shows a refresh control routine. It is a figure which shows the operation | movement of a refresh process. It is a figure which shows another example of operation | movement of a refresh process. It is a block diagram which shows the information processing system containing the semiconductor memory control apparatus by the other Example in this invention. It is a flowchart which shows the reading determination control routine.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an information processing system including a storage device including a semiconductor memory control device according to the present invention. As illustrated in FIG. 1, the information processing system includes a host information processing device 1 and a storage device 2.

  The host information processing apparatus 1 performs various kinds of information processing based on data (to be described later) stored in the storage device 2 or externally supplied data, and writes a write command and a write destination to be written. The memory device 2 is supplied with an address and data for writing, or a read command for urging data to be read and a read source address.

  The storage device 2 includes a host interface (hereinafter referred to as host IF) unit 21, a memory access bus 22, a CPU (Central Processing Unit) 23, a memory control unit 24, and a NAND flash memory 25.

  The host IF unit 21 receives a write command, a read command, an address, and write data supplied from the host information processing apparatus 1 and supplies them to the CPU 23 via the memory access bus 22. In addition, the host IF unit 21 receives read data RDD (described later) sent from the memory control unit 24 via the memory access bus 22 and supplies it to the host information processing apparatus 1. The CPU 23 generates a memory write control signal for writing the write data at this address in accordance with the write command, address and write data supplied via the memory access bus 22, The data is supplied to the memory control unit 24 via the access bus 22. Further, the CPU 23 generates a memory read control signal for reading data from the address in accordance with the read command and the address supplied via the memory access bus 22, and generates the memory read control signal via the memory access bus 22. This is supplied to the memory control unit 24.

  The memory control unit 24 includes modules such as an error correction coding unit 240, an error detection correction unit 241, a 0 error counter 242, a 1 error counter 243, a register 244, and a determination unit 245.

  In response to the memory write control signal described above, the error correction coding unit 240 adds an error correction code such as a BCH code to the write data indicated by the memory write control signal to generate an error. Write-encoded write data WD is generated and stored in register 244.

  The error detection / correction unit 241 performs error detection processing on the read data RD read from the flash memory 25. Here, when an error bit is detected in the bit sequence of the read data RD, the error detection / correction unit 241 detects the logic level of the error bit.

  At this time, the error detection / correction unit 241 selects a logical level 0 error bit from the bit sequence of the read data RD, that is, a bit that is originally in a logical level 1 but is in an erroneous state at a logical level 0, Each time a bit in which a so-called “0 error” occurs is detected, a 0 error detection pulse is generated and supplied to the 0 error counter 242. Further, the error detection / correction unit 241 has a logic level 1 error bit from the bit sequence of the read data RD, that is, a bit that is supposed to be at the logic level 0 but is in an erroneous state at the logic level 1, so-called. Each time a bit in which “1 error” occurs is detected, a 1 error detection pulse is generated and supplied to the 1 error counter 243. Then, when there is an error in the read data RD but the error can be corrected, the error detection / correction unit 241 performs error correction processing on the read data RD, and the error-corrected data Is stored in the register 244 as read data RDD as shown in FIG. If there is no error in the read data RD read from the flash memory 25, the error detection / correction unit 241 stores the read data RD in the register 244 as the read data RDD. That is, only valid data among the read data RD is stored in the register 244 as the read data RDD.

  The zero error counter 242 counts the number of the zero error detection pulses supplied and stores the count value in the register 244 as the zero error occurrence number EG0. That is, 0 error counter 242 counts the number of bits in which “0 error” has occurred in the bit sequence of read data RD, and stores 0 error occurrence number EG 0 indicating the number of “0 error” in register 244. It is.

  The 1 error counter 243 counts the number of the above-described 1 error detection pulses supplied, and stores the count value in the register 244 as the 1 error occurrence number EG1. That is, the 1 error counter 243 counts the number of bits in which “1 error” has occurred in the bit sequence of the read data RD, and stores the 1 error occurrence number EG 1 indicating the number of “1 error” in the register 244. It is.

The memory control unit 24 reflects the operation of these modules, and accesses (data write, read, erase) to the flash memory 25 according to the memory write control signal or the memory read control signal, for example, 4 kilobytes or 8 This is done in units of pages consisting of memory cells for kilobytes or in units of blocks consisting of 64 pages. That is, in response to the memory write control signal, the memory control unit 24 first performs data erasure in which the state of all the memory cells in the block including the page to be written is set to the logic level 1 state. Do. Next, the memory control unit 24 supplies the flash memory 25 with the write data WD stored in the register 244 and the address specified by the memory write control signal and a write command signal for urging data writing. To do. Thereby, when the write data WD indicates the logical level 0, the flash memory 25 changes the memory cell in the page designated by the address from the logical level 1 state (data erased state) to the logical level 0 state. Write driving (for example, charge injection or charge discharge) to be shifted to is performed. On the other hand, when the write data WD indicates the logic level 1, that is, the same logic level as the data erase state, the memory cell is not accessed. With this operation, the flash memory 25 writes the write data WD at a specified address. Further, the memory control unit 24 generates the write order management information TM indicating the page in which the write data WD is written and the information indicating the write date and time or the write order in all pages. This is stored in the register 244 as shown in FIG.

  Further, when a memory read control signal is supplied via the memory access bus 22, the memory control unit 24 reads the data while supplying the address specified by the memory read control signal to the flash memory 25. A read command signal for prompting is supplied to the flash memory 25. As a result, the flash memory 25 reads the write data WD stored at the designated address and supplies it to the memory control unit 24 as the read data RD. The bit length of each of the write data WD and the read data RD is a unit block length as an error correction code, a bit length for one page as a NAND flash memory, or the like.

  Thereafter, when the error detection and correction processing in the error detection and correction unit 241 and the count operation in the 0 error counter 242 and the 1 error counter 243 are completed for one read data RD, the determination unit 245 stores the data in the register 244. It is determined whether or not the stored 1 error occurrence number EG1 is larger than the 0 error occurrence number EG0. At this time, if it is determined that the number of occurrences of 1 error EG1 is greater than the number of occurrences of 0 errors EG0, the determination unit 245 determines that the read data RD is invalid data that has been destroyed by power-off during writing. Judge that there is.

  After the above operation is completed, the memory control unit 24 sends the read data RDD as valid data stored in the register 244 to the host IF unit 21 via the memory access bus 22. As a result, the read data read from the flash memory 25 is sent to the host information processing apparatus 1. On the other hand, the memory control unit 24 does not transmit the read data RD determined to be invalid data to the host information processing apparatus 1. Note that the memory control unit 24 performs a refresh process as described later on the page or block in which the read data RD determined to be invalid data is stored.

  As described above, when writing data to the flash memory 25, the memory control 24 sets the memory cells in the flash memory 25 to the logic level 1 state (when the write data WD is at the logic level 0). A write drive (for example, charge injection or charge discharge) to be changed from a data erasure state to a logic level 0 state is performed. However, if the power supply is interrupted during the above-described write drive, charge injection or charge into the memory cell before the state of the memory cell transitions from the logic level 1 state (data erase state) to the logic level 0 state. The discharge operation is interrupted. Therefore, the memory cell cannot be completely written to the logic level 0 state where the writing should be performed in the logic level 0 state. At this time, when data is read from the memory cell, an unstable state in which the logic level 0 is correctly read and the logic level 1 is erroneously read is mixed. Therefore, when there is an error in the data read from the memory cell, the so-called “1 error” is to be read in an erroneous state of logic level 1 where it should originally be logic level 0. "Is likely to occur.

  Therefore, when data written in a situation where the power is cut off during data writing is read and error detection is performed, the number of bits that are “1 error” among all detected error bits is , More than the number of bits that are “0 error”.

  Therefore, in the determination unit 245 of the memory control unit 24, when the 1 error occurrence number EG1 is larger than the 0 error occurrence number EG0, the read data RD is invalidated by being destroyed by the power interruption at the time of writing. It is judged as data.

  Note that when data written in a situation where the power is cut off during data writing is read, the ratio of “1 error” is actually included in all error bits generated in the bit sequence of the read data RD. This is significantly larger (for example, 9: 1) than the ratio of “0 error”. Therefore, the determination unit 245 writes the read data RD when the 1 error occurrence number EG1 is larger than the value (EG0 + SV) obtained by adding the power interruption determination shift value SV to the 0 error occurrence number EG0. It may be determined that the data is invalid data that has been destroyed due to power interruption. In addition, the determination unit 245 determines that the ratio of the number of bits of “1 error” among all error bits generated in the bit sequence of the read data RD is greater than the power cutoff determination threshold (for example, 90%). The read data RD may be determined to be invalid data that has been destroyed by power-off at the time of writing. In short, when data written in a situation where the power is cut off during data writing is read, the ratio of “1 error” among all error bits actually generated in the bit sequence of read data RD is “ In view of the fact that the number of errors is significantly larger than the ratio of “0 error”, the determination unit 245 performs the determination as described above.

  Therefore, according to the memory control unit 24, it is possible to detect whether or not the read data is the data destroyed by the power interruption during the writing process by one reading, and this data is set as invalid data. It becomes possible to manage. This avoids an unstable state in which incorrect data is read from one address and normal or correctable data is read due to power interruption during the writing process. The

  Therefore, according to the present invention, it is possible to suppress a decrease in reliability of read data even if corrupted data is written in the memory due to power interruption during the writing process, and the stability of the entire system can be suppressed. Become figured.

  Here, since the storage device 2 uses the NAND flash memory 25 as the storage medium, data destruction occurs due to read disturb, retention, power interruption during writing, or the like. Therefore, the memory control unit 24 performs rewriting of data, that is, a so-called refresh process periodically or during a read operation.

  FIG. 3 is a flowchart showing a refresh control routine executed by the memory control unit 24 in accordance with the read operation of the read data RD from the flash memory 25. In this refresh control routine, the error detection and correction processing by the error detection and correction unit 241 and the count operation by the 0 error counter 242 and the 1 error counter 243 are completed for the read data RD read from the flash memory 25. After that, it is implemented by the memory control unit 24.

  In FIG. 3, first, the memory control unit 24 adds the 0 error occurrence number EG0 and the 1 error occurrence number EG1 stored in the register 244 to obtain an error total number EA (step S1). It is determined whether or not the value is larger than the refresh execution threshold value EX (step S2). If it is determined in step S2 that the total error number EA is less than or equal to the refresh execution threshold value EX, the memory control unit 24 exits this refresh control routine. That is, at this time, the refresh process is not performed.

  If it is determined in step S2 that the total error number EA is larger than the refresh execution threshold value EX, the memory control unit 24 adds the power-off determination shift value SV to the above-described zero error occurrence number EG0 (EG0 + SV). It is determined whether or not the error occurrence number EG1 is larger (step S3).

  If it is determined in step S3 that the number of occurrences of one error EG1 is equal to or less than the above (EG0 + SV), the memory control unit 24 determines that a read disturb has occurred that changes the value of the peripheral memory cell during data reading. Then, the first block refresh process is executed (step S4).

  In the first block refresh process, the memory control unit 24, as shown in FIG. 4A, all data in the block BL1 to which the page EPG in which the read data RD read from the flash memory 25 is written belongs. The error detection and correction unit 241 performs error correction processing while sequentially reading out. Then, as shown in FIG. 4A, the memory control unit 24 copies all the corrected data to another block BL2. At this time, the memory control unit 24 updates the management information data KD stored in the register 244 so as to manage the block BL1 as an invalid block and the block BL2 as a valid block.

  If it is determined in step S3 that the number of occurrences of one error EG1 is larger than (EG0 + SV) described above, the memory control unit 24 uses the write order management information TM stored in the register 244 to It is determined whether or not the order of writing to the page in which the read data RD is stored is the newest among all the pages in the flash memory 25 (step S5). If it is determined in step S5 that the writing is not the latest writing, the memory control unit 24 determines that a retention that causes data loss due to a change with time has occurred, and executes the second block refresh process (step S5). S6).

  In the second block refresh process, the memory control unit 24, as shown in FIG. 4B, all data in the block BL1 to which the page EPG in which the read data RD read from the flash memory 25 is written belongs. Then, error correction processing is performed by the error detection / correction unit 241 and all the corrected data is overwritten in the block BL1. Therefore, at this time, since the memory control unit 24 continues to manage the block BL1 as a valid block, the management information data KD is not updated.

  If it is determined in step S5 that the order of writing to the page storing the read data RD is the latest, the memory control unit 24 shuts off the power supply during the data write operation. It is determined that the invalid data has been destroyed due to this, and page refresh processing is executed (step S7).

  In the page refresh process, as shown in FIG. 4C, the memory control unit 24 reads data only from the page EPG1 in which the read data RD read from the flash memory 25 is written, and the error detection and correction unit 241. To correct the error. Then, as shown in FIG. 4C, the memory control unit 24 copies the corrected data to the other page EPG2 in the block BL1 to which the page EPG1 belongs. In this page refresh process, the memory control unit 24 reads the data from only the page EPG1 in which the read data RD is written and performs error correction, as shown in FIG. You may make it copy to page EPG2 in block BL1 different from block BL1 to which. Then, the memory control unit 24 updates the management information data KD stored in the register 244 to manage the page EPG1 as an invalid page and the page EPG2 as a valid page.

  After step S4, S6 or S7 described above, the memory control unit 24 ends the refresh control routine shown in FIG.

  That is, when power is cut off during a write operation, write drive (for example, charge injection into a memory cell) becomes insufficient, so a logic level 0 state (for example, a desired amount of charge is accumulated) There is a high possibility that “1 error” will occur in a memory cell that has not been completely written to. Similarly, the possibility of “1 error” also increases in a memory cell in which the logic level 0 state cannot be maintained due to retention. Therefore, when there is an error in the read data RD, the memory control unit 24 determines that the ratio of “1 error” to the total number of error occurrences is larger than the ratio of “0 error” (S3). In this case, it is determined that the power interruption or retention during the writing operation has occurred. Here, retention is less likely to occur as the elapsed period from the end of writing is shorter. Therefore, the memory control unit 24 determines that the ratio of “1 error” to the total number of error occurrences is larger than the ratio of “0 error” (S3), and the read data RD that is the determination target is When it is determined that writing to the stored page is the newest among all the pages (S5), it is determined that the cause of “1 error” is the power shutdown at the time of writing. Judging that it is.

  At this time, in the retention, the same “1 error” occurs not only in the page where “1 error” is detected, but also in the entire block including the page.

  Therefore, if it is determined that the cause of “1 error” is retention, the memory control unit 24 applies the entire block including the page where “1 error” is detected, as shown in FIG. Perform a refresh process.

  On the other hand, when the power is cut off during the writing operation, “1 error” occurs only in the page in the middle of writing, and it is unlikely that the entire block is affected.

  Therefore, when it is determined that the cause of “1 error” is the power interruption during the writing operation, the memory control unit 24 determines “1 error” as shown in FIG. 4C or FIG. In other words, the refresh process is performed only on the page storing the data in which the data is detected.

  Therefore, according to the refresh process described above, when data that has been destroyed due to power-off during a write operation is written, the data is rewritten only for the page where the data is stored. Therefore, the processing time and power consumption can be reduced as compared with the case where the refresh process is performed on the entire block.

  In the first block refresh process performed when read disturb occurs in step S4 shown in FIG. 3, all data in the block BL1 including the page EPG is corrected as shown in FIG. Although copying is performed to the block BL2, the block BL1 including the page EPG may be overwritten as shown in FIG. 4B.

  Further, in the second block refresh process performed at the time of occurrence of retention in step S6 shown in FIG. 3, after correcting all data in the block BL1 including the page EPG as shown in FIG. 4B, this block BL1 However, it may be copied to another block BL2 as shown in FIG.

  Further, in the page refresh process in step S7 shown in FIG. 3, as shown in FIG. 4C or FIG. 4D, the data stored in the page EPG1 to be refreshed is subjected to error correction. Is copied to another page EPG2, but as shown in FIG. 5, the corrected data may be overwritten on the page EPG1 itself. As described above, if the same page is overwritten as the page refresh process, the data erasure required when copying to another page as shown in FIG. 4C or FIG. 4D is performed. No processing is required. Therefore, it is possible to reduce the processing time and suppress the decrease in the lifetime of the flash memory 25 due to the data erasure.

  FIG. 6 is a block diagram showing an information processing system including another semiconductor memory control device according to the present invention. Such an information processing system includes a host information processing apparatus 1 and a storage device 2 in the same manner as the information processing system shown in FIG.

  The host information processing apparatus 1 performs various information processing based on data stored in the storage device 2 or externally supplied data, and writes a write command to which data is to be written, a write destination address, and a write The storage device 2 is supplied with read data or a read command for urging the data to be read and a read source address.

  The storage device 2 includes a host IF unit 21, a memory access bus 22, a CPU 23, a memory control unit 34, and a NAND flash memory 25.

  The host IF unit 21 receives a write command, a read command, an address, and write data supplied from the host information processing apparatus 1 and supplies them to the CPU 23 via the memory access bus 22. The host IF unit 21 receives the read data RDD sent from the memory control unit 34 via the memory access bus 22 and supplies it to the host information processing apparatus 1. The CPU 23 generates a memory write control signal for writing the write data at this address in accordance with the write command, address and write data supplied via the memory access bus 22, The data is supplied to the memory control unit 34 via the access bus 22. Further, the CPU 23 generates a memory read control signal for reading data from the address in accordance with the read command and the address supplied via the memory access bus 22, and generates the memory read control signal via the memory access bus 22. This is supplied to the memory control unit 34.

  The memory control unit 34 includes modules such as an error correction coding unit 240, a register 244, an error detection and correction unit 341, an error counter 342, and a reading number counter 343.

  In response to the memory write control signal described above, the error correction coding unit 240 adds an error correction code such as a BCH code to the write data indicated by the memory write control signal to generate an error. Write-encoded write data WD is generated and stored in register 244.

  The error detection / correction unit 341 performs an error detection process on the read data RD read from the flash memory 25. When an error exists, the error detection / correction unit 341 detects an error bit in the bit sequence of the read data RD. An error detection pulse is generated and supplied to the error counter 342. Further, when there is an error in the read data RD, the error detection / correction unit 341 determines whether or not the error can be corrected, and when the error can be corrected. Performs error correction processing on the read data RD, and stores the corrected data in the register 244 as read data RDD as shown in FIG. When there is no error in the read data RD read from the flash memory 25, the error detection / correction unit 341 stores the read data RD in the register 244 as the read data RDD. That is, only valid data among the read data RD is stored in the register 244 as the read data RDD.

  The error counter 342 counts the number of supplied error detection pulses, and stores the count value in the register 244 as the total error number EA.

  The number-of-reads counter 343 counts the number of times of reading at the time when one read data RD is repeatedly read in a reading determination control routine (described later), and outputs a number of times of reading RN indicating the number of times.

  The memory control unit 34 reflects the operation of these modules, and accesses the flash memory 25 according to the memory write control signal or the memory read control signal as follows.

  That is, in response to the memory write control signal, the memory control unit 34 writes the write data WD stored in the register 244 together with the address designated by the memory write control signal and the data that prompts the data writing. A command signal is supplied to the flash memory 25. Thereby, the flash memory 25 writes the write data WD at the designated address.

  Further, when a memory read control signal is supplied via the memory access bus 22, the memory control unit 34 executes a read determination control routine as shown in FIG.

  In FIG. 7, first, the memory control unit 34 sets “0” in the read number counter 343 as an initial value of the read number RN in the read number counter 343 (step S71). Next, the memory control unit 34 performs a read access to supply the flash memory 25 with a read command signal for urging data reading while supplying the address specified by the memory read control signal to the flash memory 25 (step S40). S72). As a result, the flash memory 25 reads the write data WD stored at the designated address and supplies it to the memory control unit 34 as the read data RD described above. The bit length of each of the write data WD and the read data RD is a unit block length as an error correction code, a bit length for one page as a NAND flash memory, or the like. At this time, each time the read data RD is read from the flash memory 25, the error detection / correction unit 341 performs error detection processing on the read data RD, and if there is an error, the error detection / correction unit 341 can continue to correct the error. It is determined whether or not. If error correction is possible, the error detection / correction unit 341 performs error correction processing on the read data RD and stores the corrected data in the register 244 as read data RDD. On the other hand, when there is no error in the read data RD, the error detection / correction unit 341 stores the read data RD in the register 244 as the read data RDD. That is, only read data RD read from the flash memory 25 that has no error or that has an error but can be corrected is stored in the register 244 as read data RDD that is valid data. .

  Here, the memory control unit 34 determines whether or not there is an error in the error detection and correction unit 341 (step S73). If it is determined that there is an error, the memory control unit 34 can continue to correct the error. It is determined whether or not it is possible (step S74). If it is determined in step S74 that error correction is impossible, the memory control unit 34 determines that the read data RD is data destroyed by power-off during data writing, and invalidates the read data RD. In addition to the data, the management information data KD is updated to manage the storage area (page or block) of the read data RD as a refresh target (step S75).

  If it is determined in step S74 that error correction is possible, or if it is determined in step S73 that there is no error, the memory control unit 34 sets the current read count RN in the read count counter 343 to “ A value obtained by adding “1” is set as a new reading number RN in the reading number counter 343 (step S76). Next, the memory control unit 34 determines whether or not the read count RN is greater than the invalidity determination count IVN (step S77). If it is determined in step S77 that the read count RN is less than or equal to the invalid determination count IVN, the memory control unit 34 returns to step S72 and repeatedly executes the above-described operation.

  On the other hand, when it is determined in step S77 that the read count RN is larger than the invalid determination count IVN, the memory control unit 34 reads the read data RDD as valid data stored in the register 244 into the memory access bus 22. To the host IF unit 21 (step S78). After execution of step S78 or S75, the memory control unit 34 exits from the read determination control routine and ends the above-described operation.

  As described above, the execution of the read determination control routine shown in FIG. 7 causes the memory control unit 34 to repeatedly read the data designated for reading from the flash memory 25 and check whether there is an error in the read data for each read. (S73) and whether or not error correction is possible (S74). At this time, if it is determined that there is an uncorrectable error before the number of repeated readings reaches the invalidity determination number IVN, the memory control unit 34 shuts off the power supply during data writing. Is determined to be invalid data that is in an unstable state. Then, the memory control unit 34 sets the read data as invalid data, and updates the management information data KD to manage the page where the read data is stored or the block to which the page belongs as a refresh target ( S75). That is, such control detects an area (page or block) in an unstable writing state in which invalid data is read from one address and normal or correctable data is read. It is done. On the other hand, when it is continuously determined that there is no error in each read data or that there is an error but correction is possible until the number of repeated readings reaches the invalid determination number IVN, the memory control unit 34 Determines that the read data is valid data and transmits it to the host information processing apparatus 1. The memory control unit 34 does not transmit read data managed as invalid data by the management information data KD to the host information processing apparatus 1 side.

  As described above, according to the memory control unit 34, a case where illegal data is read from one address and a case where normal or correctable data is read are mixed due to power interruption during data writing. An area (page) in an unstable writing state can be detected. Therefore, thereafter, the read data read from the area is set as invalid data, or the data is recovered by performing refresh processing on the area, so that the correct read data is stably supplied to the host information processing apparatus 1. It becomes possible to transmit.

  In addition, in order to detect the storage area of the data that has become an unstable writing state due to the power interruption during data writing, the memory control unit 24 shown in FIG. 1 performs the read determination control shown in FIG. The methods for determining invalid data may be combined. For example, in the flowchart shown in FIG. 7, step S3 shown in FIG. 3 is adopted instead of step S74. At this time, if it is determined in step S3 that the 1 error occurrence number EG1 is equal to or less than the number (EG0 + SV) obtained by adding the power interruption determination shift value SV to the 0 error occurrence number EG0, the memory control unit 34 The process proceeds to step S76 shown in FIG. On the other hand, if it is determined that the number of occurrences of one error EG1 is greater than (EG0 + SV), the memory control unit 34 determines that the read data RD has been destroyed due to power interruption during data writing. The process moves to execution of step S75 shown in FIG.

  Further, in the memory control unit 24 or 34 shown in FIG. 1 or FIG. 6, in accordance with the read command supplied from the host information processing apparatus 1 as an external device, the invalid data determination operation as described above and the operation shown in FIG. Although the refresh process or the read determination control as shown in FIG. 7 is started, the process described above may be started at another timing.

  For example, the memory control unit 24 (or 34) is provided with a means for generating a read command for prompting data reading in response to power-on, and the memory control unit 24 (or in response to the read command generated in response to power-on. 34) may start the invalid data determination operation as described above, the refresh process shown in FIG. 3, or the read determination control as shown in FIG.

  The memory control unit 24 (or 34) is provided with a means for generating a read command for urging data reading during a standby period when no access is made from the host information processing apparatus 1, and the read command generated during the standby period is provided. In response to this, the memory control unit 24 (or 34) may start the invalid data determination operation as described above, the refresh process shown in FIG. 3, or the read determination control as shown in FIG.

  Further, in the determination unit 245 shown in FIG. 1, invalid data is determined for all storage areas in the flash memory 25, but only for pages with the latest writing order among all pages. The invalid data may be determined as described above.

  In the embodiment shown in FIG. 1 or FIG. 6, the state of all the memory cells in the block including the page to be written is set to the logic level 1 state, that is, the data erase state, Data writing is performed such that only the desired memory cell is changed to a logic level 0 state. However, data writing may be performed in which the data erase state in the memory cell is set to the logic level 0 and the state is changed to the logic level 1 state. In the above embodiment, the states of logic levels 1 and 0 are represented by the difference in the amount of charge stored in the memory cell. However, the states of logic levels 1 and 0 are represented by the difference in physical properties other than the charge. You may make it express. In the above embodiment, the NAND flash memory 25 is used as the nonvolatile memory, but the present invention is not limited to this.

  In short, the present invention sets all memory cells in a memory cell group composed of a plurality of memory cells to a state of a first logic level, and then sets only a desired memory cell in the memory cell group to a second logic level. The present invention is applied to a semiconductor memory in which data is written to make a transition to a level state and data is read from the memory cell group in response to a read command to perform access such that a read data piece (RD) is obtained.

  At this time, in the present invention, the error detection unit (241) detects an error bit by performing error detection processing on the read data piece. Then, the determination unit (245) determines that the number of error bits having the first logic level described above is greater than the number of error bits having the second logic level among all error bits detected from the read data piece. If it is larger, it is determined that this read data piece is invalid data.

  Alternatively, as another aspect, the error detection / correction determination unit (341) detects whether or not an error has occurred in the read data piece (RD) read from the memory cell group and an error has occurred. Whether or not correction is possible is determined. At this time, if it is determined that there is no error in the read data piece, or that an error has occurred but that it can be corrected, the read control unit (S71 to S77) stores the memory for the invalid determination count (IVN). Read data pieces repeatedly from the cell group. At this time, if the error detection / correction determination unit (341) determines that at least one of the read data pieces repeatedly read is uncorrectable, the determination unit (S74, S75) It is determined that the read data piece is invalid data.

2 storage device 24 memory control unit 25 flash memory 241 error detection correction unit 243 1 error counter 245 determination unit

Claims (5)

A control device for a semiconductor memory that performs data writing and reading in units of a memory cell group composed of a plurality of memory cells,
An error detection and correction determination unit that detects whether or not an error has occurred in the read data piece read from the memory cell group, and determines whether or not the error can be corrected if an error has occurred;
When the error detection / correction determination unit determines that no error has occurred in the read data piece, or that an error has occurred but is correctable, the read data is repeatedly read from the memory cell group by the number of invalidity determination times. A read control unit for reading out pieces,
When at least one of the read data pieces read repeatedly by the read control unit by the number of invalidity determination times is determined to be uncorrectable by the error detection / correction determination unit, the read And a determination unit that determines that the data piece is invalid data to be refreshed.   2. The semiconductor memory control device according to claim 1, wherein the determination unit starts an operation in response to a read command supplied from an external device. Means for generating a read command for urging data read from the memory cell group in response to power-on,
3. The semiconductor memory control device according to claim 2, wherein the determination unit starts an operation in response to the read command generated in response to the power-on. Means for generating a read command for urging data reading from the memory cell group during a standby period in which no access is made from an external device;
2. The semiconductor memory control device according to claim 1, wherein the determination unit starts an operation in response to the read command generated during the standby period. A method of controlling a semiconductor memory that performs data writing and reading in units of a memory cell group composed of a plurality of memory cells,
Detecting whether or not an error has occurred in the read data piece read from the memory cell group, and determining whether or not the error can be corrected if an error has occurred;
When it is determined that no error has occurred in the read data piece or that an error has occurred but correction is possible, the read data piece is repeatedly read from the memory cell group for the number of invalid determination times. A control of a semiconductor memory, wherein when it is determined that at least one of the read data pieces is uncorrectable, the read data piece is determined to be invalid data to be refreshed. Method.

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