JP4866107B2 - Nonvolatile memory device and write determination method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it becomes the same as the entire deletion completion though the deletion of a physical page is not completed for data after error correction is performed after power interruption immediately after starting write to the physical page and determination as the state that write is normally performed is erroneously made. <P>SOLUTION: When writing the data to a nonvolatile memory, a write mark is surely written simultaneously. Information is read for each of a plurality of write units included in a unit block and the error correction of the read information is performed by an error correction function. Then, a write state for each write unit is determined on the basis of the read information of the write mark. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a non-volatile storage device using a non-volatile memory such as a flash memory and a write determination method thereof.

  In recent years, a nonvolatile memory device equipped with a nonvolatile memory has been put into practical use as a memory card, and the market has been expanded as a memory card for digital cameras and mobile phones. Memory cards are expanding in capacity and speed for applications such as higher pixel count of digital cameras and video recording on mobile phones.

  The main nonvolatile memory used in the memory card is a flash memory. As the capacity of flash memory increases, the physical block size, which is an erasure unit, tends to increase. However, the management unit viewed from the host and the user operating the host as a memory card is constant. As a result, it is necessary to adjust the data management on the host side and the data management on the flash memory side under the control of the memory controller mounted on the memory card.

  In order to improve reliability, an error correction code (hereinafter simply referred to as ECC) is added to the nonvolatile memory when data is written, and error correction is performed after reading. A device that manages a state in which a physical block is written halfway is known.

In general, the management unit of data stored in the memory card by the host is smaller than 128 kB which is the capacity of the physical block, for example, 16 kB. Therefore, it becomes necessary for the memory controller to manage the state written halfway to the physical block. A method for managing partial writing in a physical block is also described in Patent Document 1.
JP 2001-154909 A

  However, in the conventional write determination method, an error that cannot be corrected by the ECC circuit has occurred because the original write data has not been normally written due to the power interruption during the writing of the physical page. to decide. This determination method can detect that data has not been written correctly due to power shutdown. However, when power is interrupted and the data to be originally written is not written correctly, it is determined that the error correction is possible by the ECC circuit. If no data is written and only a few bits within the correctable range are written, the data after error correction is all “1”, which is the same as all erased. Become. In this case, there is a possibility that the physical page has not been erased, and it is erroneously determined that the data has been normally written even though the data has not been normally written. If an erroneous determination occurs, the original data that is erroneously updated by the erroneous determination is the same as all erased data in order to determine that data that has not been written normally is written normally. There is a problem that the original data may be lost and the reliability of the data may not be maintained.

  It is an object of the present invention to provide a nonvolatile memory device and a method for determining writing thereof that can accurately detect an abnormality such as a power interruption during writing.

In order to solve this problem, the nonvolatile memory device of the present invention includes a storage area including a plurality of erase unit blocks, stores user data, and stores an area for storing a write mark for each one or a plurality of write units. A non-volatile memory, and a memory controller that writes and reads data to and from the non-volatile memory, and the memory controller detects whether all the data read from the non-volatile memory has been erased An erase detection circuit that detects and corrects errors in the read data, and when writing data to the non-volatile memory , the write mark is recorded in the write mark while the data is read sometimes the output of the write mark and the output of the total erasure detection circuit and the error detecting and correcting circuit A control circuit for detecting an abnormality of the after writing based and has a.

  Here, the minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing with a single write command to the nonvolatile memory is the write unit. Assuming that the maximum unit that can be written with a single write command to the memory is the maximum write unit, the write mark is the write unit of the final maximum write unit when it is divided into the maximum write units within the management unit. You may make it provide for every.

  Here, the minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing with a single write command to the nonvolatile memory is the write unit. If the maximum unit that can be written by a single write command to the memory is the maximum write unit, the write mark is provided for every write unit when the management unit is less than or equal to the maximum write unit. Also good.

  Here, the erasing unit block may be configured by erasing units across a plurality of nonvolatile memories as a group.

  Here, the erase unit block may be constituted by an integral multiple of the erase unit of the nonvolatile memory.

  In order to solve this problem, a write determination method for a nonvolatile storage device according to the present invention includes a storage area including a plurality of erase unit blocks, stores user data, and writes a write mark for each one or a plurality of write units. A non-volatile memory having a storage area, and a memory controller for writing and reading data to and from the non-volatile memory, and a non-volatile storage device write determination method comprising: at least one of a plurality of at least one plurality of units included in the unit block A read step for reading data for each writing unit, an erased determination step for determining whether or not all read data is erased data, an error correction step for performing error correction on the data read in the read step, and data Based on the presence or absence of the write mark when reading It includes a step of detecting an abnormality when write attempts, and is to determine the programming state of the non-volatile memory.

  Here, when it is determined that the read data has not been erased and the write mark is not yet written, it may be determined that an abnormality has occurred during writing in the write unit.

  Here, the minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing with a single write command to the nonvolatile memory is the write unit. Assuming that the maximum unit that can be written with a single write command to the memory is the maximum write unit, the write mark is the write unit of the final maximum write unit when it is divided into the maximum write units within the management unit. It may be provided for each.

  Here, the minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing with a single write command to the nonvolatile memory is the write unit. If the maximum unit that can be written by a single write command to the memory is the maximum write unit, the write mark is provided for every write unit when the management unit is less than or equal to the maximum write unit. Also good.

  Here, the erase unit block may be configured as a group of erase units that span a plurality of the nonvolatile memories.

  Here, the erase unit block may be constituted by an integral multiple of the erase unit of the nonvolatile memory.

  As described above, according to the present invention, the control state determines the write state based on the output of the all-erase detection circuit and the presence / absence of the write mark, thereby accurately detecting an abnormality such as power interruption during writing. It is possible to provide a highly reliable non-volatile memory device and a writing determination method thereof.

  A nonvolatile memory device and a write determination method thereof according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a nonvolatile memory device and a host according to an embodiment of the present invention. In FIG. 1, a host 101 has a non-volatile storage device attached to write or read data. The memory card 102 is a nonvolatile storage device. The memory card 102 includes a flash memory 103 in which data to be written from the host 101 is stored, and a memory controller 104 that controls the interface (IF) with the host 101 and controls the flash memory 103. The memory controller 104 is provided with a host interface (IF) 105 that controls an interface with the host 101 and a flash interface (IF) 106 that controls an interface with the flash memory 103. The control circuit 107 is a control unit that controls the internal operation of the memory controller 104, and has a write mark determination function as will be described in detail later. The buffer memory 108 is a buffer inside the memory controller 104 for temporarily storing read and write data between the host 101 and the flash memory 103. The buffer memory 108 has a capacity of 512 B (bytes), for example. The ECC circuit 109 performs an operation for generating an error correction code (ECC) to be added to data to be written from the host 101 to the flash memory 103, or performs an error correction operation when data is read from the flash memory 103 to the host 101, and an error is corrected. This is a circuit to be corrected. The ECC circuit 109 uses a Reed-Solomon code or the like, but detects that an error exceeding the correction capability has occurred by taking a correction code correction capability larger than the amount of data that needs to be corrected. (The case where the result of calculating the error correction position is an address where data does not exist or a correction pattern where data does not exist). The all-erase detection circuit 110 determines whether all data read from the flash memory 103 has been erased.

  FIG. 2 shows an internal configuration of the flash memory 103. If the flash memory 103 is a flash memory having a capacity of 128 MB, for example, there are 1024 physical blocks PB0 to PB1023 inside. Each physical block has a capacity of 128 kB, and this physical block is a data erasure unit block in the flash memory 103. The capacity value here indicates the capacity of the area where user data transferred from the host is stored, and actually has a management area for storing ECC and the like.

  FIG. 3 shows an internal configuration of one physical block of the flash memory. Within each physical block, there are 64 physical pages PP0 to PP63, each having a capacity of 2 kB, and this physical page is a unit that can be written by a single write command in the flash memory 103. is there. Note that the capacity value here also indicates the capacity of the area for storing user data transferred from the host, and actually has a management area for storing ECC and the like.

  FIG. 4 shows an example of the configuration of logical data inside a physical page. Each physical page has a 2 kB data area and a 64 B management area. Data from the host 101 is stored in the data area, and management information used inside the memory card 102 such as a logical address and ECC is stored in the management area. It is set so that the ECC is judged to be correct in a state where ECC is generally added and erased. In this case, too, coding that does not cause an error correction error in the erased state is used. Further, the management area has an area for recording a write mark. The write mark WM is a fixed value “0” that is always written when data is written, and is 2 bits here. The write mark is written to both the data area and the management area when data is written to one physical page which is a write unit. The write mark WM is in the area to be subjected to the ECC calculation, and if there is an error in reading, it is to be corrected.

  In this example, the writing unit is one physical page, that is, 2 kB, and the management unit is also one physical page, that is, 2 kB. FIG. 5 shows an example of the inside of the physical block of the flash memory 103, but data has been written in the 16 kB capacity portion of the physical pages PP0 to PP7, and the physical pages PP8 to PP63 are not yet written. It is. The memory controller 104 not only manages this state, but also needs to determine that the memory card 102 is in the write state as shown in FIG. 5 after the power is turned on. Therefore, when reading the data of each physical page of the physical block, the memory controller 104 uses the all erase detection circuit 110 to determine whether it has been written or not written.

  FIG. 6 shows a simple configuration of the all-erase detection circuit 110. The main components of the all-erase detection circuit 110 are an AND gate 111 and a flip-flop 112. The output of the AND gate 111 is connected to the D terminal that is the input of the flip-flop 112, and one input of the AND gate 111 is connected to the Q terminal that is the output of the flip-flop 112. The other input of the AND gate 111 is an input of the all erasure detection circuit 110, and the Q terminal which is the output of the flip-flop 112 is the output of the all erasure detection circuit 110. The flip-flop 112 receives a clock signal synchronized with data input to the all-erase detection circuit 110.

  First, the memory controller 104 sets the data latched in the flip-flop 112 of the all-erase detection circuit 110 to “1” when reading a physical page to be determined whether it has been erased or written. Then, all read data of the physical page is input to the all-erase detection circuit 110. Then, the output of the all-erase detection circuit 110 obtained after the reading is completed is a logical product operation of all the data read from the physical page. That is, if the output of the all erase detection circuit 110 is “1”, the data on the physical page is all “1” in an unwritten state, and if the output of the all erase detection circuit 110 is “0”, It can be seen that “0” is present in the data, and at least one bit exists.

  FIG. 7 is a diagram showing the data state of a certain erased physical page. The physical page includes a data area and a management area, and the management area includes a write mark area WM. Here, a case where a 2-bit area is allocated to the write mark area WM is shown. Since it has been erased, all data on the physical page is filled with “1” data. The data in the write mark area is also “1”.

  FIG. 8 is a diagram showing the data state of a written physical page. Areas indicated by hatching are data areas of either “1” or “0”. Since the data area stores data sent from the host 101, the data area is in either “1” or “0” state, and the logical block information and ECC in the management area are also in either “1” or “0” state. It can also take. However, since the data in the write mark area WM is to be written “0”, it is always “0”, and the state shown in FIG.

  FIG. 9 is a diagram showing an example of a data state in the case where a power interruption occurs immediately after starting to write to a certain erased physical page. Data in the data area and the management area is almost “1”, but only a total of 2 bits, 1 bit indicated by 901 in the data area and 1 bit indicated by 902 in the management area, is data “0”. Although the data “0” was supposed to be written in the write mark area WM, the power is cut off during the writing, so that the data remains “1” indicating unwritten.

  The output result when the all-erase detection circuit 110 is read out in the example of the physical page shown in FIG. 9 is “0” indicating that writing has been completed because there are areas 901 and 902 that are “0”. . If the performance of the ECC circuit 109 has the ability to correct an error of 2 bits or more, the data “0” in the areas 901 and 902 is corrected to “1” when the error correction process is performed and the data is read. Is possible. In this case, all data in the data area and the management area are corrected to “1”, and it is determined that there is no error that cannot be corrected. It should be noted here that after ECC error correction is performed, nothing is written in the write mark area WM.

  A physical block write determination method according to the present embodiment will be described with reference to the flowchart of FIG. First, in step 1001, the physical page to be read is set to the first page, for example, the physical page PP0. Hereinafter, the physical page thus set is referred to as a setting page. Next, in step 1002, all data of the target setting page is read out. At this time, the ECC circuit 109 performs an error correction operation, and the all erasure detection circuit 110 also performs an operation for detecting erased data. Next, in a determination step 1003, it is determined whether the setting page has been written based on the result of the all erasure determination circuit 110. If it is determined that writing has been completed, the process proceeds to determination step 1004. If it is determined that data has been erased, the process proceeds to result 1009. In result 1009, it is determined that the current setting page is in an unwritten state, and new data can be written from the setting page. On the other hand, in the determination step 1004, it is determined whether there is no error in the calculation result of the ECC circuit 109 or whether there is a correctable error. If it is determined that there is no error or correction is possible, the process proceeds to step 1005, and if it is determined that there is an error that cannot be corrected (the address indicated by the operation result covers an area where no error correction pattern exists in the data). In this case, the result is an uncorrectable error). In result 1010, it is determined that an abnormal state such as a power shutdown has occurred during data writing to the setting page, and data recovery processing is performed to eliminate the abnormal state. In the data recovery process, the data immediately before the page in which the error has occurred is regarded as valid data, and data is rewritten after the page in which the error has occurred. On the other hand, in step 1005, error correction is performed based on the calculation result of the ECC circuit 109. In the case of FIG. 9, since only 2 bits are 0, all the bits are “1”, that is, erased by error correction. Thereafter, the process proceeds to determination step 1006, where it is determined whether or not the write mark WM has been written to the data after error correction by the ECC circuit 109 using the write mark determination function of the control circuit 107. If it is determined that writing has been completed, the process proceeds to determination step 1007. If it is determined that writing has not been completed, the process proceeds to result 1010. In the result 1010, it is determined that there is an abnormal state such as a power shutdown while writing to the setting page, and data recovery processing for eliminating the abnormal state is performed. On the other hand, in the determination step 1007, it is determined whether or not the current setting page is the final page, that is, PP63, and if it is the final page, the process proceeds to a result 1011. In result 1011, it is determined that all pages have been written, and the process is terminated. On the other hand, if it is not the last page, the process proceeds to step 1008, the setting page to be read is incremented by 1, and the process proceeds to step 1002, and the same processing is repeated. According to the above determination flowchart, it is determined to which page of the physical block data has been written.

  In the present embodiment, as shown in FIG. 9, in the state where only a few bits within the correctable range, which are generated when the power is turned off immediately after the start of writing, are written, that is, not completely erased but an ECC error. Even in a state where there is no uncorrectable error, it is possible to detect an abnormality such as a power interruption during writing depending on whether or not the writing mark area has been written. In this embodiment, an abnormal process can be performed in the result step 1010, and a data recovery process can be performed, thereby improving data reliability.

  In this embodiment, a case has been described in which writing determination is performed for each physical page that is a writing unit of the flash memory that is a nonvolatile storage memory. However, the present embodiment is not necessarily limited to a physical page. If a determination can be made for each writing unit managed as a nonvolatile storage device system, the determination can be made in accordance with the spirit of the present invention.

  Here, the unit of writing is the minimum unit that can be written by a single write command to the flash memory, and the maximum unit of writing is the maximum unit that can be written by a single write command to the flash memory. The management unit is the minimum unit for writing to the flash memory when there is one write command from the host. Writing to the flash memory by a single write command from the host is not limited to one write, and may be written in multiple times. In addition, a plurality of management units may be written in one write to the flash memory, but writing is always performed in an integral multiple of the management unit.

  In the case of a system in which data can be written by dividing a physical page into a plurality of sectors, it is possible to make a determination by providing a write mark area for each sector which is a write unit. For example, in FIG. 11, the maximum writing unit is one physical page, and the writing unit and the management unit are one sector, that is, ¼ physical page. In this case, a write mark WM is provided for each sector that is a management unit of each page. Although the minimum unit for writing to the flash memory at one time is one sector, the maximum writing unit is one page, and it is possible to write simultaneously to four sectors existing on the same page. Rather than determining the writing state only by the unit, it is necessary to determine whether it is unwritten or written for each management unit over the page which is the maximum writing unit. In the information described for each sector in FIG. 11, “normally written” means that data has been normally written to the sector and the write mark has been set to written. Further, “erased (unwritten)” means that the sector has been erased and, of course, the write mark is in an unwritten state. Further, “written” (unwritten) means that the sector is not erased but has been written since the power is cut off immediately after writing, but the write mark is in an unwritten state.

  The state shown in FIG. 11 shows a state in which the power is cut off immediately after writing while writing the third sector of the physical page PP3. Writing is normally completed up to the second sector of PP3, and a part of the third sector has been written, but the write mark WM is in an unwritten state. The fourth sector and PP4 and thereafter are in an unwritten erased state. In this case, by determining the writing state of each sector over the physical page that is the maximum writing unit, PP0 to PP2 are written pages, PP3 is written to the second sector after writing to the second sector is correctly completed. It can be recognized that the power interruption occurs in the writing of three sectors and the data writing is not completed normally, and the data recovery can be performed correctly.

  As in FIG. 11, the maximum write unit is one physical page, the write unit is one sector, that is, 1/4 physical page, and the management unit is also one sector, that is, 1/4 physical page. In this case as well, as in the case of FIG. 11, it is necessary to determine whether the management unit is unwritten or has been written over the page which is the maximum writing unit. The notation for each sector written in FIG. 12 represents the same meaning as in FIG.

  Now, the state of FIG. 12 shows a state in which the power shutoff occurs immediately after writing during simultaneous writing to the four sectors included in the physical page PP3. Of the four sectors included in PP3, data is partially written only in the third sector, but the write mark in the third sector is still unwritten. Also in this case, by determining the writing state of each sector over the physical page which is the maximum writing unit, PP0-2 are written pages, PP3 first sector is erased, but PP3 remaining sectors It can be seen that the third sector has been partially written and the write mark WM has not been written. Therefore, after the writing to PP2 has been performed normally, the power shutoff occurs during the writing of PP3. It can be recognized that data writing has not been completed normally, and data recovery can be performed correctly.

  In some cases, a system that permits a data write state in a physical block in a plurality of write units may be configured. For example, in the system shown in FIG. 13, the writing unit is one physical page, the maximum writing unit is one physical page, and the management unit is two physical pages. In such a case, the determination can be made by providing the write mark WM only in the final maximum write unit among the plurality of maximum write units included in the management unit. This is because a write state less than the management unit is not allowed in the system, so that the management unit write can be determined if it can be correctly determined whether or not the final maximum write unit is correctly written. In other words, if the maximum non-final write unit included in the management unit is already written, it will not be misjudged as a management unit even if it is written correctly or not correctly written Even if a halfway write due to blocking is misjudged as a normal write, the final maximum write unit should have been erased, so a management unit is not configured and an abnormality can be detected). Therefore, the write mark WM is not required except for the last unit of the maximum write unit in the management unit. The notation for each page written in FIG. 13 represents the same meaning as in FIG.

  Now, the state of FIG. 13 shows a state in which a power interruption occurs immediately after writing during writing to the physical page PP3. In this case, by determining the writing state of each page for each management unit, the top management unit (PP0, PP1) is a written page, and the next management unit (PP2, PP3) is Since PP2 has been normally written, PP3 has been partially written, and the write mark WM has not been written, the power is shut down during the writing of the next management unit after the writing to the first management unit has been performed normally. It can be recognized that data writing has not been completed normally, and data recovery can be performed correctly.

  Further, in order to realize parallel writing for speeding up the writing performance, the management unit may extend over a plurality of physical blocks, or may extend over physical blocks existing in a plurality of nonvolatile memories. FIG. 14 shows an example of such a case, where the write unit is one physical page, the maximum write unit is two physical pages that span multiple physical blocks of one or more nonvolatile memories, and the management unit is two physical units. A page. In FIG. 14, one management unit is composed of one physical page of the physical block PB0 and two pages of the physical page corresponding to the physical block PB1. In this case, a write mark WM is provided on the physical page of each physical block as shown in the figure. The notation for each page written in FIG. 14 represents the same meaning as the notation for each sector in FIG.

  The state shown in FIG. 14 shows a state in which a power interruption occurs immediately after writing during simultaneous writing to the physical page PP3 of PB0 and PB1. In this case, by determining the write state of each page over each management unit, the management units (PB0 PP0, PB1 PP0), (PB0 PP1, PB1 PP1), (PB0 PP2, PB1 PP2) constituting the management unit are written. Management unit, the next management unit (PB0 PP3, PB1 PP3) has PB0 PP3 erased, but PB1 PP3 has been partially written and the write mark WM has not been written. (PB0 PP3, PB1 PP3) It is possible to recognize that the power interruption has occurred during the writing, and the data writing has not ended normally, and the data can be restored correctly.

  In general, a write mark is required for each write unit of the final maximum write unit when divided into the maximum write units in the management unit. However, when the management unit is smaller than the maximum writing unit, a writing mark is required for every writing unit. By arranging the write mark in this way, the write state of the nonvolatile memory can be determined.

  The nonvolatile storage device and the write determination method according to the present invention can further improve data reliability with respect to a host that stores data for a large-capacity nonvolatile storage device. The present invention can be applied to a recording medium of a portable AV device such as a still image recording / playback device or a moving image recording / playback device, or a portable communication device such as a mobile phone.

It is a block diagram which shows the structure of the non-volatile storage device and host apparatus by one Embodiment of this invention. It is the figure which showed the structure of the non-volatile memory mounted in the non-volatile storage device of this Embodiment. It is the figure which showed the structure of the non-volatile memory mounted in the non-volatile storage device of this Embodiment. It is the figure which showed the logical structure of the data in the physical page of this Embodiment. It is the figure which showed the writing state of the data of the non-volatile memory mounted in the non-volatile storage device of this Embodiment. FIG. 5 is a circuit diagram of an all erasure detection circuit according to the present embodiment. It is the figure which showed the data of the erased physical page of this Embodiment. It is the figure which showed the data of the written physical page of this Embodiment. It is the figure which showed the data of the physical page after the power-off immediately after writing of this Embodiment. It is a flowchart which shows the written physical page detection method of this Embodiment. It is a figure which shows the write state of the physical block by the other form of this invention. It is a figure which shows the write state of the physical block by the other form of this invention. It is a figure which shows the write state of the physical block by the other form of this invention. It is a figure which shows the write state of the physical block by the other form of this invention.

Explanation of symbols

101 Host 102 Memory Card 103 Flash Memory 104 Memory Controller 105 Host Interface 106 Flash Interface 107 Control Circuit 108 Page Buffer 109 ECC Circuit 110 All Erase Detection Circuit

Claims (11)

A non-volatile memory including a storage area composed of a plurality of erase unit blocks, storing user data, and storing an area for storing a write mark for each one or a plurality of write units;
A memory controller for writing and reading data to and from the non-volatile memory,
The memory controller is
An all-erase detection circuit for detecting whether all data read from the non-volatile memory is erased data;
An error detection and correction circuit for detecting and correcting an error in the read data;
When writing data to the non-volatile memory, a write mark is recorded in a write mark, while when reading data, after writing based on the write mark, the output of the all-erase detection circuit , and the output of the error detection and correction circuit And a control circuit for detecting an abnormality of the non-volatile memory device. The minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing by one write command to the nonvolatile memory is the write unit, and the nonvolatile unit is transferred to the nonvolatile memory. If the maximum unit that can be written with one write command is the maximum write unit,
The nonvolatile memory device according to claim 1, wherein the write mark is provided for each write unit of the final maximum write unit when the write mark is divided into the maximum write units in the management unit. The minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing by one write command to the nonvolatile memory is the write unit, and the nonvolatile unit is transferred to the nonvolatile memory. If the maximum unit that can be written with one write command is the maximum write unit,
The nonvolatile memory device according to claim 1, wherein the write mark is provided for every write unit when a management unit is equal to or less than a maximum write unit.   The non-volatile storage device according to claim 1, wherein the erase unit block is configured by erasing units extending over a plurality of non-volatile memories as a group.   The nonvolatile memory device according to claim 1, wherein the erase unit block is configured by an integral multiple of an erase unit of the nonvolatile memory. A non-volatile memory including a storage area composed of a plurality of erase unit blocks, storing user data, and storing an area for storing a write mark for each one or a plurality of write units;
A memory controller for writing and reading data to and from the non-volatile memory, and a non-volatile memory device write determination method comprising:
A reading step of reading data for each of at least one plurality of writing units included in the unit block;
An erased determination step for determining whether the read data is all erased data; and
An error correction step for performing error correction on the data read in the reading step;
And a step of detecting an abnormality at the time of reading based on the presence or absence of the write mark at the time of reading the data, and a method for determining the writing of the nonvolatile memory device for determining the writing state of the nonvolatile memory. When it is determined that the read data is not erased and the write mark is not written,
The write determination method for a nonvolatile memory device according to claim 6, wherein it is determined that an abnormality has occurred during writing in the write unit. The minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing by one write command to the nonvolatile memory is the write unit, and the nonvolatile unit is transferred to the nonvolatile memory. If the maximum unit that can be written with one write command is the maximum write unit,
The write determination method for a nonvolatile memory device according to claim 6, wherein the write mark is provided for each write unit of the final maximum write unit when the write mark is divided into the maximum write units in the management unit. The minimum unit for writing when there is a single write command from the outside is the management unit, and the minimum unit for writing by one write command to the nonvolatile memory is the write unit, and the nonvolatile unit is transferred to the nonvolatile memory. If the maximum unit that can be written with one write command is the maximum write unit,
The method according to claim 6, wherein the write mark is provided for every write unit when a management unit is equal to or less than a maximum write unit.   10. The non-volatile memory device write determination method according to claim 6, wherein the erase unit block is configured by erasing units extending over a plurality of the non-volatile memories as a group.   The write determination method for a nonvolatile memory device according to claim 6, wherein the erase unit block is configured by an integral multiple of an erase unit of the nonvolatile memory.

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