JP2009037317A - Memory controller, non-volatile storage device using the same, and non-volatile memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller for surely preventing the generation of any bit error due to read disturb, and a non-volatile storage device using the same, and a non-volatile storage system. <P>SOLUTION: This controller (memory controller) 2 for writing and reading data whose logical address is designated from host equipment 51 in and from a non-volatile memory 3 having a plurality of physical blocks 14 is provided with: a reading frequency table 11 for recording reading frequency by physical page units about a plurality of physical pages included in the plurality of physical blocks 14 as the reading frequency of the corresponding physical blocks 14; and a main control part 4 for restricting the reading operation of data to the non-volatile memory 3 by referring to the reading frequency table 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory controller that controls driving of a nonvolatile memory, a nonvolatile storage device using the same, and a nonvolatile storage system.

  In recent years, a nonvolatile storage device such as a memory card has been used as a storage medium for a portable information terminal represented by a digital camera or a mobile phone, and its market has been expanded. In addition, a nonvolatile memory such as a flash memory is mounted on the memory card. In such a non-volatile memory, the capacity thereof is increased with the miniaturization in the semiconductor process. Further, in the nonvolatile memory, the capacity is further increased by using the multi-value technology of the memory cell, and the bit unit price is lowered and it can be obtained at a low cost. In particular, NAND type flash memories are widely used because their bit unit price is the cheapest compared to other nonvolatile memories. However, this NAND-type flash memory has some characteristics related to data retention, and the characteristics may appear remarkably with miniaturization in a semiconductor process.

  Therefore, in the conventional nonvolatile memory device, for example, as described in Patent Document 1 below, the read disturb characteristic of the memory cell is improved by adjusting the voltage condition applied to the memory cell when reading data. It has been proposed to increase data retention.

In addition, as described in Patent Document 2 below, for example, a conventional nonvolatile memory device detects the progress of bit error due to read disturb by using an error correction code circuit when reading data. It has been proposed to prevent bit errors from occurring by refreshing data.
Japanese Patent Laid-Open No. 2002-298591 JP 2004-326867 A

  However, the conventional nonvolatile memory device as described above has a problem that it is impossible to reliably prevent the occurrence of bit errors due to read disturb. Specifically, in the conventional nonvolatile memory device described in Patent Document 1, the read disturb characteristic of the memory cell itself can surely be improved, but it is ensured that a bit error due to read disturb occurs. I couldn't prevent it. In addition, in the conventional nonvolatile memory device described in Patent Document 2, an error correction code circuit is used by performing a data read operation in order to detect the progress of bit error due to read disturb. This data read operation promotes deterioration that causes read disturb and may cause bit errors.

  In view of the above problems, an object of the present invention is to provide a memory controller that can reliably prevent the occurrence of bit errors due to read disturb, a nonvolatile memory device and a nonvolatile memory system using the memory controller.

In order to achieve the above object, a memory controller according to the present invention is a memory controller that writes and reads data specifying a logical address from the outside to a nonvolatile memory having a plurality of physical blocks,
An address conversion table for converting the logical address and the address of the physical block;
The logical address is input, and referring to the address conversion table, a main control unit that controls a data write operation and a read operation with respect to the nonvolatile memory,
For a plurality of physical pages included in each of the plurality of physical blocks, there is provided a read count table for recording the read count in units of physical pages as the read count of the corresponding physical block,
The main control unit is configured to limit a data read operation to the nonvolatile memory with reference to the read count table.

  The memory controller configured as described above has a read count table that records the number of reads in physical page units as the number of reads of the corresponding physical block for the physical pages contained in each physical block of the nonvolatile memory. In addition, a main control unit that restricts the data read operation is provided with reference to the read count table. Thus, unlike the conventional example, it is possible to reliably prevent the occurrence of bit errors due to read disturb.

Further, in the memory controller, the data stored in the physical block of the nonvolatile memory is configured to be cacheable, and when the data read operation is requested from the outside to the main control unit, An output memory for outputting the data to the outside without reading the data from the nonvolatile memory;
It is preferable that an output table for managing the read count of cache data cached in the output memory is provided.

  In this case, by caching the data in the output memory, when the data read operation is requested from the outside, the data can be output to the outside without being read from the nonvolatile memory. It is possible to efficiently suppress deterioration due to read disturb.

  In the memory controller, when the main control unit is requested to write data to the physical block of the non-volatile memory, the output is performed to determine whether the data is cached in the output memory. When determining by referring to the table and determining that the data is cached, an output memory release instruction unit is provided for instructing the output memory to release the cache of the data. May be.

  In this case, the output memory release instruction unit instructs the output memory to release the cache of the data written in the non-volatile memory, so that the effective use of the output memory can be facilitated. Efficiency can be increased.

  In the memory controller, the output memory release instructing unit determines whether the data is cached in the output memory when data is moved between different physical blocks of the nonvolatile memory. In the case of determining by referring to the output table and determining that the data is cached, it is preferable to instruct the output memory to release the cache of the data.

  In this case, the utilization efficiency of the output memory can be more reliably increased.

Further, in the memory controller, when a data read operation is requested from the outside, the main controller obtains a read count corresponding to the data for which the read operation is requested from the read count table, By referring to the output table and the read count table, the read count corresponding to the cache data cached in the output memory is obtained and compared with the read count corresponding to the data requested for the read operation. A cache determination unit for determining whether or not a data cache is necessary;
When the cache determination unit determines that the number of reads corresponding to the data requested for the read operation is greater than the number of reads corresponding to the cache data, the data requested for the read operation is output as the output It is preferable that a cache instruction unit for caching in the memory is provided.

  In this case, data cached in the output memory can be selected appropriately, and the convenience of the output memory can be improved.

  In the memory controller, when there are a plurality of cache data in the output memory, the cache determination unit determines a minimum number of times of reading out of a plurality of times of reading corresponding to the plurality of cache data. You may choose.

  In this case, the data with the smallest number of reads out of the plurality of data cached in the output memory is selected by the cache determination unit, so that the data cached in the output memory can be selected more appropriately, and the output The convenience of the memory can be easily improved.

In the memory controller, when a read operation for reading data from the physical block of the nonvolatile memory designated by an external logical address is requested to the main control unit, the number of times of reading the physical block is set. A number comparison unit that is obtained from the read number table and compares the obtained number of reads with a predetermined threshold;
When it is determined by the number comparison unit that the acquired number of readings has reached the predetermined threshold, the physical block different from the physical block of the nonvolatile memory specified by the logical address Preferably, a data movement instructing unit for instructing to move data for which the read operation is requested is provided.

  In this case, it is possible to reliably prevent the occurrence of bit errors due to read disturb while preventing the data retention in the nonvolatile memory from deteriorating.

The memory controller further includes a rewrite count table that records the erase count of the physical block as the rewrite count of the corresponding physical block,
In the main control unit, a function setting unit in which a function indicating a relationship between the number of rewrites and the allowable number of reads in the nonvolatile memory is set;
When a data read operation is requested from the outside, the read count corresponding to the data requested for the read operation is obtained from the read count table, and the rewrite count corresponding to the data requested for the read operation is obtained. Obtained from the function setting unit based on the obtained number of rewrites, and obtained the number of readings obtained from the obtained number of permitted readings, obtained from the rewrite number table and corresponding to the data for which the read operation is requested. By subtracting, the remaining allowable number of reads for the data for which the read operation is requested is calculated, and by referring to the output table and the read number table, it corresponds to the cache data cached in the output memory. The number of readings to be performed The rewrite count corresponding to the cache data is obtained from the rewrite count table, and the allowable read count corresponding to the cache data is obtained from the function setting unit based on the obtained rewrite count, and obtained from the obtained allowable read count. By subtracting the read count, the remaining allowable read count for the cache data is calculated and compared with the remaining allowable read count for the data for which the read operation is requested to determine whether the data cache is necessary. A cache determination unit for determining;
When the remaining allowable read count corresponding to the data for which the read operation is requested by the cache determination unit is smaller than the remaining allowable read count corresponding to the cache data, the data for which the read operation is requested is stored in the output memory. It is preferable to provide a cache instruction unit for caching.

  In this case, data cached in the output memory can be selected appropriately, and the convenience of the output memory can be improved. In addition, since the cache determination unit compares the remaining allowable read counts corresponding to the data for which the read operation is requested and the cache data, appropriate cache data is determined according to the degree of read disturb stress of the nonvolatile memory. Therefore, it is possible to more reliably prevent the occurrence of bit errors due to read disturb.

  In the memory controller, when there are a plurality of cache data in the output memory, the cache determination unit determines a minimum number of times of reading out of a plurality of times of reading corresponding to the plurality of cache data. You may choose.

  In this case, the data with the smallest number of reads out of the plurality of data cached in the output memory is selected by the cache determination unit, so that the data cached in the output memory can be selected more appropriately, and the output The convenience of the memory can be easily improved.

The memory controller further includes a rewrite count table that records the erase count of the physical block as the rewrite count of the corresponding physical block,
In the main control unit, a function setting unit in which a function indicating a relationship between the number of rewrites and the allowable number of reads in the nonvolatile memory is set;
When a read operation for reading data from a physical block of the nonvolatile memory designated by an external logical address is requested, the physical block read count is acquired from the read count table and the physical block is rewritten. The number comparison unit for obtaining the number of times from the rewrite number table, obtaining the allowable read number from the function setting unit based on the obtained number of rewrites, and comparing the acquired read number and the acquired allowable read number;
When it is determined by the number comparison unit that the acquired number of readings has reached the allowable number of readings, a physical block different from the physical block of the nonvolatile memory specified by the logical address Preferably, a data movement instructing unit for instructing to move data for which the read operation is requested is provided.

  In this case, it is possible to more reliably prevent the occurrence of bit errors due to read disturb while preventing the retention of data in the nonvolatile memory from being deteriorated.

  In the memory controller, in the function, the allowable number of readings may monotonously decrease with respect to the number of rewrites.

  In this case, a more appropriate function according to the read and write characteristics of the nonvolatile memory is used, and each processing operation in the cache determination unit and the data copy migration unit can be performed more appropriately.

In addition, a nonvolatile memory device of the present invention includes a nonvolatile memory having a plurality of physical blocks, and any one of the above memory controllers.

In addition, a nonvolatile memory system of the present invention includes a nonvolatile memory having a plurality of physical blocks, and a memory controller that writes and reads data specifying a logical address from the outside to the nonvolatile memory. A non-volatile storage system comprising: a volatile storage device; and a host device that performs an access instruction specifying a logical address for the non-volatile storage device,
Any of the above memory controllers is used as the memory controller.

  In the nonvolatile memory device and the nonvolatile memory system configured as described above, a memory controller that can reliably prevent the occurrence of bit errors due to read disturb is used. Therefore, a highly reliable nonvolatile memory device and A nonvolatile storage system can be easily configured.

  According to the present invention, it is possible to provide a memory controller that can reliably prevent the occurrence of bit errors due to read disturb, a nonvolatile memory device using the memory controller, and a nonvolatile memory system.

  Hereinafter, preferred embodiments of a memory controller, a nonvolatile memory device, and a nonvolatile memory system of the present invention will be described with reference to the drawings. In the following description, a case where the present invention is applied to a memory card will be described as an example.

[First Embodiment]
[Configuration of non-volatile storage system]
FIG. 1 is a block diagram showing a main configuration of a memory card and a nonvolatile storage system using the memory controller according to the first embodiment of the present invention. In FIG. 1, a nonvolatile memory system 50 according to the present embodiment is connected to a memory card 1 as a nonvolatile memory device, the memory card 1 is detachably connected, and a logical address is designated to the memory card 1. And a host device 51 that performs the access instruction. The nonvolatile storage system 50 is configured such that bidirectional data transfer can be performed between the memory card 1 and the host device 51. The non-volatile storage system 50 is built into a digital camera, personal computer, or the like, and a storage system that stores data therein is constructed.

  The memory card 1 includes a controller 2 configured using the memory controller of the present invention, and a nonvolatile memory 3 in which data writing control and reading control are performed by the controller 2. Specifically, for example, a NAND type flash memory is used as the nonvolatile memory 3, and the number of rewrites is limited to about 100,000. The nonvolatile memory 3 includes a plurality of physical blocks 14 as will be described in detail later.

  The controller 2 is configured to write and read data specifying an external logical address with respect to the nonvolatile memory 3. That is, the controller 2 writes the data transferred together with the write request specifying the logical address from the host device 51 provided outside the memory card 1 to the nonvolatile memory 3 or specifies the logical address from the host device 51. In response to a read request, data is read from the nonvolatile memory 3 and transferred to the host device 51.

  The controller 2 is configured to perform management and control for improving the data reliability of the nonvolatile memory 3. That is, the controller 2 includes the main control unit 4, the host I / F 5 and the memory I / F 7 as interfaces provided on the host device 51 side and the nonvolatile memory 3 side, and the host I / F 5. And a memory I / F 7 are provided with a buffer 6 and an error detection / correction circuit section (hereinafter abbreviated as “ECC”) 8. A CPU, DSP, or the like is used for the main control unit 4, and the above write request and read request are input from the host device 51.

  In the controller 2, when a write request is input to the main control unit 4, the data from the host device 51 sequentially passes through the host I / F 5, the buffer 6, and the memory I / F 7 to the nonvolatile memory 3. And the write operation is performed. Further, in the data writing operation, the ECC 8 adds a code for error correction to the data. On the other hand, when a read request is input to the main control unit 4 and a read operation is performed in the nonvolatile memory 3, data from the nonvolatile memory 3 is stored in the memory I / F 7, the buffer 6, and the host I / F 5. Are sequentially transferred to the host device 51. In the data read operation, the ECC 8 corrects an error in the data by using the added error correction code.

  The controller 2 also includes an address conversion table 9, a rewrite count table 10, and a read count table 11. Further, the controller 2 includes a cache memory 12 as an output memory configured to cache data stored in the physical block 14 of the nonvolatile memory 3, and the number of times the cache data cached in the cache memory 12 is read. The cache table 13 is provided as an output table for managing information such as, and the data is read from the nonvolatile memory 3 when the main control unit 4 is requested to read data from the host device 51. The data can be output from the cache memory 12 to the host device 51 without any problem. The cache memory 12 includes a plurality of, for example, 1024 pages assigned with page numbers 0 to 1023. Each page has a data area of 2 Kbytes, for example.

  In the controller 2, the main control unit 4 performs drive control of each unit of the controller 2 by appropriately referring to the address conversion table 9, the rewrite count table 10, the read count table 11, and the cache table 13. Yes. Further, in the controller 2, the main control unit 4 refers to the number-of-reads table 11, and restricts the data reading operation from the nonvolatile memory 3, and the nonvolatile memory 3 has a bit error caused by read disturb. It is comprised so that generation | occurrence | production can be prevented reliably (details are mentioned later).

  Here, the main control unit 4 will be described in detail with reference to FIG.

  FIG. 2 is a block diagram showing specific functional blocks of the main control unit shown in FIG.

  The main control unit 4 is functionally provided with a number comparison unit 40, a data movement instruction unit 41, and a cache control unit 42. The main control unit 4 is provided with an upper limit number storage unit 43 that stores a predetermined number of times as a predetermined threshold in advance. When the read operation for reading data from the physical block 14 of the nonvolatile memory 3 designated by the logical address from the host device 51 is requested, the number comparison unit 40 indicates the number of times the physical block 14 has been read. Get from. The number comparison unit 40 compares the acquired number of readings with the specified number of times stored in the upper limit number storage unit 43 and notifies the data movement instruction unit 41 of the comparison result. The specified number of times is the upper limit number of times of reading operation that does not cause a bit error due to read disturb in the physical block 14 of the nonvolatile memory 3.

  When the data movement instruction unit 41 determines from the comparison result from the number comparison unit 40 that the number of times of reading of data for which a read operation has been requested has reached the specified number of times, The other physical block 14 of the non-volatile memory 3 designated by a logical address different from the address is instructed to move the data. Thereby, in the nonvolatile memory 3, the data movement process for which the read operation is requested between the two physical blocks 14 is performed, and the data movement process is completed.

  The cache control unit 42 performs data write control and data read control in the cache memory 12, and the cache control unit 42 includes a cache determination unit 42a, a cache instruction unit 42b, and a cache release instruction unit 42c. ing. The cache determination unit 42a determines whether there is a data cacheable page in the cache memory 12 by referring to the cache table 13 when a data read operation is requested from the host device 51, and The determination result is notified to the cache instruction unit 42b.

  When the cache determination unit 42a determines that there is no page that can be cached in the cache memory 12, the cache determination unit 42a reads the number of times corresponding to the data for which the read operation is requested (that is, the physical block 14 in which the data is written). Is read from the read count table 11. Further, the cache determination unit 42 a refers to the read count table 11 and the cache table 13 to read the read count corresponding to the cache data cached in the cache memory 12 (that is, the same data as the cache data is written). The number of reads of the physical block 14 of the non-volatile memory 3 is determined. Then, the cache determination unit 42a compares the number of reads corresponding to the data for which the read operation is requested with the number of reads corresponding to the cache data, determines whether the data cache is necessary, and determines the determination result. The cache instruction unit 42b is notified.

  Further, the cache determination unit 42a is configured to select the minimum number of times of reading out of a plurality of times of reading corresponding to each of the plurality of cache data, when there are a plurality of pieces of cache data in the cache memory 12. Has been.

  The cache instruction unit 42b determines that there is a page that can be cached in the cache memory 12 from the cache determination unit 42a, or the number of reads corresponding to the data for which the read operation is requested is greater than the number of reads corresponding to the cache data. When it is notified that there are too many, the data requested to be read out is cached in the cache memory 12.

  The cache release instruction unit 42c constitutes an output memory release instruction unit, and when the host device 51 designates a logical address to the nonvolatile memory 3 and a data write operation is requested, the data is stored in the cache memory. 12 is determined by referring to the cache table 13. Further, when it is determined that the data is cached, the cache release instruction unit 42c instructs the cache memory 12 to release the cache of the data.

  Further, the cache release instruction unit 42 c determines whether or not the data is cached in the cache memory 12 even when the data is moved between the different physical blocks 14 of the nonvolatile memory 3. When it is determined that the data is cached, the cache memory 12 is instructed to release the cache of the data.

  Returning to FIG. 1, the nonvolatile memory 3 includes 4096 physical blocks 14 having block numbers 0 to 4095, for example. Each physical block 14 includes, for example, a 256 Kbyte data area and a 2 Kbyte management area. In each physical block 14, data from the host device 51 is written in the data area, and a code for error correction is written in the management area. Further, the physical block 14 is a data erasure unit of the nonvolatile memory 3. In the nonvolatile memory 3, data is rewritten in units of the physical block 14 which is an erasure unit when data is rewritten.

  Next, the physical block 14 will be specifically described with reference to FIG.

  As illustrated in FIG. 3, 128 physical pages 14 a with page numbers 0 to 127 are provided in the physical block 14. Each physical page 14a has, for example, a 2K byte data area and a 64 byte management area. The physical page 14a is both a data write unit and a data read unit. Therefore, when all the data of the physical block 14 is read in the nonvolatile memory 3, 128 read operations are performed on the physical block 14.

  Next, an address conversion table, a rewrite count table, a read count table, and a cache table provided in the controller 4 will be specifically described with reference to FIGS.

  4 is a diagram showing the configuration of the address conversion table shown in FIG. 1, and FIG. 5 is a diagram showing the configuration of the rewrite count table shown in FIG. 6 is a diagram showing the configuration of the read count table shown in FIG. 1, and FIG. 7 is a diagram showing the configuration of the cache table shown in FIG.

  As shown in FIG. 4, the address conversion table 9 is provided with a column 9a in which the logical address of the logical block is written and a column 9b in which the address of the physical block 14 is written. Is configured to be able to convert a logical address and a physical address associated with each other. In addition, the main control unit 4 uses the address conversion table 9 to convert the logical address from the host device 51 into the address of the corresponding physical block 14 of the nonvolatile memory 3, and uses the converted address to store the memory. By controlling the I / F 7, the corresponding physical block 14 in the nonvolatile memory 3 can be designated.

  As shown in FIG. 5, in the rewrite count table 10, a column 10a in which the number of the physical block 14 is written, and a column 10b in which a flag indicating whether valid data is written in the corresponding physical block 14 is written. And a column 10c in which the number of rewrites of the corresponding physical block 14 is written. In this column 10c, the erase count of the corresponding physical block 14 is recorded as the rewrite count of the physical block 14, and the rewrite count table 10 indicates the erase count of the physical block 14 as the physical block 14. It is configured to manage in units.

  As illustrated in FIG. 6, the read count table 11 includes a column 11 a in which the number of the physical block 14 is written and a column 11 b in which the read count of the corresponding physical block 14 is written. In the read count table 11, the read count in units of physical pages 14 a is recorded in the column 11 b as the read count of the corresponding physical block 14 for a plurality of physical pages 14 a included in each physical block 14. The read count table 11 is configured to be able to manage the read count in units of physical pages 14a. In other words, in this read count table 11, when an arbitrary physical block 14 is read in order from page 0, which is the first physical page 14a, to page 127, which is the last physical page 14a, those physical pages 14a The total number of readings of 128 is added to the number of readings of the column 11b in the arbitrary physical block 14 as the number of readings in the current reading operation.

  The address conversion table 9, the rewrite count table 10, and the read count table 11 all use a nonvolatile memory, preferably an MRAM (Magnetoresistive Random Access Memory) with a sufficiently large number of rewrites. Note that the address conversion table 9 and the rewrite count table 10 can be configured by a volatile memory such as SRAM (Static Random Access Memory). However, in this case, it is necessary to read the data from the non-volatile memory 3 in order to write the information in the non-volatile memory 3 and create the address conversion table 9 and the rewrite count table 10 after the memory card 1 is powered on. is there. On the other hand, it is not appropriate to configure the read count table 11 with a volatile memory. This is because the read count cannot be written in the non-volatile memory 3 where the limit of the rewrite count is severe.

  As shown in FIG. 7, the cache table 13 includes a column 13a in which the page address in the cache memory 12 is written, and a flag indicating whether the cache data cached in the corresponding page is valid or invalid. Is stored in the corresponding page by referring to the flag written in the column 13b, or the page is an empty page and new data is stored. It can be determined whether or not can be cached.

  In addition, the cache table 13 is provided with a column 13c in which the logical address of the cache data cached in the corresponding page is written, so that the main control unit 4 can search the cache source of the cache data. It has become. That is, the main control unit 4 can specify the physical page 14a of the physical block 14 of the nonvolatile memory 3 in which the same data as the cache data is written by using the logical address written in the column 13c. .

  Further, the cache table 13 is provided with a column 13d in which the read count of cache data cached in the corresponding page is written, and after the data is cached in the page, the cache memory 12 sends the data to the host device 51. The number of times the cache data is read, that is, the number of cache hits is recorded in the column 13d as the number of read times.

  Hereinafter, the data processing operation in the present embodiment configured as described above will be specifically described with reference to FIGS.

[Data read operation]
First, a data read operation will be described with reference to FIG.

  FIG. 8 is a flowchart showing a read operation in the memory card.

  In FIG. 8, when the host controller 51 requests the main controller 4 to read data specifying a logical address, the main controller 4 determines whether or not the data hits the cache (step S1). ). Specifically, the main control unit 4 searches the column 13c of the cache table 13 and checks whether or not the logical address from the host device 51 is written in the column 13c. It is determined whether or not it is cached in the cache memory 12. When the logical address corresponding to the column 13c is written, the flag of the column 13b is further confirmed. When the flag is valid, the main control unit 4 determines that a cache hit has occurred and starts the cache memory from the column 13a. The corresponding page address in 12 is obtained, the cache data is read from the cache memory 13 based on the obtained page address, and is output to the host device 51 (step S2). When the data read operation from the cache memory 12 to the host device 51 is completed, the main control unit 4 adds 1 to the read count in the corresponding column 13d of the cache table 13 and updates the read count. The read operation is finished.

  On the other hand, if no cache hit occurs in step S1, that is, if there is a miss hit, the main control unit 4 refers to the address conversion table 9 to read the physical block 14 to be read from the nonvolatile memory 3. And the physical page 14a. Then, the main control unit 4 controls the memory I / F 7 based on the determined physical page 14a to read data from the physical page 14a into the buffer 6, and the main control unit 4 further reads the host I / F. 5 is output to the host device 51 from the buffer 6 (step S3).

  Subsequently, the main control unit 4 increments the counter of the read count table 11 corresponding to the physical block 14 from which data has been read in step S3 (step S4). That is, the main control unit 4 adds the number of times of the number of physical pages 14a from which data has been read to the number of times of reading of the corresponding column 11b.

  Next, the main control unit 4 compares the number of readings after the number comparison unit 40 adds in step S4 with the specified number of times, and whether or not the number of readings reaches the specified number of times. A determination is made (step S5). If the read count has not reached the specified count, the main control unit 4 executes a read cache process for determining whether or not to cache the data read in step S3 with respect to the cache memory 12 (step S3). S6) The read operation is terminated.

  On the other hand, when it is determined in step S5 that the number of readings has reached the specified number, the main control unit 4 causes the number of readings to exceed the specified number when the next data reading operation is performed. Then, it is determined that a bit error due to read disturb may occur in the corresponding physical block 14, and the data movement instruction unit 41 executes a data movement process for moving the data to another physical block 14 (step S7). The read operation is finished.

[Data movement processing]
Next, with reference to FIGS. 9 to 13, the data movement process in step S <b> 7 will be specifically described.

  FIG. 9 is a flowchart showing a specific operation of the data movement process shown in FIG.

  First, as a state before the data movement process is executed, the read count table 11, the rewrite count table 10, the address conversion table 9, and the nonvolatile memory 3 are shown in FIGS. 10A, 10B, and 10C, respectively. ) And (d) will be described as an example. That is, in the nonvolatile memory 3, as shown in FIG. 10D, valid data of the block number 0005 of the logical block is written in the physical block 14 of the block number 0002. In S1, it is assumed that it corresponds to the logical address designated by the host device 51. It is assumed that invalid data exists in the physical block 14 with the block number 0003. Further, in correspondence with the state of the nonvolatile memory 3, in the address conversion table 9, as shown in FIG. 10C, as the physical block 14 corresponding to the logical block with the block number 0005, Block number 0002 is recorded.

  Further, in the rewrite count table 10, as shown in FIG. 10B, flags indicating validity and invalidity are recorded in the column 10b as the flags of the physical blocks 14 having the block numbers 0002 and 0003, respectively. In the column 10c, 100 times and 10 times are recorded as the number of rewrites of the physical block 14 with the block numbers 0002 and 0003, respectively. Further, as shown in FIG. 10A, it is assumed that 10000000 times and 1000 times are recorded in the read count table 11 as the read counts of the physical blocks 14 with the block numbers 0002 and 0003, respectively. In step S5, it is determined that the specified number of times has been reached, and the data movement processing in step S7 is performed. Here, the specified number of times is 10000000, and the number of reads of the physical block 14 with the block number 0002 is It is assumed that the data movement instructing unit 41 has determined that the specified number of times has been reached.

  As described above, since it has been determined that the read count of the physical block 14 with the block number 0002 has reached the specified count, the data movement instruction unit 41, as shown in step S8 of FIG. Referring to the column 10b and the column 10c, the physical block 14 having a smaller number of rewrites among the invalid physical blocks 14 is searched. Here, it is assumed that the physical block 14 having the block number 0003 is invalid and searched as the physical block 14 having the smallest number of rewrites.

  Subsequently, as shown in step S9 in FIG. 9, the data movement instruction unit 41 controls the memory I / F 7 to erase the physical block 14 having the block number 0003 searched in step S8. As a result, as shown in FIG. 11D, invalid data is erased in the physical block 14 of the block number 0003 of the nonvolatile memory 3. 11A to 11C, the read count table 11, the rewrite count table 10, and the address conversion table 9 are changed from the states shown in FIGS. 10A to 10C. Not.

  Next, the data movement instruction unit 41 acquires the address of the physical block 14 where the data of the movement source logical address that is the old data exists from the address conversion table 9 as shown in step S10 of FIG. This process uses the same address as the read process of the physical block 14 in step S3. Specifically, since the block number of the physical block 14 corresponding to the logical block of the block number 0005 in the address conversion table 9 is recorded as 0002, 0002 is acquired as the address of the physical block 14 of the movement source.

  Subsequently, as shown in step S11 of FIG. 9, the data movement instruction unit 41 sets the first page in the variable X, and further, the page X of the physical block 14 in which the old data that is the movement source acquired in step S10 exists. Is read out to the buffer 6 and the data read out to the buffer 6 is written to the page X of the erased physical block 14 to be moved in step S8 (step S12).

  Next, as shown in step S13 of FIG. 9, the data movement instructing unit 41 determines whether or not the variable X indicates the final page. If the variable X is not the final page, the data movement instructing unit 41 increments the variable X (step S13). S14), returning to step S12, the page moving process is repeated.

  On the other hand, if it is determined in step S13 that the page is the last page, the data movement instructing unit 41 determines that the data movement process has been completed. As a result, as shown in FIG. 12D, in the physical block 14 with the block number 0003 in the nonvolatile memory 3, the data of the logical block with the block number 0005 is moved and held. As shown in FIGS. 12A to 12C, the read count table 11, the rewrite count table 10, and the address conversion table 9 are changed from the states shown in FIGS. 10A to 10C. Not.

  Subsequently, the main control unit 4 updates the rewrite count table 10 as shown in step S15 of FIG. Thereafter, the main control unit 4 updates the address conversion table 9 (step S16), and further resets the counter corresponding to the physical block 14 with the block number 0003 in the read count table 11 (step S17). As a result, in the rewrite count table 10, as shown in FIG. 13B, the rewrite count of the column 10c corresponding to the physical block 14 of the block number 0003 that has been erased is incremented and changed to 11 times. . In the column 10b of the rewrite count table 10, the flags of the physical block 14 with the block numbers 0002 and 0003 are updated to invalid and valid, respectively. As a result, in the nonvolatile memory 3, the logical block data (old data) of the block number 0005 exists in the physical block 14 of the block number 0002, but in the memory card 1, the physical data in which invalid data exists thereafter. Recognized as block 14.

  In the address conversion table 9, the physical block 14 corresponding to the logical block with the block number 0005 is updated to the block number 0003. In the read count table 11, the read count of the physical block 14 with the block number 0003 that has been erased is reset to zero.

[Read cache processing]
Next, with reference to FIG. 14, the read cache process in step S6 will be specifically described.

  FIG. 14 is a flowchart showing a specific operation of the read cache process shown in FIG.

  As illustrated in step S <b> 18 of FIG. 14, the cache determination unit 42 a refers to the column 13 b of the cache table 13 and determines whether there is an invalid page in the cache memory 12. Specifically, when the cache determination unit 42a determines that there is an invalid page, the cache determination unit 42a determines that the cache memory 12 has a free space, and notifies the cache instruction unit 42b of the determination result. When the cache determination unit 42a notifies that the cache memory 12 has a free space, the cache instruction unit 42b caches the data in the cache memory 12 and registers it in the cache table 13 (step S19).

  Specifically, the cache instruction unit 42b causes the data read by copying the data read in step S3 to the invalid page retrieved in step S18 to cause data cache. Further, the cache instruction unit 42b effectively updates the flag of the corresponding column 13b of the cache table 13 based on the page address of the cache memory 12 that has been subjected to data caching, and the logical page of the corresponding column 13c is logically updated in page units. The address is recorded, and 0 is recorded as the number of readings of the corresponding column 13d.

  On the other hand, when it is determined in step S18 that there is no invalid page, the cache determination unit 42a determines that there is no space in the cache memory 12. Further, the cache determination unit 42a acquires the number of reads of the physical block 14 in which the data read in step S3 is present from the number-of-reads table 11 (step S20).

  Subsequently, the cache determination unit 42a refers to the column 13d of the cache table 13 to search for a page in the cache memory 12 with the smallest number of reads, that is, with the smallest number of cache hits. By referencing, the address of the physical block 14 of the nonvolatile memory 3 corresponding to the retrieved page is obtained (step S21). Thereafter, the cache determination unit 42a obtains, from the read count table 11, the read count of the physical block 14 of the nonvolatile memory 3 corresponding to the cache data cached in the searched page by using the address obtained in step S21. (Step S22).

  Next, the cache determination unit 42a compares the number of reads corresponding to the data acquired in step S20 with the number of reads corresponding to the cache data acquired in step S22 (step S23), and reads corresponding to the cache data. If the number of times is larger, the cache determination unit 42a determines that the data read in step S3 does not need to be cached, and ends the read cache process.

  On the other hand, if the number of reads corresponding to the cache data is smaller in step S23, the cache determination unit 42a determines that it is better to cache the data read in step S3, and the determination result is used as the cache instruction unit. 42b is notified. Thereby, the process of step S19 is executed by the cache instruction unit 42b. However, in this step S19, the cache instruction unit 42b causes the data retrieved by copying the data read in step S3 to be the data cache for the search page retrieved in step S21. Further, the cache instruction unit 42b effectively updates the flag of the corresponding column 13b of the cache table 13 based on the page address of the cache memory 12 for the search page that has been data cached, and the logical page of the corresponding column 13c. To record the logical address in page units, and record 0 times as the number of reads in the corresponding column 13d.

  As described above, whether or not data is cached is determined by the number of readings in units of physical blocks 14 (obtained in step S20) in the nonvolatile memory 3 of the page to be cached and the cached page. This is executed using the number of readings in units of physical blocks 14 in the nonvolatile memory 3 that is the cache source (step S22).

[Data write operation]
Next, the data write operation will be specifically described with reference to FIG.

  FIG. 15 is a flowchart showing a write operation in the memory card.

  In FIG. 15, when the host controller 51 requests the main controller 4 to write data specifying a logical address, the main controller 4 refers to the columns 10b and 10c of the rewrite count table 10. Among the invalid physical blocks 14, a physical block 14 with a small number of rewrites is searched (step S24). Thereafter, the main control unit 4 controls the memory I / F 7 to erase the data written in the physical block 14 searched in step S24 (step S25).

  Next, the main control unit 4 writes the data transferred from the host device 51 to the buffer 6 via the host I / F 5 to the physical block 14 from which data has been erased in step S25 (step S26). Furthermore, the main control unit 4 effectively changes the flag of the column 10b of the rewrite count table 10 corresponding to the physical block 14, and increments and updates the rewrite count of the column 10c (step S27). .

  Subsequently, the main control unit 4 updates the address conversion table 9 with respect to the physical block 14 in which the data is written in step S26 (step S28), and the main control unit 4 further updates the physical block in the read count table 11. The number of readings of the column 11b corresponding to 14 is changed to 0 (step S29).

  Thereafter, in the main control unit 4, the cache release instruction unit 42c determines whether or not the data written in step S26 (that is, data requested to be written this time) is held as cache data in the cache memory 12. If it is held in the cache memory 12, a cache release process for releasing the cache data is executed (step S30). Specifically, the cache release instruction unit 42c refers to the column 13c of the cache table 13 to search whether or not a logical page included in the data exists, and if it exists, The flag in the page column 13b is changed to invalid. This is because data is written to the cache memory 12 in order to avoid bit errors due to read disturb for data whose read count in the read count table 11 is reset to 0 in step S29 by the data write processing in step S26. This is because there is no need to cache. In other words, in the present embodiment, the cache release instruction unit 42c always releases the cache corresponding to the written data. As a result, effective use of the cache memory 12 can be facilitated, and the use efficiency of the cache memory 12 can be increased.

  Also, in this cache release process, the data requested to be written by the host device 51 is smaller than the capacity of the physical block 14 and 256 Kbytes, and data other than the data from the host device 51 is rewritten to the memory card 1 in order to rewrite the data. The same applies to the case of writing by moving around the inside. In other words, in the present embodiment, not only the data from the host device 51 outside the memory card 1 but also the data to be subjected to the cache release process is moved between the plurality of physical blocks 14 of the nonvolatile memory 3. It is determined whether or not cache release can be performed for all data that includes data and has been written to the physical block 14 of the nonvolatile memory 3. As described above, in the present embodiment, even when data movement is performed between different physical blocks 14, the cache release process is executed, so that the utilization efficiency of the cache memory 12 can be improved more reliably. .

  As described above, in the controller (memory controller) 2 of the present embodiment, when a read operation for reading data from the physical block 14 of the nonvolatile memory 3 designated by the logical address from the host device (external) 51 is requested. In addition, the number comparison unit 40 acquires the number of readings of the physical block 14 from the number-of-reads table 11 and compares the acquired number of readings with a specified number (predetermined threshold) in the upper limit number storage unit 43. Further, when it is determined that the acquired number of readings has reached the specified number, the data movement instruction unit 41 moves to a different physical block 14 different from the physical block 14 of the nonvolatile memory 3 designated by the logical address. On the other hand, it instructs to move the data for which the read operation is requested. As a result, in the controller 2 of this embodiment, even when a NAND type flash memory is used as the nonvolatile memory 3, unlike the conventional example, it is possible to reliably prevent the occurrence of bit errors due to read disturb. In addition, since the controller 2 that can reliably prevent the occurrence of bit errors due to read disturb is used, a highly reliable memory card (nonvolatile storage device) 1 and nonvolatile storage system 50 can be easily obtained. Can be configured.

  In this embodiment, the cache determination unit 42a compares the number of reads shown in step S23, and the number of reads corresponding to the data for which the read operation is requested is stored in the cache data in the cache memory (output memory) 12. When it is determined that the number is larger than the corresponding number of reads, the cache instruction unit 42b causes the cache memory 12 to cache the data requested for the read operation. Thereby, in this embodiment, the data cached in the cache memory 12 can be selected appropriately, and the convenience (data cache function) of the cache memory 12 can be improved. Furthermore, in this embodiment, as shown in step S21, the cache determination unit 42a selects and searches the minimum number of times of reading out of a plurality of times of reading corresponding to each of a plurality of cache data. The data cached in the cache memory 12 can be selected more appropriately, and the convenience of the cache memory 12 can be easily improved.

[Second Embodiment]
FIG. 16 is a block diagram showing specific functional blocks of the main controller of the memory controller according to the second embodiment of the present invention. In the figure, the main difference between this embodiment and the first embodiment is that a function indicating the relationship between the number of rewrites and the number of allowable reads in the nonvolatile memory is set instead of the upper limit number storage unit. The function setting unit is provided in the main control unit, and the cache determination unit determines whether the data cache is necessary by using the function set in the function setting unit. In addition, about the element which is common in the said 1st Embodiment, the same code | symbol is attached | subjected and the duplicate description is abbreviate | omitted.

  That is, as shown in FIG. 16, the main control unit 4 of the present embodiment is provided with a function setting unit 44, and a function indicating the relationship between the number of rewrites and the allowable number of reads in the nonvolatile memory 3 is set. It has come to be. In addition, the cache control unit 42 is provided with the function of the cache determination unit 42 of the first embodiment, and uses a function set in the function setting unit 44 to determine whether or not a data cache is necessary. A determination unit 42a 'is provided.

  In the function setting unit 44, as illustrated in FIG. 17, a function defined by a straight line 60 in which the allowable number of readings monotonously decreases with respect to the number of rewritings is set. This function is determined according to the resistance against the read disturb stress in the physical page 14a unit of the nonvolatile memory 3 with respect to the number of rewrites in the physical block 14 unit of the nonvolatile memory 3, and the number comparison unit 40 The data movement instructing unit 41 reflecting the processing result can be more appropriately performed. This function is also used for the processing operation in the cache determination unit 42a ', and the read cache process reflecting the determination result can be performed more appropriately.

  The cache determination unit 42a ′ determines whether or not there is a page that can be cached in the cache memory 12 by referring to the cache table 13 when a data read operation is requested from the host device 51. The determination result is notified to the cache instruction unit 42b.

  When the cache determination unit 42 a ′ determines that there is no data cacheable page in the cache memory 12, the cache determination unit 42 a ′ acquires the number of reads corresponding to the data requested for the read operation from the read number table 11. Further, the cache determination unit 42a ′ acquires the number of rewrites corresponding to the data for which the read operation is requested from the rewrite number table 10, and acquires the allowable number of reads corresponding to the data for which the read operation is requested. Based on the number of rewrites performed, the function setting unit 44 obtains the remaining allowable read count for the data for which the read operation is requested by subtracting the acquired read count from the obtained allowable read count.

  Further, the cache determination unit 42 a ′ refers to the read count table 11 and the cache table 13 to obtain the read count corresponding to the cache data cached in the cache memory 12. Further, the cache determination unit 42a ′ acquires the number of rewrites corresponding to the cache data from the rewrite number table 10, and sets the allowable number of reads corresponding to the cache data based on the acquired number of rewrites. The remaining allowable read count for the cache data is calculated by subtracting the acquired read count from the calculated allowable read count. Then, the cache determination unit 42a ′ compares the data for which the read operation is requested and the remaining allowable number of read operations for the cache data, determines whether the data cache is necessary, and notifies the cache instruction unit 42b of the determination result. To do.

  In addition, when a plurality of cache data exists in the cache memory 12, the cache determination unit 42a ′ selects the minimum number of readings from among a plurality of readings corresponding to each of the plurality of cache data. It is configured.

  The cache instruction unit 42b indicates that there is a page that can be cached in the cache memory 12 from the cache determination unit 42a ′, or the remaining allowable read count corresponding to the data for which the read operation is requested corresponds to the cache data. When it is notified that the number is less than the remaining allowable number of reads, the cache memory 12 is made to cache the data requested for the read operation.

[Data read operation]
Hereinafter, a data read operation according to the present embodiment will be described with reference to FIG.

  FIG. 18 is a flowchart showing a read operation by the main control unit shown in FIG.

  In FIG. 18, in the main control unit 4 of the present embodiment, after the operations shown in steps S1, S3, and S4 are finished, the number comparison unit 40 is added from the number-of-reads table 11 in step S4. The number of reads of the physical block 14 is acquired and the number of rewrites of the physical block 14 is acquired from the rewrite number table 10 (step S31). Thereafter, the number comparison unit 40 acquires the allowable number of readings from the function setting unit 43 based on the number of rewrites acquired in step S31 (step S32). Specifically, the number comparison unit 40 acquires, for example, the number of rewrites W1 illustrated in FIG. 17 in step S31, and acquires the allowable number of reads r1 obtained from the number of rewrites W1 in step S32.

  Subsequently, the number comparison unit 40 compares the acquired number of readings and the allowable number of readings to determine whether or not the number of readings has reached the allowable number of readings (step S33). If the read count does not reach the allowable read count, the main control unit 4 executes a read cache process for determining whether or not the data read in step S3 is cached in the cache memory 12 (step S3). S6) The read operation is terminated.

  On the other hand, when it is determined in step S33 that the number of readings has reached the allowable number of readings, the main control unit 4 performs the data movement processing by the data movement instruction unit 41 as in the first embodiment. The data read in step S3 is moved to another physical block 14 different from the original physical block 14, and the read operation is terminated.

[Read cache processing]
Next, with reference to FIG. 19, the read cache processing in the present embodiment will be specifically described.

  FIG. 19 is a flowchart showing a specific operation of the read cache process shown in FIG.

  In FIG. 18, in the main control unit 4 of the present embodiment, the cache determination unit 42 a ′ executes the operation shown in step S <b> 18 to determine whether there is a free space (invalid page) in the cache memory 12. When it is determined that there is a free space in the cache memory 12, the process of step S19 is executed by the cache instruction unit 42b as in the first embodiment, and the data read in step S3 is stored in the cache memory 12 as described above. And is registered in the cache table 13.

  On the other hand, if it is determined in step S18 that there is no invalid page, the cache determination unit 42a 'determines that there is no free space in the cache memory 12. Furthermore, the cache determination unit 42a ′ acquires the number of reads of the physical block 14 in which the data read in step S3 exists from the read number table 11, and acquires the number of rewrites of the physical block 14 from the number of rewrites table 10. (Step S34).

  Subsequently, the cache determination unit 42a ′ refers to the column 13d of the cache table 13 to search for a page in the cache memory 12 with the smallest number of reads, that is, with the smallest number of cache hits, and the address conversion table 9 , The address of the physical block 14 of the nonvolatile memory 3 corresponding to the retrieved page is obtained (step S21).

  Next, the cache determination unit 42a ′ uses the address obtained in step S21 to calculate the number of reads of the physical block 14 of the nonvolatile memory 3 corresponding to the cache data cached in the retrieved page. Get from. Further, the cache determination unit 42a ′ uses the address obtained in step S21 to calculate the number of rewrites of the physical block 14 of the nonvolatile memory 3 corresponding to the cache data cached in the retrieved page from the rewrite number table 10. Obtain (step S35).

  Subsequently, for each of the data read in step 3 and the cache data obtained in step 21, the cache determination unit 42a ′ obtains the difference between the allowable read count and the read count, that is, the remaining allowable read count. Compare (step S36). If the remaining allowable read count for the data read in step 3 is greater than the remaining allowable read count for the cache data obtained in step 21, the cache determination unit 42a ′ determines the data read in step 3 as the data. It is determined that there is no need to cache, and the read cache process is terminated.

  On the other hand, in step S36, if the remaining allowable read count for the data read in step 3 is less than the remaining allowable read count for the cache data obtained in step 21, the cache determination unit 42a ′ determines in step S3. It is determined that it is better to cache the read data, and the determination result is notified to the cache instruction unit 42b. Thereby, the process of step S19 is executed by the cache instruction unit 42b. However, in this step S19, the cache instruction unit 42b causes the data retrieved by copying the data read in step S3 to be the data cache for the search page retrieved in step S21. Further, the cache instruction unit 42b effectively updates the flag of the corresponding column 13b of the cache table 13 based on the page address of the cache memory 12 for the search page that has been data cached, and the logical page of the corresponding column 13c. To record the logical address in page units, and record 0 times as the number of reads in the corresponding column 13d.

  Specifically, in step S34, the cache determination unit 42a ′ obtains the number of rewrites and the allowable number of reads corresponding to the data read in step S3 from, for example, the number of rewrites W1 and the number of rewrites W1 shown in FIG. The permissible read count r1 is acquired. Further, the cache determination unit 42a ′ obtains the read count r1 ′ corresponding to the data from the read count table 11, calculates the difference value between the allowable read count r1 and the read count r1 ′, and reads it in step S3. The remaining allowable number of readings for the output data is obtained.

  Furthermore, in step S35, the cache determination unit 42a ′, as the number of rewrites and the allowable number of reads corresponding to the cache data searched in step S21, for example, the number of rewrites W2 shown in FIG. The number of times r2 is acquired. Further, the cache determination unit 42a ′ acquires the read count r2 ′ corresponding to the cache data from the read count table 11, calculates the difference between the allowable read count r2 and the read count r2 ′, and in step S21. The number of remaining allowable reads for the retrieved cache data is obtained. In step S 36, the cache determination unit 42 a ′ compares the remaining allowable read counts for the data read in step S 3 and the cache data searched in step S 21.

  With the above configuration, the present embodiment can achieve the same operational effects as those of the first embodiment. Further, in the present embodiment, the number comparison unit 40 obtains the number of rewrites of the physical block 14 for which the data read operation is requested from the rewrite number table 10, and based on the obtained number of rewrites, permits reading from the function setting unit 44. The number of times is acquired and compared with the number of reads of the physical block 14. Further, the data movement instruction unit 41 moves the data requested for the read operation to another physical block 14 when the read count reaches the allowable read count. As a result, in this embodiment, it is possible to prevent the occurrence of bit errors due to read disturb more reliably than in the first embodiment.

  That is, in the nonvolatile memory 3, the occurrence of a bit error due to read disturb greatly depends on the number of rewrites. In other words, in the nonvolatile memory 3, the physical block 14 with a smaller number of rewrites has a better read disturb characteristic, and the read disturb characteristic tends to decrease as the number of rewrites increases. Therefore, as shown in steps S31 to S33, it is more appropriate to determine whether to move data in order to prevent the bit error by using both the number of times of reading and the number of times of rewriting. Can do.

  Specifically, in the present embodiment, for example, when the number of rewrites is 100, the allowable number of reads of 10000000 is set as a threshold, and when the number of rewrites reaches 1000000, the number of allowable reads is set as a threshold of 1000. An appropriate threshold value corresponding to the use state of the block 14 is used for the comparison process in the number comparison unit 40, so that a more appropriate determination can be made.

  Further, in the present embodiment, the cache determination unit 42a ′ compares the remaining allowable read counts for the data for which the read operation is requested and the cache data, so that it depends on the read disturb stress level of the nonvolatile memory 3. Therefore, it is possible to select appropriate cache data, and it is possible to more reliably prevent occurrence of bit errors due to read disturb.

  The above embodiments are all illustrative and not restrictive. The technical scope of the present invention is defined by the claims, and all modifications within the scope equivalent to the configurations described therein are also included in the technical scope of the present invention.

  For example, in the above description, the case where the present invention is applied to a memory card (nonvolatile memory device) has been described. However, the memory controller of the present invention is not limited to this, and other nonvolatile memory such as a flash disk is used. The present invention can also be applied to a storage device and a nonvolatile storage system including the storage device.

  Further, in the above description, when the number comparison unit determines that the number of readings for the data for which a reading operation is requested has reached the specified number (predetermined threshold) or the allowable number of readings, a data movement instruction A configuration has been described in which the unit instructs to move the data to another physical block of the nonvolatile memory. However, the present invention provides a read count table for recording the read count in units of physical pages as the read count of the corresponding physical block for the physical pages included in each physical block of the nonvolatile memory, and the main control unit However, there is no limitation as long as it refers to the read count table and restricts the data read operation to the nonvolatile memory.

  However, when data is moved to another physical block as in each of the above embodiments, it is possible to prevent the data retention in the nonvolatile memory from being reduced, and read disturb This is preferable in that the occurrence of bit errors can be surely prevented.

  Further, in the above description, the case where the number comparison unit compares the number of readings with a predetermined threshold value or the allowable number of readings after reading data from the physical page to be read has been described. It is sufficient that the above comparison is performed when a read operation is requested, and the comparison may be executed before the data read operation.

  In the above description, a controller (memory controller) having a cache memory (output memory) has been described. However, the memory controller of the present invention is not limited to this, and a memory controller in which no output memory is installed is used. Can also be applied.

  However, as in the above embodiments, when the output memory is installed and the data can be cached, the data is read from the non-volatile memory when a data read operation is requested from the outside. Therefore, it is possible to output the data to the host device (external), and it is preferable in that deterioration due to read disturb in the nonvolatile memory can be efficiently suppressed.

  In the above description, the case where a NAND type flash memory is used as the nonvolatile memory has been described. However, the present invention is not limited to this, and other types of flash memory such as a MONOS type and an AND type are used. It can also be applied to.

  The present invention relates to a memory controller that can reliably prevent bit errors caused by read disturb in a nonvolatile memory, a nonvolatile memory device having a nonvolatile memory with improved data reliability, and nonvolatile memory Useful for systems.

It is a block diagram which shows the principal part structure of the memory card using the memory controller concerning the 1st Embodiment of this invention, and a non-volatile storage system. It is a block diagram which shows the specific functional block of the main control part shown in FIG. It is a figure which shows the structure of the physical block of the non-volatile memory shown in FIG. It is a figure which shows the structure of the address conversion table shown in FIG. It is a figure which shows the structure of the rewrite frequency table shown in FIG. It is a figure which shows the structure of the reading frequency table shown in FIG. It is a figure which shows the structure of the cache table shown in FIG. It is a flowchart which shows read-out operation | movement with the said memory card. It is a flowchart which shows the specific operation | movement of the data movement process shown in FIG. (A), (b), (c), and (d) are specific states of the read count table, the rewrite count table, the address conversion table, and the nonvolatile memory, respectively, before the data movement process is performed. It is a figure explaining. (A), (b), (c), and (d) are specific examples of the read count table, the rewrite count table, the address conversion table, and the nonvolatile memory after the operation of step S9 in FIG. 9 is performed. It is a figure explaining each state. (A), (b), (c), and (d) are specific examples of the read count table, the rewrite count table, the address conversion table, and the nonvolatile memory before the operation of step S15 in FIG. 9 is performed. It is a figure explaining a state, respectively. (A), (b), (c), and (d) are specific examples of the read count table, the rewrite count table, the address conversion table, and the nonvolatile memory after the operation of step S17 in FIG. 9 is performed. It is a figure explaining each state. FIG. 9 is a flowchart showing a specific operation of read cache processing shown in FIG. 8. FIG. It is a flowchart which shows the write-in operation | movement with the said memory card. It is a block diagram which shows the concrete functional block of the main control part of the memory controller concerning the 2nd Embodiment of this invention. It is a graph which shows the specific example of the correlation between the frequency | count of rewriting in the said non-volatile memory, and the frequency | count of permissible reading. 17 is a flowchart showing a read operation by the main control unit shown in FIG. 16. 19 is a flowchart showing a specific operation of the read cache process shown in FIG. 18.

Explanation of symbols

1 Memory card 2 Controller (memory controller)
Reference Signs List 3 Nonvolatile memory 4 Main control unit 40 Number comparison unit 41 Data bit error instruction unit 42a, 42a 'Cache determination unit 42b Cache instruction unit 42c Cache release instruction unit (output memory release instruction unit)
43 Function Setting Unit 9 Address Conversion Table 10 Rewrite Count Table 11 Read Count Table 12 Cache Memory (Output Memory)
13 Cache table (output table)
14 Physical Block 14a Physical Page 50 Nonvolatile Storage System 51 Host Device

Claims (13)

A memory controller for writing and reading data specifying a logical address from the outside to a nonvolatile memory having a plurality of physical blocks,
An address conversion table for converting the logical address and the address of the physical block;
The logical address is input, and referring to the address conversion table, a main control unit that controls a data write operation and a read operation with respect to the nonvolatile memory,
For a plurality of physical pages included in each of the plurality of physical blocks, there is provided a read count table for recording the read count in units of physical pages as the read count of the corresponding physical block,
The main control unit refers to the read count table and restricts a data read operation to the nonvolatile memory.
This is a memory controller. The data stored in the physical block of the non-volatile memory is configured to be cacheable, and the data is read from the non-volatile memory when the main control unit is requested to read data from the outside. Output memory to output the data to the outside without,
The memory controller according to claim 1, further comprising an output table for managing a read count of cache data cached in the output memory. When the main control unit is requested to write data to the physical block of the nonvolatile memory, the main control unit determines whether the data is cached in the output memory by referring to the output table. And an output memory release instruction unit that instructs the output memory to release the cache of the data when it is determined that the data is cached. The described memory controller. The output memory release instruction unit refers to the output table as to whether or not the data is cached in the output memory when data is moved between different physical blocks of the nonvolatile memory. 4. The memory controller according to claim 3, wherein when the data is determined and when it is determined that the data is cached, the output memory is instructed to release the data cache. When a data read operation is requested from the outside, the main control unit obtains the read count corresponding to the data requested for the read operation from the read count table, and also outputs the output table and the read count. By referring to the table, the number of reads corresponding to the cache data cached in the output memory is obtained and compared with the number of reads corresponding to the data for which the read operation is requested. A cache determination unit for determining NO,
When the cache determination unit determines that the number of reads corresponding to the data requested for the read operation is greater than the number of reads corresponding to the cache data, the data requested for the read operation is output as the output The memory controller according to claim 2, further comprising a cache instruction unit that causes the memory to cache. 6. The cache determination unit according to claim 5, wherein when there are a plurality of cache data in the output memory, the cache determination unit selects a minimum number of read times out of a plurality of read times corresponding to the plurality of cache data. Memory controller. When the main control unit is requested to perform a read operation for reading data from the physical block of the nonvolatile memory specified by an external logical address, the main control unit acquires the read count of the physical block from the read count table. A number comparison unit that compares the acquired number of readings with a predetermined threshold;
When it is determined by the number comparison unit that the acquired number of readings has reached the predetermined threshold, the physical block different from the physical block of the nonvolatile memory specified by the logical address The memory controller according to claim 1, further comprising: a data movement instructing unit that instructs to move data for which the read operation is requested. A rewrite count table for recording the number of erases of the physical block as the rewrite count of the corresponding physical block;
In the main control unit, a function setting unit in which a function indicating a relationship between the number of rewrites and the allowable number of reads in the nonvolatile memory is set;
When a data read operation is requested from the outside, the read count corresponding to the data requested for the read operation is obtained from the read count table, and the rewrite count corresponding to the data requested for the read operation is obtained. Obtained from the function setting unit based on the obtained number of rewrites, and obtained the number of readings obtained from the obtained number of permitted readings, obtained from the rewrite number table and corresponding to the data for which the read operation is requested. By subtracting, the remaining allowable number of reads for the data for which the read operation is requested is calculated, and by referring to the output table and the read number table, it corresponds to the cache data cached in the output memory. The number of readings to be performed The rewrite count corresponding to the cache data is obtained from the rewrite count table, and the allowable read count corresponding to the cache data is obtained from the function setting unit based on the obtained rewrite count, and obtained from the obtained allowable read count. By subtracting the read count, the remaining allowable read count for the cache data is calculated and compared with the remaining allowable read count for the data for which the read operation is requested to determine whether the data cache is necessary. A cache determination unit for determining;
When the remaining allowable read count corresponding to the data for which the read operation is requested by the cache determination unit is smaller than the remaining allowable read count corresponding to the cache data, the data for which the read operation is requested is stored in the output memory. The memory controller according to any one of claims 2 to 4, further comprising a cache instruction unit that caches the memory controller. The cache determination unit selects a minimum number of read times from among a plurality of read times corresponding to the plurality of cache data when a plurality of cache data exists in the output memory. Memory controller. A rewrite count table for recording the number of erases of the physical block as the rewrite count of the corresponding physical block;
In the main control unit, a function setting unit in which a function indicating a relationship between the number of rewrites and the allowable number of reads in the nonvolatile memory is set;
When a read operation for reading data from a physical block of the nonvolatile memory designated by an external logical address is requested, the physical block read count is acquired from the read count table and the physical block is rewritten. The number comparison unit for obtaining the number of times from the rewrite number table, obtaining the allowable read number from the function setting unit based on the obtained number of rewrites, and comparing the acquired read number and the acquired allowable read number;
When it is determined by the number comparison unit that the acquired number of readings has reached the allowable number of readings, a physical block different from the physical block of the nonvolatile memory specified by the logical address 10. The memory controller according to claim 1, further comprising a data movement instruction unit that instructs to move data for which the read operation is requested. 10. The memory controller according to claim 8, wherein in the function, the allowable number of readings monotonously decreases with respect to the number of rewritings. A non-volatile storage device comprising: a non-volatile memory having a plurality of physical blocks; and the memory controller according to claim 1. A non-volatile memory device having a non-volatile memory having a plurality of physical blocks, a non-volatile memory device provided with a memory controller for writing and reading data specifying a logical address from the outside, and the non-volatile memory device A non-volatile storage system including a host device that performs an access instruction specifying a logical address.
The memory controller according to any one of claims 1 to 11 is used as the memory controller.
A non-volatile storage system.

Images