JP2019160197A - Storage device, control program and control method - Google Patents

Abstract

To improve the durability of a semiconductor storage.SOLUTION: A storage device comprises: an error correction processing part 21 that, when detecting an error in data read from a semiconductor storage 101, performs error correction and outputs the number of corrected errors; and a setting unit 12 that, when from among a plurality of unit areas included in the semiconductor storage 101, the sum of a first error count detected in the first unit area and an error count detected in a second unit area adjacent to the first unit area reaches or exceeds a threshold, sets data in the first unit area not to be taken out of a cache memory 102.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a storage apparatus, a control program, and a control method.

  2. Description of the Related Art In recent years, a storage device has been realized that can store large volumes of data safely and for a long time, mainly for reading, while being able to read at high speed when necessary, and is used, for example, for long-term storage of video data. Such a storage device may be called archive storage.

  As a semiconductor device for storing data in such a storage device, a NAND flash memory which is a low-capacity nonvolatile memory having a large capacity and capable of reading and writing at a relatively high speed is often used.

  In addition, as a NAND flash memory, a device using a recording method called MLC (Multi Level Cell) capable of storing multiple values in one memory cell is increasingly used.

  FIG. 8 is a diagram showing a hardware configuration of a conventional storage system.

  The storage system 500 includes a storage device 510 and a host 501. The host 501 reads / writes data from / to the storage apparatus 510. For example, the host 501 makes a data request by designating a data address to the storage apparatus 510.

  The storage device 510 includes a memory controller 502, a NAND flash memory 503, and a DRAM (Dynamic Random Access Memory) 504.

  The NAND flash memory 503 is a non-volatile storage device that stores data, and has a configuration similar to, for example, a general SSD (Solid State Drive).

  The memory controller 502 controls reading / writing of data with respect to the NAND flash memory 503 and the DRAM 504.

  The DRAM 504 is a semiconductor memory that stores data, and can perform data access at a higher speed than the NAND flash memory 503. In the storage system 500, the DRAM 504 functions as a cache memory that temporarily stores data. Hereinafter, the DRAM 504 may be referred to as a cache memory 504.

  The data read from the NAND flash memory 503 is temporarily stored in the cache memory 504, and if a cache search hits at the time of a data request from the host 501, the cache memory 504 reads the data to realize high-speed access. To do.

  The capacity of the cache memory 504 is generally smaller than the capacity of the NAND flash memory 503, and the entire data of the NAND flash memory 503 cannot be cached. Therefore, data is evicted from the cache memory 504 (also referred to as cache-out) according to a certain rule, and the next data is cached.

  In the NAND flash memory 503, due to the structure as a device, there is a life (durability limit) in which data read failure or data corruption occurs when data is read and written multiple times.

  In particular, the NAND flash memory 503 using the MLC has a plurality of values in one memory cell, so that it becomes difficult to determine the value at an early stage, so the durability is low and the probability of an error is high. Further, such a phenomenon has become remarkable due to miniaturization, and an error correction function represented by ECC (Error Collection Code) encoding is essential for the memory controller 502.

  In particular, an example of an error pattern in the recent NAND flash memory 503 is read disturb. Until now, writing has been the dominant factor for shortening the lifetime, but it has been found that the memory cell is burdened even during reading. Further, not only the data access target page but also the adjacent page (peripheral address) is affected by address control inside the memory.

JP 2010-92528 A JP-A-8-279295 JP 2009-37317 A

  In conventional storage systems, SLC (Single Level Cell) is often used as a storage medium, and a deterioration problem called read disturb in the NAND flash memory 503 is rarely realized.

  Read disturb is a phenomenon in which when a NAND flash memory is read, a digital value of a neighboring cell of a read target cell is changed by repeatedly reading a page in the same block. As a result, the data in the neighboring cells of the read target cell cannot be read correctly.

  However, in recent years, MLC has been frequently used to improve the capacity density of storage elements, and the influence of read disturb cannot be ignored.

In an LRU (Least Recently Used) method that is generally used as a management method for the cache memory 504, data to be evicted from the DRAM 504 is determined based on the access frequency (time elapse) from the host 501.
In other words, in the LRU method, when the cache becomes full, the oldest data in the cache memory is set as a target for removal (deletion) from the cache memory 504. In other words, the passage of time for access is managed by the generation number, and the necessity of the cache is determined.

  In such an LRU method, the overall number of reads of the flash memory can be reduced, but deterioration of the NAND flash memory 503 at the time of reading is not taken into consideration.

  For example, a page (address) that is accessed many times at intervals but with a low local frequency is accessed in the LRU method as a cache eviction target. As a result, there is a problem that data access to the NAND flash memory 503 occurs and the deterioration of the NAND flash memory 503 progresses.

  Further, in the LRU method, cache eviction control is performed only for a specific address where a cache hit occurs, so pages around the address where the cache hit occurs are not considered. Therefore, consideration is not given to the protection of peripheral addresses and read caching in read disturb, and there is a problem that the NAND flash memory 503 deteriorates due to these.

  In one aspect, an object of the present invention is to improve the durability of a semiconductor memory device.

  For this reason, the storage device performs error correction when an error is detected in data read from the semiconductor memory device, and outputs an error correction processing unit that outputs the number of corrected errors, and a plurality of units provided in the semiconductor memory device When the total of the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area is greater than or equal to the first threshold value among the areas. And a setting unit for setting the data of the first unit area to be excluded from the cache memory.

  According to one embodiment, the durability of the semiconductor memory device can be improved.

1 is a diagram illustrating a configuration of a storage system including a storage device as an example of an embodiment. It is a figure which illustrates the cache management information in the storage system as an example of embodiment. (A), (b) is a figure for demonstrating the proximity page in the storage system as an example of embodiment. 3 is a diagram for explaining a priority order for determining a cache eviction target in a storage system as an example of an embodiment; FIG. It is a figure for demonstrating the determination method of the cache eviction target based on the prediction number of CE in the storage system of embodiment. 4 is a flowchart for explaining a read request processing method in a storage system as an example of an embodiment; It is a flowchart explaining the detail of the selection method of the replacement target of step A7 of the flowchart shown in FIG. It is a figure which shows the hardware constitutions of the conventional storage system.

  Hereinafter, embodiments of the storage apparatus, a control program, and a control method will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment. Each figure is not intended to include only the components shown in the figure, and may include other functions.

(A) Configuration FIG. 1 is a diagram illustrating a configuration of a storage system 1 including a storage apparatus 100 as an example of an embodiment.

  As shown in FIG. 1, the storage system 1 includes a host 200 such as a PC (Personal Computer) and a storage apparatus 100. The host 200 and the storage apparatus 100 are connected via an interface such as a SAS (Serial Attached Small Computer System Interface), an FC (Fibre Channel), or a network.

  The host 200 includes a processor such as a CPU (Central Processing Unit) (not shown), and implements various functions by executing applications using this processor.

  As will be described later, the storage device 100 includes a plurality of types of storage devices (in the example shown in FIG. 1, a NAND flash memory 101 and a DRAM 102), and provides storage areas of these storage devices to the host 200. The storage area provided by the hierarchical storage apparatus 1 stores data generated by executing an application in the host 200, data used for executing the application, and the like.

  IO access occurs when the host 200 writes or reads data to or from the storage area of the storage system 1.

  As shown in FIG. 1, the storage apparatus 100 includes a memory controller 110, a NAND flash memory 101, and a DRAM 102.

  The NAND flash memory 101 is an example of a storage device that stores various data, programs, and the like, and is a flash memory (semiconductor storage device) of a nonvolatile storage element. The NAND flash memory 101 may be an MLC.

  The DRAM 102 (second storage device) is a semiconductor memory and is an example of a storage device having a performance (for example, higher speed) different from that of the NAND flash memory 101. The DRAM 102 is used as a cache memory. Hereinafter, the DRAM 102 may be referred to as the cache memory 102.

  In the present embodiment, the NAND flash memory 101 and the DRAM 102 are exemplified as different storage devices, but the present invention is not limited to this. Instead of the NAND flash memory 101 and the cache memory 102, various storage devices having a performance difference (for example, a read / write speed difference) may be used.

  The memory controller 110 performs various accesses to the NAND flash memory 101 and the DRAM 102 in response to a data access request from the host 200. For example, when a data request (read) is made from the host 200, the memory controller 110 reads the data requested from the NAND flash memory 101 or the DRAM 102, and responds the read actual data to the host 200 (data response).

  The memory controller 110 includes a cache management unit 10, a data access control unit 20, and an error correction processing unit 21.

  The error correction processing unit 21 detects a code error (error) for data read from the NAND flash memory 101, and performs error correction (error correction) when an error is detected. Note that error detection and error correction can be realized by various known methods, and description thereof will be omitted. The error correction processing unit 21 may be realized by an error correction circuit, for example.

  Further, the error correction processing unit 21 outputs (notifies) the number of errors (CE number) for which error correction has been performed to the cache management unit 10. CE is an abbreviation for Correctable Error.

  The data access control unit 20 processes a data access request input from the host 200. For example, when a read request (data request) is input from the host 200, the data access control unit 20 performs a cache search with respect to the cache management unit 10 described later based on the data address input with the data request. input. The data access control unit 20 issues a data request to the NAND flash memory 101 or the DRAM 102 based on the search result returned from the cache management unit 10 for this cache search.

  Specifically, when the cache search results in a cache hit, that is, when a result response indicating that the requested data is in the cache memory 102 is received from the cache management unit 10, the data access control unit 20 A data request is made to the cache memory 102.

  Thus, the data read from the cache memory 102 (cache read data) is returned to the host 200 as actual data.

  On the other hand, if the cache search results in a cache miss, i.e., if the cache management unit 10 returns a result response indicating that the requested data is not in the cache memory 102, the data access control unit 20 uses the NAND flash memory. A data request is made to 101.

  Data read from the NAND flash memory 101 (NAND read data) is subjected to error detection by the error correction processing unit 21, and then returned to the host 200 as actual data. When an error is detected by the error correction processing unit 21, the error correction processing unit 21 performs error correction and then returns a response to the host 200 as actual data.

  Further, the data read from the NAND flash memory 101 is subjected to error detection by the error correction processing unit 21, and is subjected to error correction as necessary, and then stored in the cache memory 102 (data writing for cache). ).

  Further, the data access control unit 20 registers the cache in the cache management unit 10 by notifying the cache management unit 10 of the data address of the data request made to the NAND flash memory 101.

  The cache management unit 10 manages the cache memory 102. As illustrated in FIG. 1, the cache management unit 10 includes an information management unit 11 and a cache access control unit 12.

  The information management unit 11 manages information for managing the cache memory 102. Specifically, the information management unit 11 manages the cache management information 111a and the cache history information 111b. Each piece of information constituting the cache management information 111a and the cache history information 111b is stored, for example, in a memory (storage unit) (not shown) provided in the memory controller 110.

  FIG. 2 is a diagram illustrating cache management information 111a in the storage system 1 as an example of the embodiment.

  The cache management information 111a manages data (pages) stored in the cache memory 102. The cache management information 111a includes a NAND address, a generation number, a corresponding CE number, a neighboring CE number, a history CE number, and flags A to D (for each data range area (unit area) called a page in the NAND flash memory 101). FLAG_A to FLAG_D) are associated with each other. That is, in the cache management information 111a, an entry is configured for each page of the NAND flash memory 101. Hereinafter, a page corresponding to each entry may be referred to as a corresponding page.

  The NAND address represents the physical position of the corresponding page in the NAND flash memory 101.

  The generation number is information indicating the passage of time for the data access made to the page. For example, at the time of registration (cache registration) in the cache memory 102 and update of the cache management information 111a, the generation number corresponding to the page on which data access has been performed is updated.

  The generation number is updated to a value larger than the generation number of any other page, for example, when registering in the cache memory 102 and updating the cache management information 111a.

  In the present embodiment, it is assumed that the smaller the generation number value, the more recent (previous) access indicates the older page.

  The number of corresponding CEs is the number of CEs detected in the corresponding page, and the number of CEs detected by the error correction processing unit 21 when reading data from the NAND flash memory 101 is registered in units of pages.

  The number of CEs represents, for example, the number of bits per page of the NAND flash memory 101 corrected by the error correction processing unit 21. In general, the page size of the NAND flash memory 101 is 4096 bytes (4 KB). Although depending on the mounting method of the error correction processing unit 21, for example, an error correction method using a BCH code has a correction capability of around 50 bits per 4096 bits. For this reason, the number of CEs per page may be stored as a number of CEs from 0 to 50 bits.

  If a page with a large number of CEs is read again, deterioration may progress and the number of errors may increase. Therefore, in this storage system 1, the NAND flash memory 101 is protected by leaving a page with a large number of CEs as a protection target and leaving the data in the cache memory 102.

  In the number of corresponding CEs, the number of CEs when reading from the NAND flash memory 101 at the time of no hit in the cache memory 102 is registered in units of pages.

  The number of adjacent CEs is the number of CEs detected on adjacent pages that are adjacent (close to each other) sharing the address signal, which are pages around the corresponding page.

  The read disturb affects not only the page (the corresponding page) that is actually read, but also the peripheral pages that share the address signal. Therefore, in the present storage system 1, the total number of CEs of a plurality of pages including the corresponding page and the adjacent page adjacent to the corresponding page is compared with a predetermined threshold value. If the total number of CEs is larger than a predetermined threshold value, control is performed so that those adjacent pages are regarded as the same page as the corresponding page and are protected, and the data of those pages is left in the cache memory 102.

  3A and 3B are diagrams for explaining adjacent pages in the storage system 1 as an example of the embodiment. 3A is a diagram illustrating the positional relationship between the corresponding page and the adjacent page on the NAND flash memory 101, and FIG. 3B is a diagram illustrating the positional relationship between the corresponding page and the adjacent page in a table.

  In FIGS. 3A and 3B, the corresponding page is indicated by the symbol A, and the adjacent pages are indicated by the symbols B, C, D, and E.

  The adjacent page refers to a page that is physically close to the corresponding page. However, the definition of the adjacent page changes depending on the physical arrangement inside the LSI (Large Scale Integration) of the NAND flash memory 101 and the address line control method. Therefore, the proximity page may be defined by obtaining data from the memory device to be controlled or information from the manufacturer.

  In the example shown in FIGS. 3A and 3B, for simplification, it is assumed that address = page address and logical arrangement = physical arrangement.

  In the example shown in FIGS. 3A and 3B, it is assumed that the row address of the read target page (corresponding page) A is “RA” and the column address is “CA”.

  For example, the address of the adjacent page B is “RA-1” for the Row address and “CA” for the Column address, and the address (NAND address) of the adjacent page B on the NAND flash memory 101 is obtained from the Row address and the Column address. Can do. Similarly, for example, the address of the adjacent page C has the Row address “RA” and the Column address “CA-1”, and the NAND address of the adjacent page C can be obtained from the Row address and the Column address.

  The number of adjacent CEs can be acquired by referring to the cache management information 111a. For example, the number of adjacent CEs for page A can be calculated by summing the number of corresponding CEs for page B, the number of corresponding CEs for page C, the number of corresponding CEs for page D, and the number of corresponding CEs for page E.

  In the example shown in FIGS. 3A and 3B, “1” included in “−1” or “+1” in the Row address and the Column address represents an address for one page.

  Whether or not the number of adjacent CEs is registered in the information management unit 11 can be determined by searching a NAND address registered in the cache management unit 10. For example, if the NAND address of page B is not registered in the information management unit 11, the number of corresponding CEs of page B may be set to zero.

  The number of neighboring CEs is acquired from the number of corresponding CEs registered in the cache management information 111a for neighboring pages.

  The history CE number is the CE number of the cache history page. A cache history page is a page that has been cached in the past, although no actual data remains in the cache memory 102. In the history CE number, the page number of such a cache history page and the CE number (history CE number) when the page is read are recorded. That is, the history CE number corresponds to the number of errors detected in the past in the corresponding page.

  For example, when the same page is read a plurality of times, the number of CEs read at the previous time is stored as the number of history CEs, and the number of CEs read this time is stored as the number of corresponding CEs.

  The history CE number is referenced from the CE number registered in cache history information 111b described later.

  In FLAG_A, FLAG_B, FLAG_C, and FLAG_D, determination results that are determined when the cache access control unit 12 described later selects a flag to be replaced on the cache memory 102 (see the flowchart shown in FIG. 7) are recorded. The

  In FLAG_A, “0” is set when the number of corresponding CEs is smaller than the reference value A, and “1” is set when the number of corresponding CEs is greater than or equal to the reference value A.

  FLAG_B is set to “0” when the generation number is smaller (older) than the reference value B (second threshold), and “1” when the generation number is greater than or equal to the reference value B.

  In FLAG_C, “0” is set when the number of corresponding CEs is smaller than the reference value C (third threshold) compared with the history CE number, and the corresponding CE number is compared with the history CE number. In the above case, “1” is set.

  FLAG_D is “0” when the total number of CEs of the corresponding page and adjacent pages is smaller than the reference value D (first threshold), and the total number of CEs of the corresponding page and adjacent pages is greater than or equal to the reference value D. In this case, “1” is set.

  The storage of the determination result in FLAG_A, FLAG_B, FLAG_C, and FLAG_D will be described later in the description of the flowchart of FIG.

  In the cache management information 111a, the latest state of each page is recorded as an entry.

  The cache history information 111b manages data (pages) stored in the cache memory 102 in the past. The cache history information 111b has the same configuration as the cache management information 111a, and when any entry of the cache management information 111a is updated, the entry before the update is recorded in the cache history information 111b. That is, the cache history information 111b functions as a history of the cache management information 111a.

  For example, when a read request is input from the host 200 and a read access to the NAND flash memory 101 occurs, the entry of the corresponding page in the cache management information 111a is updated. The old entry updated in the cache management information 111a is recorded in the cache history information 111b.

  Hereinafter, the cache management information 111a and the cache history information 111b may be collectively referred to as cache information 111. The information management unit 11 manages the cache information 111.

  When a cache search request is input from the cache access control unit 12, the cache management unit 10 instructs the cache management information 111a to perform a search in response to the cache search request, so that the read target data is stored in the cache memory. 102.

  For example, when a read request with a data address is input from the host 200, the cache access control unit 12 inputs a cache search request with a data address to the information management unit 11. Based on the input data address, the information management unit 11 searches each NAND address of the cache management information 111a to determine whether the read target data is stored in the cache memory 102.

  The information management unit 11 returns a search result (cache hit or cache miss) to the cache access control unit 12, and the cache access control unit 12 returns a response from the information management unit 11 to the data access control unit 20 (result response). )

  In addition, when an instruction to register, update, or delete data for the cache information (cache management information 111a) is input from the cache access control unit 12, the information management unit 11 responds to the cache information 111 in response to the instruction. Register, update, and delete data.

  The cache access control unit 12 controls data access to the cache memory 102.

  For example, when a read data request is input from the host 200 to the data access control unit 20, the data access control unit 20 requests the cache access control unit 12 to perform a cache search.

  For example, when a read request with a data address is input from the host 200, the cache access control unit 12 inputs a cache search request with a data address to the information management unit 11.

  Further, the cache access control unit 12 responds to the data access control unit 20 with the search result returned from the information management unit 11.

  The cache access control unit 12 controls the memory controller 110 in general. For example, the cache access control unit 12 performs a cache search in response to a data request from the host 200. If the requested data does not exist in the cache memory 102 (no cache hit), the cache access control unit 12 causes the NAND flash memory 101 to read data.

  Further, when the data read from the NAND flash memory 101 is written to the cache memory 102, the cache access control unit 12 instructs the information management unit 11 to register data for the cache information (cache management information 111a). .

  When the data on the cache memory 102 is replaced and the data is deleted (cached out) from the cache memory 102, the cache access control unit 12 sends the page of the corresponding data to the information management unit 11 as cache management information 111a. Instruct to delete from. Further, when the data arrangement on the cache memory 102 is changed, the cache access control unit 12 instructs the information management unit 11 to change the page of the corresponding data in the cache management information 111a.

  The cache access control unit 12 also manages data to be cached in the cache memory 102.

  The capacity of the cache memory 102 is smaller than the capacity of the NAND flash memory 101, and all data in the NAND flash memory 101 cannot be cached in the cache memory 102.

  Therefore, the cache access control unit 12 performs data eviction processing from the cache memory 102 according to a certain rule, and caches the next data.

  In this storage system 1, when a read request for data is received from the host 200, if there is no free space in the cache memory 102 (cache full), the cache access control unit 12 performs the following processing.

  That is, the cache access control unit 12 sets the priority order for the pages of the NAND flash memory 101 for the purpose of protecting the NAND flash memory 101, and determines the data to be ejected from the cache memory 102 (cache eviction target).

  FIG. 4 is a diagram for explaining a priority order for determining a cache eviction target in the storage system 1 as an example of the embodiment.

  The cache access control unit 12 determines a page to be cached according to the priority illustrated in FIG.

  FIG. 4 shows an example in which priorities of 1 to 8 are set based on the number of CEs and generation numbers in a page. The smaller the priority value, the higher the priority for cache eviction.

  In this storage system 1, since a page with a large number of CEs in the NAND flash memory 101 is considered to be an area that has deteriorated, data access to the area is reduced in order to protect the area. To control. That is, by controlling the data (page data) in the protection target area in the NAND flash memory 101 to remain in the cache memory 102, data access to the protection target area in the NAND flash memory 101 is reduced.

  For this reason, page data in an area that is unlikely to be protected in the NAND flash memory 101 is preferentially selected as a cache eviction area.

  For example, the number of CEs of a page is compared with a predetermined reference value (threshold value) A, and pages with a CE number equal to or greater than this reference value A are left out of the cache memory 102 as a target of cache eviction, and the CE number Priority is given to small pages as cache eviction targets. That is, a page with a large number of CEs is left as a protection target in the cache memory 102, and a page with a small number of CEs is given priority as a cache eviction target.

  Further, the generation number of the page is compared with a predetermined reference value (second threshold) B, and a page whose generation number is newer than this reference value B is left out of the cache memory 102 as a cache eviction target, and the generation number is the reference value. A page older than B is given priority as a cache eviction target. That is, a page having a large generation number and a short period in which there is no access since the last access is left in the cache memory 102 as a protection target. Then, a page having a small generation number and a long period of no access since the last access is given priority as a cache eviction target.

  Further, from the viewpoint of the number of CEs, the cache memory 102 excludes pages having an increase in the number of CEs equal to or greater than a predetermined reference value (third threshold) C as compared to the past (history) number of CEs on the same page. To leave. Then, a page whose number of CE increases is less than a predetermined reference value (third threshold) C is preferentially set as a cache eviction target.

  In addition, the cache access control unit 12 leaves a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is equal to or greater than a predetermined reference value (first threshold) D in the cache memory 102 as a cache eviction target. Then, a page whose sum of the number of corresponding CEs and the number of adjacent CEs is smaller than a predetermined reference value (fourth reference value) D is preferentially set as a cache eviction target.

  When the sum of the number of corresponding CEs and the number of adjacent CEs is equal to or greater than a predetermined reference value (first threshold value) D, the number of CEs of each page adjacent to the corresponding page is also large. It is considered that the area corresponding to the page has also deteriorated. Therefore, in the present storage system 1, such a page is set as a protection target, not as a cache eviction target, and data is left in the cache memory 102, thereby protecting the NAND flash memory 101 from access to the area.

  Further, the cache access control unit 12 refers to the cache management information 111a and the cache history information 111b, and reads the next time (after the generation number difference) from the generation number, the corresponding CE number, and the history CE number of the corresponding page. The number of CEs to perform is extrapolated. Then, when the estimated value of the number of CEs exceeds the correctable number of the error correction processing unit 21, the cache access control unit 12 sets the corresponding page as a target to be protected in the cache memory 102.

  That is, the cache access control unit 12 predicts the number of CEs at the time of the next read (predicted CE number) based on the past number of CEs, and uses this predicted CE number to determine the cache eviction target.

  FIG. 5 is a diagram for explaining a cache eviction target determination method based on the predicted number of CEs in the storage system 1 of the embodiment.

  In FIG. 5, the number of relevant CEs = a and the number of history CEs = b. Further, the number of CEs that can be corrected in the error correction processing unit 21 (the number of CE corrections possible) = c, and the predicted number of CEs at the next read = d.

Since the increment from the history CE number (b) to the corresponding CE number (a) is (ab), assuming that the rate of increase in CE number and the read interval are uniform, the predicted CE number at the next read (D) can be obtained by the following equation (1).
Predicted CE number at next read (d) = a + (a−b) (1)

Here, when the predicted number of CEs (d) at the next read exceeds the correctable number (c), correction is impossible. Therefore, if the following conditional expression (2) is not satisfied, error correction is performed at the next read. Correction is impossible in the processing unit 21.
a + (a−b) ≦ c (2)

That is, if the number of corresponding CEs (a) does not satisfy the following expression (3), the error correction processing unit 21 cannot perform correction at the next read.
a ≦ (b + c) / 2 (3)

  The above reference value assumes that the read interval and the CE number increment are uniform, but in actuality these values vary, and therefore the coefficient k (0 ≦ k ≦ 1) It is desirable to set a reference value c ′ ′ with a margin and to make a determination.

  In the above example, the reference value focusing on the increase in the number of corresponding CEs is set, but the present invention is not limited to this. For example, a reference value focusing on the increase in the number of CEs including adjacent pages may be set, and various modifications can be made.

(B) Operation A read request processing method in the storage system 1 as an example of the embodiment configured as described above will be described with reference to the flowchart (steps A1 to A10) shown in FIG.

  In step A <b> 1, a read request (data request) is input from the host 200, and the data access control unit 20 acquires the data request and the read target data address from the host 200.

  In step A2, the data access control unit 20 requests the cache access control unit 12 of the cache management unit 10 to perform a cache search. The cache access control unit 12 inputs a search request with a data address to the information management unit 11.

  In step A3, the information management unit 11 searches the cache management information 111a and confirms whether the read target data is stored in the cache memory 102, that is, whether a cache hit has occurred.

  If the result of the check is a cache hit (see YES route in step A3), the process proceeds to step A4. In step A4, the information management unit 11 updates the generation number of the page corresponding to the read access destination in the cache management information 111a. The information management unit 11 returns the search result to the cache access control unit 12, and the cache access control unit 12 returns the search result to the data access control unit 20.

  In step A5, the data access control unit 20 reads the read target data stored in the cache memory 102 and causes the host 200 to respond.

  On the other hand, if the result of confirmation in step A3 is that there is no cache hit (see NO route in step A3), the process proceeds to step A6.

  In step A6, the cache access control unit 12 confirms whether the cache memory 102 is in a cache full state. As a result of the confirmation, if the cache memory 102 is not cache full (refer to the NO route in step A6), the process proceeds to step A9.

  If the result of confirmation in step A6 is that the cache memory 102 is full (see YES route in step A6), the process proceeds to step A7.

  In step A7, the cache access control unit 12 selects page data to be replaced from the page data stored in the cache memory 102, that is, page data to be cached out.

  In step A8, the cache access control unit 12 deletes (caches out) the replacement target data in the cache memory 102. Further, the cache access control unit 12 causes the information management unit 11 to delete the entry of the page data deleted from the cache memory 102 from the cache management information 111a. The entry deleted from the cache management information 111a is stored in the cache history information 111b. Thereafter, the process proceeds to step A9.

  In step A9, the cache access control unit 12 causes the information management unit 11 to register information about the read data newly stored in the cache memory 102 in the cache management information 111a.

  In step A <b> 10, the data access control unit 20 reads the read target data from the NAND flash memory 101. Data read from the NAND flash memory 101 is input to the error correction processing unit 21, and after error detection is performed in the error correction processing unit 21, the data is transmitted to the host 200 as a data response. When a correctable error (CE) is detected in the error correction processing unit 21, the error correction processing unit 21 corrects this error, and the read data subjected to this error correction is sent to the host 200 as response data. As sent.

  The error correction processing unit 21 notifies the cache access control unit 12 (cache management unit 10) of the number of CEs when error correction is performed.

  The cache access control unit 12 notifies the information management unit 11 of the CE number notified from the error correction processing unit 21, and updates the CE number of the corresponding entry in the cache management information 111a.

  The read data read from the NAND flash memory 101 and subjected to error correction as necessary is also transferred to the cache memory 102 and stored (cached in) in the cache memory 102.

  Next, details of the replacement target selection method in step A7 of the flowchart shown in FIG. 6 will be described according to the flowchart (steps B1 to B17) shown in FIG.

  In step B1, the cache access control unit 12 confirms with the information management unit 11 whether there is a page in which the number of CEs is smaller than the reference value A in the cache management information 111a (hereinafter sometimes referred to as condition J_01). To do.

  As a result of the confirmation in step B1, if there is a page whose CE number is smaller than the reference value A (see YES route in step B1), “0” is set in FLAG_A, and the process proceeds to step B2.

  In step B2, the cache access control unit 12 confirms whether there is a page whose generation number is older than the reference value B (hereinafter may be referred to as condition J_02).

  As a result of the confirmation in step B2, if there is a page whose generation number is older than the reference value B (see YES route in step B2), “0” is set in FLAG_B, and the process proceeds to step B3.

  In step B3, the cache access control unit 12 selects all pages that satisfy both the above-described condition J_01 and condition J_02.

  In step B4, the cache access control unit 12 compares the number of CEs of the corresponding page with the history in the page selected in step B3, and whether there is a page with an increased number of CEs less than the reference value C ( Hereinafter, it may be referred to as condition J_03).

  As a result of the confirmation in step B4, if there is no page in which the number of CE increases is less than the predetermined reference value C (see NO route in step B4), “1” is set in FLAG_C, and the process proceeds to step B5. .

  In step B5, the cache access control unit 12 determines whether there is a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D in the page selected in step B3 (hereinafter, referred to as condition J_04). )

  As a result of the confirmation in step B5, when there is no page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D (see NO route in step B5), FLAG_D is set to “1”, and step B6 Migrate to

  In Step B6, the cache access control unit 12 selects all pages that satisfy the above-described condition J_01 and do not satisfy the condition J_02.

  In step B7, the cache access control unit 12 compares the number of CEs of the corresponding page with the history in the page selected in step B6, and whether there is a page where the number of CE increases is smaller than the reference value C ( Check condition J_03).

  As a result of the confirmation in step B7, if there is no page in which the number of CE increases is less than the predetermined reference value C (see NO route in step B7), “1” is set in FLAG_C, and the process proceeds to step B8. .

  In step B8, the cache access control unit 12 confirms whether there is a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is less than the reference value D in the page selected in step B6 (condition J_04).

  As a result of the confirmation in step B8, if there is no page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D (see NO route in step B8), FLAG_D is set to “1”, and step B10 Migrate to

  As a result of the confirmation in step B4 and step B7, if there is a page in which the number of CE increases is smaller than the predetermined reference value C (see YES route in step B4, YES route in step B7), “ 0 "is set, and the process proceeds to step B9.

  Further, as a result of the confirmation in step B5 and step B8, when there is a page where the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D (see YES route in step B5, YES route in step B8), FLAG_D is set to “0” and the process proceeds to step B9.

  On the other hand, as a result of the confirmation in step B1, if there is no page with the CE number less than the reference value A (see NO route in step B1), “1” is set in FLAG_A, and the process proceeds to step B10.

  In step B10, the cache access control unit 12 checks whether there is a page whose generation number is older than the reference value B (condition J_02).

  As a result of the confirmation in step B10, if there is a page whose generation number is older than the reference value B (see YES route in step B10), FLAG_B is set to “0” and the process proceeds to step B11.

  In step B11, the cache access control unit 12 selects all pages that satisfy the above-described condition J_01 and do not satisfy the condition J_02.

  In step B12, the cache access control unit 12 compares the number of CEs of the corresponding page with the history in the page selected in step B11, and whether there is a page in which the increased number of CEs is smaller than the reference value C ( Check condition J_03).

  As a result of confirmation in step B12, if there is no page in which the number of CE increases is smaller than the predetermined reference value C (see NO route in step B12), FLAG_C is set to “1” and the process proceeds to step B13. .

  In step B13, the cache access control unit 12 confirms whether there is a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D in the page selected in step B11 (condition J_04).

  As a result of the confirmation in step B13, if there is no page in which the sum of the number of corresponding CEs and the number of adjacent CEs is less than the reference value D (see NO route in step B13), “1” is set to FLAG_D, and step B14 Migrate to

  In step B14, the cache access control unit 12 selects all pages that do not satisfy the above-described condition J_01 and do not satisfy the condition J_02.

  In step B15, the cache access control unit 12 compares the number of CEs of the corresponding page with the history in the page selected in step B14, and whether there is a page with an increased number of CEs less than the reference value C ( Check condition J_03).

  As a result of the confirmation in step B15, if there is no page in which the number of CE increases is less than the predetermined reference value C (see NO route in step B15), FLAG_C is set to “1” and the process proceeds to step B16. .

  In step B16, the cache access control unit 12 confirms whether there is a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D in the page selected in step B14 (condition J_04).

  As a result of the confirmation in step B16, if there is no page in which the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D (see NO route in step B16), FLAG_D is set to “1”, and step B17 Migrate to

  In step B <b> 17, the cache access control unit 12 determines the page with the oldest generation number as a replacement target and ends the process.

  As a result of the confirmation in step B12 and step B15, if there is a page in which the number of CE increases is smaller than the predetermined reference value C (see YES route in step B12, YES route in step B15), “ 0 "is set, and the process proceeds to step B9.

  Further, as a result of the confirmation in step B13 and step B16, when there is a page where the sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D (see YES route in step B13, YES route in step B16), FLAG_D is set to “0” and the process proceeds to step B9.

  In step B9, the cache access control unit 12 determines a page having the oldest generation number as a replacement target from pages satisfying any one of steps B4, B5, B7, B8, B12, B13, B15, and B16. The process ends.

(C) Effect As described above, according to the storage system 1 as an embodiment of the present invention, the information management unit 11 of the cache management unit 10 manages the number of corresponding CEs, the number of adjacent CEs, and the number of history CEs for each page. To do.

  Then, the cache access control unit 12 leaves a page in which the sum of the number of corresponding CEs and the number of adjacent CEs is equal to or greater than a predetermined reference value (first threshold) D in the cache memory 102 as a target of cache eviction. Then, a page whose sum of the number of corresponding CEs and the number of adjacent CEs is smaller than the reference value D is preferentially set as a cache eviction target.

  As a result, the data of the page considered to have deteriorated in the NAND flash memory 101 is held in the cache memory 102 without being evicted from the cache memory 102. As a result, even when a read request is issued from the host 200 to this page, access to the page in the NAND flash memory 101 can be suppressed. By leaving data in the cache memory 102, data access to the NAND flash memory 101 can be avoided. As a result, the progress of deterioration of the area can be suppressed, and the durability of the NAND flash memory 101 can be improved.

  The cache access control unit 12 determines the target to be evicted from the cache memory 102 based on not only the number of CEs detected in the page of the data to be read (corresponding page) but also the number of CEs detected in the adjacent page. to decide. In this way, by considering not only the page to be read but also the number of CEs of the adjacent page, it is possible to determine whether or not the cache is necessary focusing on read disturb, and the durability of the NAND flash memory 101 can be improved. .

  Further, the cache access control unit 12 compares the generation number of the page with a predetermined reference value (second threshold) B, and leaves a page whose generation number is newer than the reference value B as a cache eviction target in the cache memory 102. . Then, a page whose generation number is older than the reference value B is given priority as a cache eviction target.

  As a result, it is possible to leave, in the cache memory 102, data of a page that has a short period of time when there is no access since the last access, and is likely to be accessed again. Therefore, even when a read request is issued from the host 200 to this page, data access to the NAND flash memory 101 can be avoided. That is, the progress of deterioration of the area can be suppressed and the durability of the NAND flash memory 101 can be improved.

  The cache access control unit 12 compares the CE number of the page with a predetermined reference value (threshold value) A, leaves a page having the CE number equal to or greater than the reference value A in the cache memory 102 as a cache eviction target, and the CE number is A page smaller than the reference value A is preferentially set as a cache eviction target.

  As a result, pages with a large number of CEs can remain in the cache memory 102 as protection targets. Therefore, even when a read request is issued from the host 200 to this page, data access to the NAND flash memory 101 can be avoided. That is, the progress of deterioration of the area can be suppressed and the durability of the NAND flash memory 101 can be improved.

  Further, the cache access control unit 12 compares the number of CEs in the past (history) in the same page with the number of increase in the number of CEs equal to or greater than a predetermined reference value (third threshold) C as a cache eviction target. Leave to 102. Then, a page whose number of CE increases is less than a predetermined reference value (third threshold) C is preferentially set as a cache eviction target.

  As a result, a page whose number of CEs is increasing can be left in the cache memory 102 as a protection target. Therefore, even when a read request is issued from the host 200 to this page, data access to the NAND flash memory 101 can be avoided. That is, the progress of deterioration of the area can be suppressed and the durability of the NAND flash memory 101 can be improved.

(D) Others In the above-described embodiment, the functions (cache management unit 10, data access control unit 20, and error correction processing unit 21) as the memory controller 110 may be realized by hardware using a circuit device. Further, at least a part of these functions may be realized by a processor executing a control program. The processor is any one of a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and a field programmable gate array (FPGA). It may be one. Further, the processor may be a combination of two or more types of elements among CPU, MPU, DSP, ASIC, PLD, and FPGA.

  The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. Each structure and each process of this embodiment can be selected as needed, or may be combined suitably.

  Further, according to the above-described disclosure, this embodiment can be implemented and manufactured by those skilled in the art.

(E) Additional remarks The following additional remarks are disclosed regarding the above embodiment.

(Appendix 1)
An error correction processing unit that performs error correction when an error is detected in the data read from the semiconductor storage device, and outputs the number of corrected errors;
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area And a setting unit that sets the data of the first unit area to be excluded from being evicted from the cache memory when the sum of the above and the first threshold is equal to or greater than the first threshold.

(Appendix 2)
The setting unit
The data of the first unit area is evicted from the cache memory when the elapsed time in the absence of access since the data access to the first unit area is shorter than the second threshold value The storage device according to appendix 1, wherein the storage device is set outside.

(Appendix 3)
The setting unit
The first unit when the first error number detected in the first unit area is greater than or equal to a third threshold value from the number of errors detected in the past in the first unit area. The storage apparatus according to appendix 1 or 2, wherein the data in the area is set as a target not to be evicted from the cache memory.

(Appendix 4)
A storage unit for storing cache management information for managing data stored in the cache memory in units of unit areas;
The storage according to any one of appendices 1 to 3, wherein the cache management information includes position information of the unit area in the semiconductor storage device and the number of errors detected in the unit area. apparatus.

(Appendix 5)
In an information processing apparatus comprising a processor and an error correction processing unit that performs error correction when an error is detected in data read from a semiconductor storage device and outputs the number of corrected errors,
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area Is a control program that causes the processor to execute a process of setting the data in the first unit area to be excluded from being purged from the cache memory.

(Appendix 6)
The data of the first unit area is evicted from the cache memory when the elapsed time in the absence of access since the data access to the first unit area is shorter than the second threshold value The control program according to appendix 5, which causes the processor to execute processing to be set outside.

(Appendix 7)
When the first error number detected in the first rank area is larger than the number of errors detected in the past in the first rank area, the first rank area is greater than or equal to a third threshold value. The control program according to appendix 5 or 6, which causes the processor to execute a process of setting the data to be exempted from the cache memory.

(Appendix 8)
Causing the processor to execute processing for storing cache management information for managing data stored in the cache memory in units of unit areas,
The control according to any one of appendices 5 to 7, wherein the cache management information includes position information of the unit area in the semiconductor memory device and the number of errors detected in the unit area. program.

(Appendix 9)
In an information processing apparatus comprising a processor and an error correction processing unit that performs error correction when an error is detected in data read from a semiconductor storage device and outputs the number of corrected errors,
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area A process of comparing the sum of and the first threshold value;
And a process of setting the data of the first unit area to be excluded from eviction from the cache memory when the sum of the first error number and the second error number is equal to or greater than the first threshold value. Method.

(Appendix 10)
The data of the first unit area is evicted from the cache memory when the elapsed time in the absence of access since the data access to the first unit area is shorter than the second threshold value The control method according to supplementary note 9, comprising a process of setting outside.

(Appendix 11)
When the first error number detected in the first rank area is larger than the number of errors detected in the past in the first rank area, the first rank area is greater than or equal to a third threshold value. The control method according to appendix 9 or 10, further comprising a process of setting the data in the cache memory not to be evicted.

(Appendix 12)
A process of storing cache management information for managing the data stored in the cache memory in units of unit areas;
The control method according to any one of appendices 9 to 11, wherein the cache management information includes position information of the unit area in the semiconductor memory device and the number of errors detected in the unit area.

DESCRIPTION OF SYMBOLS 1 Storage system 100 Storage apparatus 110 Memory controller 10 Cache management part 11 Information management part 111 Cache information
111a Cache management information 111b Cache history information 12 Cache access control unit 20 Data access control unit 21 Error correction processing unit 101 NAND flash memory 102 DRAM (cache memory)

Claims (6)

An error correction processing unit that performs error correction when an error is detected in the data read from the semiconductor storage device, and outputs the number of corrected errors;
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area And a setting unit that sets the data of the first unit area to be excluded from being evicted from the cache memory when the sum of the above and the first threshold is equal to or greater than the first threshold. The setting unit
The data of the first unit area is evicted from the cache memory when the elapsed time in the absence of access since the data access to the first unit area is shorter than the second threshold value The storage apparatus according to claim 1, wherein the storage apparatus is set outside. The setting unit
The first unit when the first error number detected in the first unit area is greater than or equal to a third threshold value from the number of errors detected in the past in the first unit area. The storage apparatus according to claim 1 or 2, wherein the data in the area is set as a target not to be evicted from the cache memory. A storage unit for storing cache management information for managing data stored in the cache memory in units of unit areas;
The said cache management information is provided with the positional information on the said unit area in the said semiconductor memory device, and the number of errors detected in the said unit area, The any one of Claims 1-3 characterized by the above-mentioned. Storage device. In an information processing apparatus comprising a processor and an error correction processing unit that performs error correction when an error is detected in data read from a semiconductor storage device and outputs the number of corrected errors,
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area Is a control program that causes the processor to execute a process of setting the data in the first unit area to be excluded from being purged from the cache memory. In an information processing apparatus comprising a processor and an error correction processing unit that performs error correction when an error is detected in data read from a semiconductor storage device and outputs the number of corrected errors,
Of the plurality of unit areas provided in the semiconductor memory device, the first error number detected in the first unit area and the second error number detected in the second unit area adjacent to the first unit area A process of comparing the sum of and the first threshold value;
And a process of setting the data of the first unit area to be excluded from eviction from the cache memory when the sum of the first error number and the second error number is equal to or greater than the first threshold value. Method.

Images