JP2008262614A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of performing satisfactory data writing to, reading from and erasing for a memory array irrespective of the situation of access to each block. <P>SOLUTION: A first detection unit 41 detects a block including a defective cell as a congenital defective block. A second detection unit 42 clocks data writing time for each block other than the detected congenital defective block, and detects a block selected on the basis of the clocked data writing time as a block likely to be an acquired defective block in the future. A registration unit 45 registers pieces of information about the detected congenital and acquired defective blocks as pieces of defective block information for each block in a block information storage table 51a. A memory control unit 20 excludes the congenital and acquired defective blocks from access target blocks by referring to the pieces of defective block information registered in the block information storage table 51a beforehand by a diagnosis unit 40. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to improvement of processing for a defective block.

  In the nonvolatile semiconductor memory device, a technique for determining the deterioration status of each memory cell based on erasing information of each memory cell has been conventionally known (for example, Patent Document 1). Patent Document 1 also discloses a technique for suppressing the progress of deterioration by applying to a memory cell that is determined to be deteriorated.

  Also, a technique for replacing a deteriorated memory cell with a redundant memory cell or a memory cell block when the write / erase characteristics of the nonvolatile memory cell deteriorate has been known ( For example, Patent Document 2).

JP 2002-208286 A JP 2002-074978 A

  Therefore, the techniques of Patent Documents 1 and 2 require processing for monitoring the deterioration state of the memory cell during use. As a result, there has been a problem that the processing load of the nonvolatile semiconductor memory device increases.

  Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can execute data writing, data reading, and data erasing with respect to a memory array regardless of the access status to each block.

  In order to solve the above-mentioned problem, the invention of claim 1 is characterized in that a memory array divided into a plurality of blocks and an access status to each block included in the memory array are diagnosed to detect defects from the plurality of blocks. A diagnostic unit that detects a block; a block information storage table that stores information about the defective block; and a memory control unit that executes an access process to each block, and the memory array includes a plurality of data storage units. The diagnostic unit has a first detection unit that detects a first block including a defective cell as a congenital defective block, and obtains an index value of an access status for each block other than the congenital defective block. And a second detector for detecting the second block selected based on the index value as an acquired defective block; And a registration unit for registering information on the congenital defective block and the acquired defective block detected by the second detection unit in the block information storage table as defective block information for each block, and the memory control The unit excludes the congenital defective block and the acquired defective block from the access target block based on the defective block information registered in the block information storage table by the diagnostic unit in advance.

  According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the number of the bad block information that can be stored in the block information storage table is a predetermined number corresponding to the total number of the plurality of blocks. It is characterized by the following.

  According to a third aspect of the present invention, there is provided a memory array divided into a plurality of blocks, a diagnosis unit that diagnoses an access status to each block included in the memory array, and the diagnosis unit of the plurality of blocks. A block information storage table for storing information about the block selected according to the diagnosis result, and a memory control unit for executing access processing to each block, and the memory array stores data The diagnostic unit has a plurality of cells, the diagnostic unit detects a first block including a defective cell as a defective block, and obtains an index value of an access status for each block other than the defective block, A second detection unit for detecting a second block selected based on the index value as a refresh target block; and the first detection A registration unit for registering in the block information storage table as information on the bad block detected by the second block, and as information on the block to be refreshed detected by the second detection unit as block information to be refreshed. And the memory control unit excludes the defective block from the access target block based on the defective block information and the refresh target block registered in the block information storage table by the diagnosis unit in advance, and the refresh target A refresh process is performed on the block.

  According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to the third aspect, the total number of the defective block information that can be stored in the block information storage table and the number of the refresh target block information. Is not more than a predetermined number corresponding to the total number of the plurality of blocks.

  According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the index value is a data write executed for each block by the memory control unit. The second detection unit selects the second block in order from the block with the largest index value.

  According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fifth aspect, each block has a plurality of pages, and the memory control unit performs a data write process on a page basis. And the second detector uses a total of data writing times of each page included in the writing target block as the index value.

  According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the fifth aspect, each block has a plurality of pages, and the memory control unit performs a data write process on a page basis. And the second detection unit uses a maximum time among data writing times of each page included in the block as the index value.

  According to an eighth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the index value is a data erasure executed for each block by the memory control unit. It is time, The said 2nd detection part selects as a said 2nd block in an order from the block with the said large index value, It is characterized by the above-mentioned.

  According to a ninth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the index value is a data erasure executed for each block by the memory control unit. The time and the data writing time are summed up, and the second detection unit selects the second block in order from the block with the largest index value.

  According to a tenth aspect of the present invention, there is provided a memory array divided into a plurality of blocks, a diagnosis unit that diagnoses an access status to each block included in the memory array, and the diagnosis unit of the plurality of blocks. A block information storage table for storing information related to the block selected according to the diagnosis result, and a memory control unit for executing access processing to the plurality of blocks, and the memory array stores data The diagnostic unit has a plurality of cells to be stored, the diagnosis unit detects a first block including a defective cell as a congenital defective block, and an access status for each block other than the congenital defective block And the second block in which the index value is in the first range is detected as an acquired defect block, and the index value is A second detection unit that detects a third block that is in a range and has a better access status as compared to the second block as a refresh target block; the congenital defective block detected by the first and second detection units; and A registration unit that registers information about acquired defective blocks as defective block information, and information about the refresh target block detected by the second detection unit as refresh target block information, respectively, in the block information storage table; The memory control unit excludes the congenital defective block and the acquired defective block from the access target block based on the defective block information and the refresh target block registered in advance in the block information storage table by the diagnosis unit. And the reflation And executes the refresh process Shrewsbury target block.

  According to the invention described in claim 1, claim 2, and claim 5 to claim 10, the diagnosis unit not only detects a congenital defective block that already has a defective cell, but also a defective block in the future. Acquired bad blocks that are likely to become the same can be detected based on the index value of the access status. Thereby, not only a congenital defective block but also a block that may become an acquired defective block can be excluded from the access target blocks of the memory control unit. Therefore, the function of excluding acquired defective blocks from the access target during use of the device and the hardware (circuit) for realizing this function are not required, and the configuration of the nonvolatile semiconductor memory device can be simplified.

  Further, according to the inventions according to claims 1, 2, and 5 to 10, blocks that are likely to become acquired defective blocks are excluded from access targets. This eliminates the need for processing for detecting whether an acquired defective block has occurred, thereby reducing the processing burden on the nonvolatile semiconductor memory device.

  Further, according to the invention described in claims 3 to 10, there is a possibility that the data stored in the same block is repeatedly read, so that the stored data is deteriorated and a data read error occurs. A certain block can be selected as a refresh target block. That is, the selected refresh target block can be the target of the refresh process. Therefore, it is possible to prevent a data reading error from occurring in each block.

  In particular, according to the second and fourth aspects of the invention, the capacity of the block information storage table can be set to a constant value instead of a variable value. Therefore, the hardware configuration of the block information storage table can be facilitated.

  In particular, according to the fifth aspect of the present invention, the time required for writing data in each block is used as an index value. Here, it is known that the data writing time tends to increase for blocks that may become acquired bad blocks in the future.

  Therefore, by selecting in order from the block with the long data writing time, it is possible to reliably detect a block that may become an acquired defective block. Therefore, the selected second block can be surely excluded from the access target block by the memory control unit. Alternatively, a block that may become an acquired defect block in the future and that may cause a data read error can be selected as a refresh target block and can be a target of refresh processing.

  In particular, according to the sixth aspect of the invention, the data writing time of each entire block can be used as an index value. According to the seventh aspect of the present invention, the maximum time among the data writing times of each page included in the block can be used as the index value. Therefore, it is possible to reliably detect a block that may become an acquired defective block or a refresh target block.

  In particular, according to the eighth aspect of the invention, the time required for erasing data of each block is used as an index value. Here, it is known that the data erasure time tends to increase for blocks that may become acquired bad blocks in the future. Therefore, by selecting in order from the block with the long data erasing time, it is possible to reliably detect a block that may become an acquired defective block. Therefore, the selected second block can be surely excluded from the access target block by the memory control unit. Alternatively, a block that may become an acquired defect block in the future and that may cause a data read error can be selected as a refresh target block and can be a target of refresh processing.

  In particular, according to the invention described in claim 9, the total of the time required for data erasure and data writing of each block is used as the index value. Therefore, by selecting in order from the block with the largest index value, it is possible to reliably detect a block that may become an acquired defective block. Therefore, the selected second block can be surely excluded from the access target block by the memory control unit, or the selected second block can be the target of the refresh process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<1. First Embodiment>
<1.1. Configuration of information processing system>
FIG. 1 is a diagram showing an example of the overall configuration of an information processing system 1 and a nonvolatile semiconductor memory device 10 in the present embodiment. The information processing system 1 is a device that executes arithmetic processing according to a program. For example, mobile information terminals such as mobile phones and PDAs (Personal Digital Assistants), video equipment such as digital cameras and digital video, or information processing apparatuses such as personal computers and workstations correspond to the information processing system 1. As shown in FIG. 1, the information processing system 1 mainly includes a nonvolatile semiconductor memory device 10, a CPU 91, and a RAM 92.

  The non-volatile semiconductor memory device 10 is a non-volatile memory that is readable and writable, such as a NAND flash memory or a NOR flash memory, and the stored content does not disappear even when the power supply is cut off.

  Here, the nonvolatile semiconductor memory device 10 may store a program describing an instruction for the CPU 91, or may store data used for calculation by the CPU 91. Further, the form of the nonvolatile semiconductor memory device 10 may be a form that can be attached to and detached from the information processing system 1 (for example, one that is packaged in a card shape), or an information processing system that uses solder or the like. 1 may be a fixed form. Details of the nonvolatile semiconductor memory device 10 will be described later.

  A CPU (Central Processing Unit) 91 executes control according to a program and data calculation / processing. A RAM (Random Access Memory) 92 is a readable / writable volatile memory, and stores data used for calculation and processing in the CPU 91, for example. Further, each of the nonvolatile semiconductor memory device 10, the CPU 91, and the RAM 92 is electrically connected via a bus line 95. Therefore, the CPU 91 can execute, for example, data writing and data erasing with respect to the nonvolatile semiconductor memory device 10 at a predetermined timing.

<1.2. Configuration of Nonvolatile Semiconductor Memory Device>
Here, the hardware configuration of the nonvolatile semiconductor memory device 10 will be described. As shown in FIG. 1, the nonvolatile semiconductor memory device 10 mainly includes a memory array 15, a memory control unit 20, a host interface 30, a diagnosis unit 40, a first storage unit 51, and a second storage unit 52. And.

  FIG. 2 is a diagram for explaining a logical configuration of the memory array 15. The memory array 15 has a plurality of cells (storage elements: not shown) that are the minimum unit of data storage. As shown in FIGS. 1 and 2, the memory array 15 is divided into a plurality of blocks BL. ing. As shown in FIG. 2, each block BL is divided into a plurality of pages PG, and each page PG is composed of a plurality of cells. The storage capacity of each cell may be 1 bit, or may be multi-bit (2 bits or more).

  The memory control unit 20 is a controller that controls execution of access processing (data writing processing, data reading processing, data erasing processing, etc.) to each block. The memory control unit 20 executes data read / write processing in units of page PG (see FIG. 2) and data erasure processing in units of block BL (see FIGS. 1 and 2).

  Further, the memory control unit 20 can exclude the defective block from the access target block by referring to the information stored in the block information storage table 51 a of the first storage unit 51.

  Here, the defective block refers to a block that has a defective cell in the block and the access process does not end normally. Bad blocks include congenital bad blocks and acquired bad blocks.

  A defective cell is a cell in which word lines and bit lines in the memory array 15 are electrically open or short-circuited independently or in combination, and data writing or erasing is not executed correctly. Say. In addition, since the gate oxide film is significantly deteriorated, a cell in which data writing or data erasure is not correctly executed is also included in the defective cell.

  A congenital defective block is a block that is already a defective block at the time of manufacture or at the time of factory shipment.

  Further, the acquired defective block is a late defective block that occurs when the nonvolatile semiconductor memory device 10 is used after being shipped from the factory. A block that may become an acquired defective block becomes a defective cell when the number of data writing times and the number of data erasing times is less than a predetermined guaranteed number of times (that is, until the lifetime of the nonvolatile semiconductor memory device 10 is reached) Includes a cell).

  For example, for word lines and bit lines in the memory array 15, cells in which the electrical open state or short-circuit state of these lines is extremely weak, or cells in which leakage occurs in the gate oxide film (hereinafter referred to as “non-quality cells”). ”) Has a higher probability of retry processing compared to a high-quality cell, and as a result, data writing time and erasing time tend to increase. If the writing process and the erasing process are continuously performed on the non-quality cell, the non-quality cell may become a defective cell. That is, a non-good quality cell is likely to transition to a defective cell by normal use.

  The host interface 30 is a device for connecting the nonvolatile semiconductor memory device 10 to the bus line 95. For example, the host interface 30 adjusts a difference in operating voltage and response speed between the bus line 95 side and the nonvolatile semiconductor memory device 10 side. To do.

  The diagnosis unit 40 diagnoses an access status (for example, a data write status or an erase status) to each block BL included in the memory array 15, thereby congenital defective blocks and acquired defective blocks from the plurality of blocks BL. Is detected. As illustrated in FIG. 1, the diagnosis unit 40 mainly includes a first detection unit 41, a second detection unit 42, and a registration unit 45.

  The first detection unit 41 detects a block including a defective cell (first block) from each block as a congenital defective block. For example, for a block including a defective cell at the time of factory shipment, a logical value “True” indicating that it is a defective block is stored in a predetermined area (for example, a flag area) in the block. On the other hand, the logical value “False” is stored in the flag area of a block that is not determined as a defective block at the time of factory shipment. In this case, the first detection unit 41 detects the block BL whose logical value stored in the flag area is “True” as a congenital defective block.

  The second detection unit 42 obtains an index value of the access status for each block other than the detected congenital bad block after the first detection unit 41 detects the congenital bad block. In addition, the second detection unit 42 detects the block (second block) selected based on the index value as a block that may become an acquired defect block in the future.

  Here, there is a high possibility that a block that may become an acquired defective block includes the above-mentioned non-good quality cells. In addition, the data write time for the block including the non-good quality cell is likely to be longer than that for the good quality cell.

  Therefore, the second detection unit 42 measures the time of data writing performed on each block BL by the memory control unit 20, and uses the measured data writing time as an index value. And the 2nd detection part 42 selects as a block (2nd block) which may become an acquired defect block in an order from the block BL with the largest measured index value. As a result, the selected block (second block) can be surely excluded from the access target block of the memory control unit 20.

  The index value based on the data writing time was measured by causing the memory control unit 20 to execute data writing processing for each page PG (see FIG. 2) of the writing target block. The total data write time for each page may be used. Further, the maximum time among the data writing times of each page included in the writing target block may be used as the index value.

  In order to ensure the reliability of the index value, the data writing time is measured according to the following procedure. That is, first, all data in the block is deleted. Then, a time T required until “00h” is stored in all the cells of the page to be written is measured. Here, the data write time T of each page PG is the time t1 when the write control signal changes from the “Ready” state to the “Busy” state (that is, the signal logic changes from the “High” state to the “Low” state). And a time t2 when the write control signal transitions from the “Busy” state to the “Ready” state (ie, when the signal logic transitions from the “Low” state to the “High” state). (See FIG. 3).

  The registration unit 45 uses the block information storage table 51a as information on the congenital defective block detected by the first detection unit 41 and the acquired defective block detected by the second detection unit 42 as defective block information for each block. Register with.

  The first storage unit 51 is a storage unit configured by a so-called memory. In the block information storage table 51a, for example, it is stored in the block information storage table 51a that stores information on bad block information.

  FIG. 4 is a diagram showing an example of the data structure of the block information storage table 51a in the present embodiment. As shown in FIG. 4, the block information storage table 51a has, for example, fields (columns) of “ID” and “block NO”.

  In the “ID” field, an identifier for uniquely identifying each record (each row) included in the block information storage table 51a is stored. An identifier for uniquely identifying each block BL constituting the memory array 15 is stored in the “block NO” field.

  Thereby, the memory control unit 20 can exclude the congenital defective block and the acquired defective block from the access target block by referring to the defective block information registered in the block information storage table 51a by the diagnosis unit 40 in advance. it can.

  As shown in FIG. 4, the congenital defective block and the acquired defective block are not separately registered in the block information storage table 51a, but are not limited thereto. For example, a field for identifying a congenital defective block and an acquired defective block may be created in the block information storage table 51a, and data for identifying both blocks may be stored in this field.

  The number of records stored in the block information storage table 51a (that is, the number of defective block information) is a predetermined number M (M is a positive number) according to the capacity of the memory array 15 and the total number of blocks BL included in the memory array 15. Integer). Thereby, the capacity of the block information storage table 51a can be set to a fixed value instead of a variable value, and the hardware configuration of the first storage unit 51 can be facilitated.

  Similar to the first storage unit 51, the second storage unit 52 is a storage unit configured by a so-called memory. The sort information storage table 52a stores a sort information storage table 52a that can be used for the acquired defective block detection process by the second detection unit 42.

  FIG. 5 is a diagram showing an example of the data structure of the sort information storage table 52a in the present embodiment. The sort information storage table 52a is a table capable of storing N (N is a positive integer) records. The sort information storage table 52a is used to arrange the measured data writing times in descending order when the acquired defective block is detected by the second detection unit. As shown in FIG. 5, the sort information storage table 52a has, for example, fields of “block NO” and “write time”.

  In the “ID” field, an identifier for uniquely identifying each record included in the block information storage table 51a is stored. The “block NO” field stores an identifier for uniquely identifying each block BL of the memory array 15. The “write time” field stores the data write time corresponding to the block designated by the “block NO” field.

  Here, the second detection unit 42 stores the data writing time and the block NO of each block BL so that the value stored in the “writing time” field is descending from the top of the record (upper side). Store in table 52a.

  For example, the write time of the block to be written is (1) less than or equal to the value stored in the “write time” field of the record 52b, and (2) stored in the “write time” field of the record 52c. When the value is larger than the recorded value, the record with “ID” = “N” (the record in the last row) is deleted, and the “ID” of the record below the record 52b is increased by 1, and the record below the record 52b Records are advanced sequentially. Then, the block number and the data writing time of the writing target block are stored in the record with “ID” = “2”. Note that the total number N of records in the sort information storage table 52a may be a constant value based on the capacity of the memory array 15 and the like.

<1.3. Bad Block Detection Procedure>
FIG. 6 is a flowchart for explaining a procedure for detecting congenital and acquired defective blocks in the present embodiment. In this detection procedure, first, a detection process for a congenital defective block is executed by the first detection unit 41 (S101). Information on the detected congenital bad block is registered as bad block information in the block information storage table 51a (S102). The registration of defective block information may be performed every time a congenital defective block is detected, or may be performed after the detection process of a congenital defective block is completed for all the blocks BL.

  Next, the acquired detection block detection process is executed by the second detection unit 42. That is, processing for measuring the data writing time for each block BL is executed (S103). Subsequently, the measured writing time is compared with the value of “writing time” already stored in the sort information storage table 52a (S104). If the measured writing time is larger than any of the registered “writing times”, the records having the measured writing time and block NO are sorted and registered in the sort information storage table 52a. (S105). On the other hand, if the measured writing time is smaller than or equal to any of the registered “writing times”, the process proceeds to step S106. The processes in steps S103 to S105 are executed until the measurement of the data writing time is completed for all the blocks in the memory array 15 (S106). When the measurement of the data writing time is finished for all the blocks (S106), the block information is stored as acquired defective blocks in order from the block having the largest “writing time” among the data stored in the sort information storage table 52a. It is registered in the table 51a (S107), and this procedure ends.

  If the number of congenital defective blocks already registered in the block information storage table 51a is Mc (≧ 0) and the number of block information that can be registered in the block information storage table 51a is M (> 0), the block The number Mp (≧ 0) of acquired defective blocks that can be registered in the information storage table 51a can be expressed by the following equation (1).

      1 ≦ Mp ≦ M−Mc (Equation 1)

<1.4. Advantages of Nonvolatile Semiconductor Memory Device in First Embodiment>
As described above, the nonvolatile semiconductor memory device 10 according to the first embodiment not only detects a congenital defective block that already has a defective cell, but also acquires an acquired defective block that may become a defective block in the future. Can also be detected. Thereby, not only a congenital defective block but also a block that may become an acquired defective block can be excluded from the access target blocks of the memory control unit 20. Therefore, the function of excluding acquired defective blocks from the access target while using the nonvolatile semiconductor memory device 10 and the hardware (circuit) that realizes this function are not required, and the configuration of the nonvolatile semiconductor memory device 10 is simplified. Can do.

  Further, in the nonvolatile semiconductor memory device 10, blocks that may become acquired defective blocks are excluded from access targets. This eliminates the need for processing for detecting whether an acquired defective block has occurred. Therefore, the processing burden on the nonvolatile semiconductor memory device 10 can be reduced.

<2. Second Embodiment>
Next, a second embodiment of the present invention will be described. The information processing system 100 and the nonvolatile semiconductor memory device 110 in the second embodiment are compared with those in the first embodiment.
(1) The data structure of the block information storage table 151a stored in the first storage unit 51 of the nonvolatile semiconductor memory device 110 is different.
(2) The access processing executed by the memory control unit 120 is different,
Except for, the hardware configuration is the same as that of the first embodiment. Therefore, in the following, this difference will be mainly described.

  In the following description, the same components as those in the information processing system 1 and the nonvolatile semiconductor memory device 10 according to the first embodiment are denoted by the same reference numerals. Since the components with the same reference numerals have already been described in the first embodiment, description thereof will be omitted in the present embodiment.

<2.1. Configuration of Nonvolatile Semiconductor Memory Device>
The non-volatile semiconductor memory device 110 is a non-volatile memory that is readable and writable like the non-volatile semiconductor memory device 10 of the first embodiment, and that the stored content does not disappear even when the power supply is cut off. As shown in FIG. 1, the nonvolatile semiconductor memory device 110 mainly includes a memory array 15, a memory control unit 120, a diagnosis unit 40, a first storage unit 51, and a second storage unit 52. Yes.

  The diagnosis unit 40 diagnoses the access status to each block BL included in the memory array 15. As illustrated in FIG. 1, the diagnosis unit 40 mainly includes a first detection unit 41, a second detection unit 142, and a registration unit 145.

  The second detection unit 142 obtains an index value of the access status for each block other than the detected defective block after the first detection unit 41 detects the defective block (congenital defective block: first block). Further, the second detection unit 142 detects the block (second block) selected based on the index value as a refresh target block.

  Here, the refresh target block refers to a block that may cause a data read error due to deterioration of stored data due to repeated data reading on the same page of the same block. . Also, the refresh target block is likely to have the above-mentioned non-good quality cells. Furthermore, data deterioration is prevented by applying a refresh process for replenishing charges to a block or page including non-quality cells.

  Therefore, the second detection unit 142 of the present embodiment detects the refresh target block by the same method as the process of detecting the acquired defective block of the first embodiment. That is, the second detection unit 142 measures the time of data writing performed on each block BL by the memory control unit 120, similarly to the second detection unit 42 of the first embodiment. The written data writing time is used as an index value. In addition, the second detection unit 142 selects the refresh target block (second block) in order from the block BL having the largest measured index value. In addition, the memory control unit 120 executes a refresh process on the refresh target block at a predetermined timing. Thereby, it is possible to prevent a data reading error from occurring in each block.

  The registration unit 145 uses, as defective block information, information related to the defective block detected by the first detection unit 41 and information related to the refresh target block detected by the second detection unit 142 as refresh target block information for each block. Register in the block information storage table 151a.

  FIG. 7 is a diagram showing an example of the data structure of the block information storage table 151a in the present embodiment. The block information storage table 151a is a storage table that stores the defective block information selected according to the diagnosis result of the diagnosis unit 40 and the refresh target block. As illustrated in FIG. 7, the block information storage table 151 a includes, for example, fields of “ID”, “block NO”, and “type”.

  The “ID” field stores an identifier for uniquely identifying each record included in the block information storage table 151a. The “block NO” field stores an identifier for uniquely identifying the block BL constituting the memory array 15.

  In the “type” field, type information for specifying whether the information stored in each record relates to “bad block” or “refresh target block” is stored. Here, in the record with “type” = “BB”, information related to “bad block” is stored (for example, a record with “ID” = “1”). On the other hand, information regarding “refresh target block” is stored in the record in which “type” = “RB” (for example, record of “ID” = “M−1”).

  As a result, the memory control unit 120 refers to information registered in the block information storage table 151a by the diagnosis unit 40 in advance, so that (1) the defective block is excluded from the access target block and (2) the refresh target block The refresh process can be executed at a predetermined timing.

  The number of records stored in the block information storage table 151a (that is, the total number of bad block information and the number of refresh target block information) is the capacity of the memory array 15 and the total number of blocks BL included in the memory array 15. Is set to be a predetermined number M (M is a positive integer) according to. Thereby, the capacity of the block information storage table 151a can be set to a constant value instead of a variable value, and the hardware configuration of the first storage unit 51 can be facilitated.

<2.2. Detection procedure of defective block and refresh target block>
FIG. 8 is a flowchart for explaining the procedure for detecting a defective block and a refresh target block in the present embodiment. In this detection procedure, first, a detection process of a defective block (congenital defective block) is executed by the first detection unit 41 (S201). Information regarding the detected defective block is registered in the block information storage table 151a as defective block information (S202).

  Here, in step S202, “BB” indicating defective block information is stored in the “type” field (for example, a record of “ID” = “2” in FIG. 7). Also, registration of defective block information may be performed every time a defective block is detected, or may be performed after the defective block detection process is completed for all the blocks BL.

  Next, the second detection unit 142 performs a refresh target block detection process. That is, processing for measuring the data writing time for each block BL is executed (S203). Subsequently, the measured writing time is compared with the value of “writing time” already stored in the sort information storage table 52a (S204). If the measured writing time is larger than any of the registered “writing times”, the records having the measured writing time and block NO are sorted and registered in the sort information storage table 52a. (S205). On the other hand, if the measured writing time is smaller than or equal to any of the registered “writing times”, the process proceeds to step S206. The processes in steps S203 to S205 are executed until the measurement of the data writing time is completed for all the blocks in the memory array 15 (S206).

  When the measurement of the data writing time is completed for all the blocks, the data stored in the sort information storage table 52a is registered in the block information storage table 151a as the refresh target block in order from the block having the largest “writing time”. (S207), and this procedure ends. In step S207, “RB” indicating the refresh target block is stored in the “type” field.

<2.3. Advantages of Nonvolatile Semiconductor Memory Device of Second Embodiment>
As described above, the nonvolatile semiconductor memory device 110 according to the second embodiment can detect not only a defective block having a defective cell but also a refresh target block. As a result, the refresh target block can be the target of the refresh process. Therefore, it is possible to prevent a data reading error from occurring in each block.

<3. Modification>
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made.

  (1) In the first and second implementations, the second detection units 42 and 142 of the diagnosis unit 40 use the data writing time executed for each block BL of the memory array 15 as an index value. Although described as a thing, it is not limited to this.

  Here, as described above, there is a high possibility that a block that may become an acquired defective block includes a non-good quality cell. Further, as described above, if data reading is repeatedly performed on a block that may become an acquired defect block, the stored data may be deteriorated and a data reading error may occur. Further, the time required for erasing data stored in the block including the non-good quality cell is likely to be longer than that of the good quality cell, similarly to the data writing time.

  Therefore, the second detection units 42 and 142 may measure the time of data erasure performed on each block BL by the memory control units 20 and 120, and use this data erasure time as an index value. In this case, similarly to the case where the data writing time is used as the index value, the acquired defective block or the refresh target block (second block) is selected in order from the block having the long data erasing time.

  In order to ensure the reliability of the index value, the data erasure time measurement process is executed in the following procedure. That is, first, “00h” is written in all the cells in the block. Subsequently, an erasing process is executed, and a data erasing time T is measured. Here, the data erasing time is measured by the time t1 when the erasing control signal transitions from the “Ready” state to the “Busy” state and the time t2 when the erasing control signal transits from the “Busy” state to the “Ready” state. (See FIG. 3).

  (2) The total of the data writing time and the data erasing time may be used as the index value. Also in this case, by selecting in order from the block with the largest index value, it is possible to reliably detect a block or a refresh target block that may become an acquired defective block.

  (3) In the first embodiment, the information regarding the congenital defective block and the information regarding the acquired defective block have been described as being stored in the same block information storage table 51a. However, the present invention is not limited to this. Not a thing. Information on congenital bad blocks and information on acquired bad blocks may be stored in separate storage tables.

  In the second embodiment, the bad block information and the refresh target block information are described as being stored in the same block information storage table 151a. However, the present invention is not limited to this. The bad block information and the refresh target block information may be stored in separate storage tables.

  (4) Furthermore, in the second embodiment, the block information storage table 151a stores information on defective blocks and refresh target blocks, but the present invention is not limited to this. For example, the block information storage table 151a may store information on congenital bad blocks, acquired bad blocks, and refresh target blocks.

  That is, the second detection unit 142 sets (a) a block (second block) in which the index value (for example, data writing time) of the access status is in the first range as a block that may become an acquired defect block, (B) A block having a better access status (third block) is detected as a refresh target block as compared with a block that has an index value in the second range and may become an acquired defective block.

  As a result, the memory control unit 120 refers to the information registered in the block information storage table 151a by the diagnosis unit 40 in advance, thereby excluding the congenital and acquired defective blocks from the access target block ( b) The refresh process can be executed on the refresh target block at a predetermined timing. Therefore, it is possible to prevent a data reading error from occurring in each block while reducing the number of blocks that cannot be used as acquired defective blocks.

It is a figure which shows an example of the whole structure of the information processing system and the non-volatile semiconductor memory device in the 1st and 2nd embodiment of this invention. It is a figure for demonstrating the logic structure of a memory array. It is a timing chart for demonstrating the data writing time by a memory control part. It is a figure which shows an example of the data structure of the block information storage table in 1st Embodiment. It is a figure which shows an example of the data structure of the sort information storage table in 1st and 2nd embodiment. It is a flowchart for demonstrating the detection procedure of the congenital and acquired defect block in 1st Embodiment. It is a figure which shows an example of the data structure of the block information storage table in 2nd Embodiment. It is a flowchart for demonstrating the detection procedure of the defective block and refresh target block in 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,100 Information processing system 10,110 Nonvolatile semiconductor memory device 15 Memory array 20, 120 Memory control part 40 Diagnosis part 41 First detection part 42, 142 Second detection part 45, 145 Registration part 51 First storage part 51a, 151a Block information storage table 52 Second storage section 52a Sort information storage table BL block PG page

Claims (10)

(a) a memory array divided into a plurality of blocks;
(b) diagnosing the access status to each block included in the memory array, thereby detecting a defective block from the plurality of blocks; and
(c) a block information storage table in which information on the bad block is stored;
(d) a memory control unit that executes access processing to each block;
With
The memory array has a plurality of cells for storing data;
The diagnostic unit
(b-1) a first detection unit that detects a first block including a defective cell as a congenital defective block;
(b-2) a second detection unit that obtains an index value of the access status for each block other than the congenital defective block, and detects the second block selected based on the index value as an acquired defective block;
(b-3) A registration unit that registers information on the congenital defective block and the acquired defective block detected by the first and second detection units in the block information storage table as defective block information for each block. When,
Have
The memory control unit excludes the congenital defective block and the acquired defective block from the access target block based on the defective block information registered in the block information storage table by the diagnostic unit in advance. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The number of pieces of defective block information that can be stored in the block information storage table is equal to or less than a predetermined number corresponding to the total number of the plurality of blocks. (a) a memory array divided into a plurality of blocks;
(b) a diagnostic unit for diagnosing access status to each block included in the memory array;
(c) a block information storage table in which information about the block selected from the plurality of blocks according to a diagnosis result of the diagnosis unit is stored;
(d) a memory control unit that executes access processing to each block;
With
The memory array has a plurality of cells for storing data;
The diagnostic unit
(b-1) a first detector that detects a first block including a defective cell as a defective block;
(b-2) obtaining an index value of the access status for each block other than the bad block, and detecting a second block selected based on the index value as a refresh target block;
(b-3) The information regarding the defective block detected by the first detection unit is used as defective block information, and the information regarding the refresh target block detected by the second detection unit is used as refresh target block information. A registration unit for registering in the information storage table;
Have
The memory control unit is based on the defective block information and the refresh target block registered in the block information storage table by the diagnosis unit in advance.
(i) excluding the bad block from the access target block;
(ii) A nonvolatile semiconductor memory device, wherein refresh processing is executed on the refresh target block. The nonvolatile semiconductor memory device according to claim 3,
The total of the number of pieces of defective block information that can be stored in the block information storage table and the number of pieces of block information to be refreshed is equal to or less than a predetermined number corresponding to the total number of the plurality of blocks. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The index value is a time of data writing executed for each block by the memory control unit,
The non-volatile semiconductor memory device, wherein the second detection unit selects the second block in order from the block with the largest index value. The nonvolatile semiconductor memory device according to claim 5,
Each block has multiple pages,
The memory control unit executes a data writing process for each page,
The non-volatile semiconductor memory device, wherein the second detection unit uses a total data write time of each page included in a write target block as the index value. The nonvolatile semiconductor memory device according to claim 5,
Each block has multiple pages,
The memory control unit executes a data writing process for each page,
The non-volatile semiconductor memory device, wherein the second detection unit uses, as the index value, a maximum time among data writing times of each page included in the block. The nonvolatile semiconductor memory device according to claim 1,
The index value is a time of data erasure executed for each block by the memory control unit,
The non-volatile semiconductor memory device, wherein the second detection unit selects the second block in order from the block with the largest index value. The nonvolatile semiconductor memory device according to claim 1,
The index value is a total of data erasing time and data writing time executed for each block by the memory control unit,
The non-volatile semiconductor memory device, wherein the second detection unit selects the second block in order from the block with the largest index value. (a) a memory array divided into a plurality of blocks;
(b) a diagnostic unit for diagnosing access status to each block included in the memory array;
(c) a block information storage table in which information about the block selected from the plurality of blocks according to a diagnosis result of the diagnosis unit is stored;
(d) a memory control unit that executes access processing to the plurality of blocks;
With
The memory array has a plurality of cells for storing data;
The diagnostic unit
(b-1) a first detection unit that detects a first block including a defective cell as a congenital defective block;
(b-2) For each block other than the congenital defective block,
While obtaining the index value of the access status, the second block having the index value in the first range is detected as an acquired defect block,
A second detection unit that detects the third block as a refresh target block in which the index value is in the second range and the access status is good compared to the second block;
(b-3) Information regarding the congenital defective block and the acquired defective block detected by the first and second detection units is defined as defective block information, and the refresh target block detected by the second detection unit A registration unit for registering information as refresh target block information in the block information storage table,
Have
The memory control unit is based on the defective block information and the refresh target block registered in the block information storage table by the diagnosis unit in advance.
(i) excluding the congenital bad block and the acquired bad block from the access target block;
(ii) A nonvolatile semiconductor memory device, wherein refresh processing is executed on the refresh target block.

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