JP2000285001A - Semiconductor flash memory device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equalize the writing frequency set to a flash memory and to increase the lifetime of a semiconductor flash memory device by converting uniquely and updating the logical block address received from a host computer into a physical block address by means of two available parameters. SOLUTION: An interface part 1 stores temporarily the access request given from a host computer in a buffer memory 6 and sends it to an address arithmetic part 2. A control part 7 sends two available parameters stored in a register part 3 to the part 2, converts uniquely a logical block address into a physical block address with an arithmetic operation, accesses a data part 13 of a flash memory part 8 and expands plural defective block addresses and their paired substrate block addresses into an address reference table 5. Then a defective physical block address received from the part 2 is converted into a substitute block address by an address conversion part 4 and the data stored in the part 8 are updated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor flash memory device which can be erased at once, and more particularly to a semiconductor flash memory which achieves a longer life by equalizing the number of rewrites to a flash memory having a limited number of rewrites. The present invention relates to a memory device and a control method thereof.

[0002]

2. Description of the Related Art In a host computer system such as a personal computer or a work station, an external storage device for data processing is required to have a large capacity, a high speed, and a low cost per bit. In addition, portable information terminals such as notebook personal computers are required to be small, lightweight, resistant to physical impact, and low in power consumption.

Conventionally, a hard disk device (hereinafter referred to as an HDD) is provided in an external storage device such as the host computer.
And a floppy disk drive (hereinafter referred to as FDD) have been generally used. However, HDD has a large capacity,
Although the unit price per bit is low, it has a large volume and weight and has a driving part, so it is vulnerable to impact and is not suitable for carrying. On the other hand,
The FDD has a disadvantage that it has a small capacity and requires a driving device during operation, and therefore consumes a large amount of power.

In recent years, semiconductor memory cards such as SRAMs and DRAMs have been studied as an alternative, but these cards are volatile and require battery backup to retain data. Also, S
The RAM card has disadvantages in that the degree of integration is lower and the unit cost per bit is higher than that of the DRAM card. A DRAM card has a low unit cost per bit and a large capacity, but consumes a large amount of power during operation and data retention, and is not suitable for an external storage device of a portable device.

Recently, a semiconductor flash memory device (also referred to as a flash memory card) having a built-in flash EEPROM has been replaced with these external storage devices.
Is being used. This semiconductor flash memory device is non-volatile, rewritable, highly integrated and lightweight, and is configured with a semiconductor element. Since it has no driving portion, it has high impact resistance and is highly portable. Since data application is not required during data retention, power consumption is low.
It has a larger capacity than floppy disks.

[0006] Therefore, a semiconductor flash memory device using a flash EEPROM is most suitable as an external storage device of a portable device such as a notebook personal computer, a PDA, and an electronic still camera. However, flash EEPROMs have an inherent problem of limiting the number of rewrites.

When a host computer accesses an external storage device, the host computer accesses the external storage device via a file system such as an operation system or a card service or a socket service built in the host computer. In this case, the semiconductor flash memory device is an HDD
Is controlled to emulate. The minimum unit of the address accessed by the host computer system is called a sector and is 512 bytes of sequential data. This sector address is considered to be a continuous address starting from address 0 and continuing up to the specification value of the capacity of the external storage device.

In the current HDD file system, data is stored in an external storage device in units of files. A file consists of a data section and file management information (for example, FAT (File Allocation Table) and directory)
And stored on the disk. The data section is stored at a specified sector address for each file, and the capacity accessed at a time is generally a large sector. The number of accesses depends on the frequency of use of the file. However, the file management information collectively manages information on files in the entire HDD, and is stored at a specific sector address. Further, each time the file is accessed, the file management information is referenced, and each time a file is generated or deleted,
This file management information is rewritten. Therefore, although the data of the file management information has a small number of sectors, the number of accesses and the number of rewrites are overwhelmingly large as compared with the data part. In other words, in the file management information, management information on a plurality of files is concentrated, access to the sector where the file management information (FAT or directory) is located is concentrated, and the number of times of rewriting a specific sector is reduced. It will protrude.

Regarding the data portion of an individual file, the number of times of rewriting is often extremely different depending on the type of the file and the type of access by the application. A general program file or the like is mainly read, and may not be completely rewritten. Document data and the like are frequently rewritten. Further, temporary data called work data may be frequently rewritten while one application is operating. As described above, the number of rewrites is extremely different depending on the type of the file, the manner of use, and the attribute. In other words, the number of rewrites is different for each sector address accessed by the host computer.
There will be extremely concentrated sectors. As described above, the number of times of rewriting of the sector accessed by the host computer is extremely uneven for each sector address.

The limit on the number of rewrites of the flash memory of the batch erasure type has been increasing due to advances in semiconductor technology, but at present it is about 100,000 to 1,000,000 times in specifications. If used beyond this, writing / reading becomes difficult, and the block portion cannot be used.
On the other hand, as described above, when the host computer accesses the external storage device, there is a difference in the number of times of rewriting to each sector. As a result, the life of the device is limited by the sector that has been frequently rewritten.

The concept of avoiding this is to convert a sector address (referred to as a logical address) accessed by the host computer to a substantial sector address of the flash memory (referred to as a physical address). How to access. In converting a logical address into a physical address, this method refers to the number of times of rewriting for each physical address that has been accumulated, and preferentially writes to a physical address with a small number of times of rewriting. Tables have been used for address conversion methods. This table makes it possible to immediately refer to the physical address from the logical address. However, this table has a disadvantage that the table becomes larger as the memory capacity to be controlled increases.

The memory space for logical addresses, the memory space for physical addresses, the unit of address conversion, the outline of the address conversion table, and the operation will be described below.

FIG. 6 shows a logical sector specified by the host computer and an address space of a logical block related thereto. As shown in the figure, the basic unit of the address specified by the host computer is a logical sector which is 512-byte sequential data. In this logical sector, consecutive addresses are sequentially allocated from the head sector. Although not directly related to the host computer, it is divided into blocks for every 16 sectors for convenience. Similarly, consecutive addresses are sequentially allocated to the logical block from the head block. This means that the fifth bit or more of the address of the logical sector is the same as the logical block address.

FIG. 5 shows an address space of a physical sector and a physical block of the flash memory unit. Similarly,
The minimum address unit of the flash memory is a physical sector which is 528 bytes of sequential data. In this physical sector, consecutive addresses are sequentially allocated from the head sector. In addition, it is divided into physical blocks every 16 sectors. Similarly, consecutive addresses are sequentially allocated to the physical block from the head block. That is, the fifth bit or more of the address of the physical sector is equal to the physical block address. The 528-byte physical sector includes 512-byte data and 16-byte redundant data. The data of 512 bytes is the same as the data of the logical sector. The 16-byte redundant data is data uniquely used by the apparatus, and includes ECC (error correction code), address data of a logical block using the physical block, an integrated value of the number of rewrites of the block, physical sector or This is a flag indicating the state of the physical block. It is assumed that the information on the block is written in the redundant portion of the first sector in the block. It is also assumed that the information on the sector is written in the redundant part of each physical sector.

In the case of a flash memory, it is necessary to erase data in a write area before writing to a sector. The physical sector is a basic unit for writing / reading, and the physical block is a unit for performing erasing which is a characteristic unique to the flash memory. Therefore, the unit of writing differs from the unit of erasing. In this conventional example, a unit for converting a logical address into a physical address is a block address. Therefore, the logical block address is converted to the physical block address. The reason is that the unit of erase is block unit,
The number of times of rewriting is the same as the number of times of erasing, so that the number of times of rewriting can be managed in block units. It is an appropriate unit to optimize the size of the table used for conversion.

In the case of a 64 MB (megabyte) semiconductor flash memory device, it is composed of 128K physical sectors. The number of blocks is 8K. The sector address is allocated from 0 to 128K, and the fourth bit or more of the address becomes the block address.

FIG. 12 is a block diagram showing a conventional embodiment. As shown in FIG.
This is a circuit for implementing an interface protocol with a host computer (not shown). The command register stores an effective command (command) such as writing or reading from the host computer, the data register buffers data transfer, and the host A logical address register that temporarily stores a logical address that is the address of the data to be instructed. The logical address register includes a status register and an error register that notify the state of the semiconductor flash memory device and the contents of an error. The logical address register generally includes a sector register, a head register, a cylinder register, and the like. These registers are not shown.

The flash memory unit 8 is a main storage part of the semiconductor flash memory device for storing files and data in a nonvolatile manner.

The address conversion unit 20 is a unit for converting 5 bits or more of a logical sector address designated by the host computer system, that is, a logical block address into a physical block address.

Table 21 is an address conversion table 2
7. It is composed of three types of tables: a rewrite count accumulation table 26 and a block state table 25.

The control unit 7 comprises a microcontroller and corresponding hardware logic. When an access request is issued from a host computer, the control unit 7 converts a logical address into a physical address and executes data access to the flash memory unit 8. I do.

FIG. 13 shows an address conversion table of the conventional embodiment, and FIG. 14 shows a block state table of the conventional embodiment. In this conventional example, the block status table includes a rewrite frequency accumulation table.

The address conversion table is a table for referencing a physical block address from a logical block address when converting a logical block address into a physical block address. The address conversion table is a table in which addresses of physical block addresses corresponding to the order of the logical block addresses are stored over all the logical block addresses, and is configured by a volatile memory such as a DRAM or an SRAM. The operation reads the data of the physical block address at the address of the logical block address, and accesses the data of the flash memory unit according to this address.

In the block state table, in the order of the physical block address, the upper 30 bits store the integrated value of the number of rewrites of the block, and the lower 2 bits store the current state of the block as a flag. In this conventional example, every time rewriting, that is, erasing of a block occurs, the integrated value of the number of rewriting is incremented by +4, and the number of rewriting is incremented by +1. The state of the block is indicated by a 2-bit flag indicating the state of the erased, used, unerased, or bad block. By reading this, the corresponding block,
It is possible to determine whether or not the block is a bad block.

The logical block addresses of the address conversion table, the status flag of each physical block, and the number of rewrites used in the above description are read from the redundant portion of the first sector of each block on the flash memory at the time of power-on reset. Is expanded on the table. Specifically, 2-byte logical block address data and 4-byte state data (rewrite count and state flag) of a physical block are stored in the redundant portion of the first physical sector of each block. In order to expand the data into the table, the head sector of all physical blocks in the flash memory unit is read, and the data in the redundant unit is expanded into the table. When a block is erased or a new address is written, the table is updated and, at the same time, writing is performed on the redundant portion of the first sector of these blocks in the flash memory unit.

In the method of detecting a defective block, the defective block is detected at the time of erasing, writing, and reading operations. One specific example is read verify at the time of writing to the block. The data written in the block is read again and compared with the data remaining in the buffer memory. If they do not match, it is recognized that some error has occurred. Another specific example is
A method of adding a redundant bit at the time of writing and checking it at the time of reading to check the data consistency, such as an ECC (error correction code). If an error detection circuit or the like is built in the flash EEPROM chip product, the status signal in the flash EEPROM is read out after the write / erase operation to the flash EEPROM, so that the defect of the corresponding block can be known. Can be.

For the detected bad block, the status flag of the block is changed to the bad block status and stored in the block status table described above. During operation,
Access to the bad block is prohibited. In other words, control is performed so that assignment to the corresponding block in the address conversion table arranged in the order of the logical block addresses is prohibited. In addition, the defect of the block of the flash memory can be separated in units of the block address described above, and the spread to other blocks is restricted.

Here, the table size and the work memory size in the conventional example are set to a flash memory capacity of 4 MB.
Estimate (megabytes) and 160MB (megabytes). These memory sizes are proportional to the memory capacity of the semiconductor flash memory device.

As a precondition, the unit of address conversion is a block address. One physical block is 16 physical sectors. Since one sector is 512 bytes,
With a capacity of 4 MB (megabyte), 500 address units (500 blocks), and with a capacity of 160 MB (megabyte), 20,000 address units (20,000 blocks)
It is. The address translation table is
Since 9 to 14 bits are required, the unit used by a normal computer is 2 bytes or 16 bits. Therefore, for a 4MB device, 1K bytes, 160M
The device B requires an address conversion table of 40 Kbytes.

Similarly, the block state table has 32 bits to represent the specification value of the number of rewrites of 1,000,000 times. Therefore, for a 4 MB device, 2 Kbytes, 16
For a 0 MB device, 80 Kbytes are required. The total amount of both tables is the work memory capacity,
They are 3K bytes and 120K bytes, respectively.

As described above, the size of the work memory increases in proportion to the capacity of the semiconductor flash memory device, and accordingly, the power consumption increases, the number of parts increases, and the like.
This leads to increased costs. A method of creating and using only tables in the required area by tiering or splitting the table may be considered, but the control becomes complicated, and the overhead involved in moving the tier must be taken into account. Absent.

[0032]

The present invention relates to a semiconductor flash memory device, and more particularly to a semiconductor flash memory device having a limited number of times of rewriting, capable of reducing the number of times of rewriting and replacing defective blocks at a low cost with a small work memory. This is to provide a method for realizing it.

A further object is to reduce the amount of data in the management information area, reduce the number of rewrites of the management information, and consequently collectively manage the management information, and to store the management information in the work memory at power-on. It is possible to shorten the start-up time related to deployment.

[0034]

The principle of the present invention is described below.
This will be described with reference to FIG.

The same or corresponding parts as those described in the description of the conventional example are denoted by the same reference numerals, and the parts newly described in the present description will be described with the new reference numerals.

In a semiconductor flash memory device of a type which can be connected to a host computer system (not shown) and can be addressed in units of blocks, it comprises an electrically writable and readable non-volatile memory. , A flash memory unit 8 having a built-in data unit and a substitute data unit 13, an interface unit 1 connected to the host computer system for receiving and transmitting data and receiving an access request, and a volatile work memory. A buffer memory unit 6 for temporarily storing data of the flash memory unit 8 and data received from the host computer, a first variable parameter for displacing a logical block address,
An address operation unit configured to uniquely calculate and convert a logical block address to a physical block address using a second variable parameter indicating a position of a blank area, and a volatile work memory; A register unit 3 for storing the two variable parameters used in the unit 8; and a defective block address reference table comprising a volatile work memory and storing a physical block address of a defective block and its alternative block address in pairs. 5 and the physical block address output from the address operation unit 2 is checked as to whether or not it is a bad block by using the address reference table 5. If the block addresses match, a related alternative block is checked. Address conversion unit 4 for outputting an address, and management in the flash memory unit 8 Means for expanding the two variable parameters collectively stored in the report unit 10, a plurality of defective block addresses and alternative block addresses forming a pair thereof in the register unit 3 and the address reference table 5, Then, the second variable parameter is subtracted by a fixed amount, and at the same time, data of a fixed width on the flash memory 13 and data of the blank area are exchanged. Further, when the value of the second variable parameter matches the value of the first variable parameter, the value of the first variable parameter is further added by a fixed amount. Further, it comprises a means for updating the management data of the management information section 10 at regular intervals, a microcontroller and corresponding hardware logic, and when an access request is made from a host computer, the logical block address is changed to the physical block address. Convert,
A semiconductor flash memory device comprising a control unit for executing access to a data unit of the flash memory unit.

[0037]

According to the semiconductor flash memory device and the control method thereof according to the present invention, a logical block address specified by a host computer can be uniquely converted into a physical block address by two variable parameters. As a result, a logical block address-physical block address conversion table for all logical block addresses and a rewrite frequency data table for every physical block address, which are required in the conventional example, are not required.

Conversely, the only table to be added is an address conversion table which is a pair of a defective block address and a substitute block address, and the number of tables is reduced to one. Further, the table size depends on the number of defective blocks, so that the work memory is greatly reduced.

There are two types of management information sections: the two variable parameters and the address conversion table. The former is updated at regular intervals such as at power-on, and the latter is updated when a bad block occurs. The number of rewrites to the management information area of the flash memory unit is smaller than the limit of the number of rewrites to the flash memory data area. It can be held down to a sufficiently low number.

The occurrence of a bad block is about 2% of the total physical block address at maximum, and the data amount of the management information is a pair of the address of the bad block and its replacement address, which is a sufficiently small amount. Are collectively saved in a flash memory unit, which is a nonvolatile memory, and can be easily managed.

In the conventional example, the management information is distributed and stored in the redundant portion of the first sector of each block in the flash memory unit. Therefore, at the time of power-on reset, the management information is read over the entire data area of the flash memory, and is developed in a table on the work memory. In the present invention, the management information is stored collectively in a single block. Therefore, at the time of power-on reset, the operation can be performed immediately by reading the management information stored in a single block and expanding it on the work memory. Therefore, the startup time at the time of turning on the power is greatly reduced.

Further, as the work memory is reduced, the current for holding the data is reduced.

[0043]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 4 shows a hardware configuration diagram of the embodiment of the present invention. Semiconductor flash memory device 10
0 is positioned as one of the external storage devices of the host computer (not shown).

The semiconductor flash memory device 100 includes a microcontroller 60, a work memory 70, an interface circuit 50, a buffer memory 6, a memory controller 80, and a plurality of flash memory modules 90. The internal bus 40 is a common signal transmission path for interconnecting the components in the semiconductor flash memory device 100, and is composed of an address bus, a data bus, a control bus, and the like.

The interface circuit 50 is a circuit for realizing an interface protocol with the host computer, a command register for storing execution commands (commands) such as writing and reading from the host computer, and data for buffering data transfer. A register, an address register for temporarily storing a logical address which is an address of data designated by the host computer (including a status register for notifying the state of the semiconductor flash memory device 100 and contents of an error, and an error register. The registers are directly accessible by the host computer and the microcontroller 60.
These registers are not shown.

The interface circuit 50 is provided with an IDE
(Integrated Drive Electro
nics) or the PCMCIA ATA specification and the ISA bus or P of the host computer system.
Interconnected to the CMCIA bus.

The microcontroller 60 is a central controller for controlling the entire semiconductor flash memory device 100. The main control is to read commands written to the interface circuit 50 from the host computer,
The main operations such as writing to the flash memory 90 and reading from the flash memory 90 are performed. The microcontroller 60 has a built-in program ROM.
(Not shown). In addition, it performs an operation related to conversion from a logical block address to a physical block address and performs conversion from a bad block to a substitute block address. Also, execution of the main means of the present invention described later is controlled. As a specific example, the update of two variable parameters used to convert a logical block into a physical block and the movement of partial data are controlled in a fixed period such as a power-on reset. Further, the state of the block is inspected, and when a bad block occurs, updating of the address reference table of the bad block is controlled. For details of the control, refer to the description of the following embodiments.

The work memory 70 is a DRAM or an SRAM.
, And is mainly used as a work area of the microcontroller 60. In addition, the work memory 70 temporarily stores parameters used for calculating and converting a logical block address into a physical block address during operation, and stores a table of addresses of defective blocks and addresses of replacement blocks. I have.

The buffer memory 6 is an SRAM or DRA
M is a volatile memory such as M, and is a temporary storage of data transferred between the host computer and the flash memory 90.

The memory controller 80 is a dedicated controller composed of a logic circuit or the like, and controls access to the flash memory 90. Specifically, AL
A circuit for controlling E (address latch enable), CLE (command latch enable), and a CS (chip select) signal for controlling a plurality of flash chips is incorporated. In addition, an ECC (error correction code) is incorporated in the redundant portion of the flash memory 90.
The generation of the CC, the inspection of the ECC at the time of reading, the error determination and the like are also incorporated in the memory controller 80.

The flash memory 90 is a main storage part of the semiconductor flash memory device 100 for storing files and data in a nonvolatile manner. The flash memory 90 is composed of a plurality of flash EEPROM chips. The capacity in the case of a 64 megabyte flash memory card (one form of a semiconductor flash memory device) refers to the capacity of this flash memory 90. 64M
With a capacity of B (megabytes), there are 16 32-megabit flash EEPROM chips.

The flash memory 90 is connected to the microcontroller 60, the work memory 70, the buffer memory 6, and the interface circuit 50 via the memory controller 80 via the internal bus 40.

FIG. 6 schematically shows the structure of a logical memory space when the host computer emulates an external storage device, particularly an HDD. This logical memory space is first divided into units called “blocks”. Each block is continuously assigned an absolute logical block address in order from the first block in the logical memory space. Each block is composed of 16 logical sectors. Each logical sector is assigned an absolute logical sector address in order from the first sector in the logical memory space. One logical sector is 512 bytes of sequential data. The host computer system is
The access destination on the physical memory can be specified by the logical sector address. A logical block is a basic unit for converting a logical address into a physical address. Therefore, the higher order bit of the fifth bit or more of the logical sector address matches the address of the logical block. The concept of a logical block is an address system for controlling the present apparatus, and the host computer does not detect this.

FIG. 5 schematically shows the structure of the physical memory space of the semiconductor flash memory device. This physical memory space, like the logical memory space,
It is divided into units called "blocks". A physical block address is continuously allocated to each block in order from the first block in the physical memory space.

Each physical block is composed of 16 physical sectors. Each physical sector is assigned a physical sector address sequentially from the top physical sector in the physical memory space, similarly to the physical block.
That is, the bit configuration of the fifth bit or more of the physical sector address is the same as the bit configuration of the physical block address.

The flash memory chip used in this embodiment performs an erasing operation in units of blocks and performs a writing / reading operation in units of physical sectors. Therefore, erasing specifies a physical block address, and writing and reading specifies a physical sector address.

One physical sector is 528 bytes long, and is composed of two fields: a data part of 512 bytes and a redundant part of 16 bytes. In the data section, the substance of the data accessed by the host computer is written.
The redundant part is an ECC (Error Correction Code (Error C)
correction code)) is written. By reading out the error correction code and the data portion together, the presence or absence of an error in the data portion and the error correction of one or more bits can be performed.

In short, in the present embodiment, the memory space is managed by grouping the logical address space and the physical address space into a group called a block as well as a minimum unit of an address called a sector. By adopting such a hierarchical structure, writing and reading can be performed in the minimum unit of a sector, and erasing of a physical block can be directly addressed by specifying a physical block address. Also,
The number of times of rewriting of the flash memory is the same as the number of times of erasing of the flash memory, and a unit called a block is a unit of erasing of the flash memory. Therefore, in order to equalize the number of times of rewriting of the flash memory, it is also an address unit for converting a logical address into a physical address.

Note that the method of layering the memory space such as blocks and sectors, the block size, the sector size, and whether the erasure unit is a block size or a sector size are merely design items of the present embodiment. The gist of the present invention is not directly limited. It should be understood that the present invention can be suitably implemented even when the memory space is hierarchized in another manner or when the physical size of each hierarchy is different.

As described in the conventional example, in the host computer system, input and output of files and data are controlled by the file system in the operating system. According to the file system, access destinations by applications tend to be locally concentrated. on the other hand,
The number of times of rewriting of each physical sector of the flash memory is limited, and by equalizing the number of times, the life of the device can be extended.

FIG. 7 is a schematic diagram showing a case where a logical memory space is mapped to a physical memory space. Since mapping is performed in block address units, in the following description, all address units are block addresses.
In the figure, the logical block address space has, in addition to the address space opened to the host computer, the address space of a virtually allocated replacement block on a continuous address, so that the replacement of a defective block can be efficiently performed. Structure.

The physical address space has a data portion and a substitute data portion having the same capacity as the logical address space. In addition, it has a special blank area. The width of this blank area is composed of a single block or a plurality of blocks. Since these three areas move, the physical addresses are not fixed. Also,
The physical address space is larger than the logical address space by a blank area.

There is a management information area (not shown) in the physical block address space other than the above description. In the management information area, the last single or multiple physical blocks in the physical address space are used, and the data of the defective black address and the substitute block address which are developed in the address conversion table of the defective block and the logical address-physical address conversion Are stored together with two variable parameters used for the operation, and a parameter indicating the number of defective blocks and the address position of an empty replacement block for allocating a replacement block when a new bad block occurs. I have.

The concept of mapping related to address conversion in the present invention will be described with reference to FIG. According to the figure, the start address of the logical block address is set to the start address of the physical block address, that is, the address specified by the first variable parameter described in the claims. Further, a blank area having a constant width exists on the physical block address. The address pointing to this blank area is the blank address, which is also the value of the second variable parameter as defined in the claims. The mapping is to develop the logical block address continuously from the start address of the physical block. If there is a blank area on the way, it jumps over that area and performs mapping. For logical blocks exceeding the maximum address of a physical block, mapping is performed continuously from address 0 of the physical block.

As shown in the figure, the logical block address is virtually provided with two used and unused alternative block areas in addition to the address area opened to the host computer. In this area, the logical block address is similarly mapped to the physical block address. It is assumed that a newly generated bad block is allocated from an index position of an address indicating an unused replacement block.

The address operation section is a section for calculating and converting a logical block address into a physical block address. In the conversion, the microcontroller reads the logical block address, calculates and outputs the logical block address. FIG. 8 shows a schematic diagram of the actual address calculation. As shown in the figure, the calculation first changes from the relative positional relationship between the start address and the address indicated by the blank address. When the blank address is larger than the start address, Formula 1 is applied to the area from the start address to the blank address. Similarly, the calculation formula 2 is applied to the address beyond that. In the case of the maximum physical block address or more, the calculation formula 3 is applied. Similarly, when the start address is smaller than the blank address, the calculation formulas 4, 5, and 6 shown in FIG.

Here, assuming that start address = a blank address = b maximum physical block address = z blank width = m logical block address = x physical block address = y, the respective conditions and formulas are as follows.

Condition 1: (a <b) and (x <= (ba)) Formula 1: y = x + a Condition 2: (a <b) and ((ba) <x <= (z −
az)) Formula 2: y = x + a + m Condition 3: (a <b) and (x> (za)) Formula 3: y = x + a + mz Condition 4: (a> b) (X <= (za)) Formula 4: y = x + a Condition 5: (a> b) and ((za) <x <= (z-
a + b)) Formula 5: y = x + a-z Condition 6: (a> b) and (x> (za-b)) Formula 6: y = x + a-z + m Also, the logical block address is calculated by a microcontroller or the like. FIG. 9 shows a flowchart in the case of calculating and converting to a physical block address. In this example, up to 6
Condition determination and address calculation are executed. It is assumed that data during the operation is kept stored in the internal register of the microcontroller.

To start the address calculation, the start address is added to the logical block address, and the result is held (step S201).

Next, the start address and the blank address are compared (step S202). This operation can be calculated in advance. If the start address is smaller than the blank address, step S203
Run. Conversely, if the start address is larger than the blank address, execute step S208.

If the calculation result of step S201 is smaller than the blank address, the physical block address becomes the calculation result of step 201 (step S207).
The process ends here. Conversely, if the calculation result of step S201 is larger than the blank address, step S20
Add the width of the blank to the calculation result of 1, save the result,
Next, execute step S205.

If the calculation result of step S204 is within the maximum physical block address, the physical block address becomes the result of step S204 (step S20).
7). The process ends here. Conversely, when the calculation result of step S204 is equal to or greater than the maximum physical block address, the physical block address is a value obtained by subtracting the maximum physical block address from the calculation result of step S204 (step S206). The process ends here.

Next, in step S208, step S208
If the calculation result of 201 is smaller than the maximum physical block address, the physical block address becomes the calculation result of step S201 (step S207). The process ends here. Conversely, if the calculation result of step S201 is larger than the maximum physical block address, the maximum physical block address is subtracted from the calculation result of step S201, the result is stored, and step S210 is executed (step S20).
9).

In the next step S210, step S2
If the result of calculation in step 09 is within the blank address, the physical block address is the result of calculation in step S209 (step 207). The process ends here. Conversely, if it is equal to or greater than the blank address, the physical block address is
The result is the value obtained by adding the blank width to the calculation result in step S209 (step S211). The process ends here.

FIG. 10 illustrates the transition of mapping of logical block addresses in the physical memory space. In the figure, from the left, the initial state at the time of shipment from the factory, the state during use, and the state after the variable parameter is updated once in a fixed cycle such as power-on reset.

In the initial state at the time of factory shipment, the start address is set to the physical block address 0. Therefore, the logical blocks are successively developed from the head block of the physical block. The blank is set at the end of the physical block address space. When the update is performed at a constant interval, the blank address falls by a fixed width. At the same time, the blank and the data immediately before the blank address are exchanged. When the blank address matches the start address, the start address increases by a certain width. This fixed width is the same as the width of the blank.

In the middle of the figure, a state during use is shown. At the same time, the left side of the figure shows a state in which the variable parameter is updated once every fixed period from the above-mentioned halfway state. As shown in the figure, the blank next to the logical address 32 is lowered by a certain width, and the data at the logical address 32 and the blank are exchanged.

As described above, the blanks are generated at regular intervals.
It descends by a certain width, and the blank address also moves. When the blank address moves and matches the start address, the start address is increased by a certain width.
Here, the moving direction of the blank is downward, but if it is controlled as rising, the blank address rises accordingly, and if the blank address and the start address match, the start address is controlled to fall reversely. I will do it. In the description in the figure, the width of the blank is one block address.

As described above, when the blank address makes one round of the entire physical block address space, the start address is updated once, and this is repeated, so that the start address makes one round of the entire physical block address space. During this time, data in the flash memory is rewritten according to an access request from the host computer.

Looking at the transition by focusing on the logical address 32 shown in FIG. 10, while the blank address makes one round, it moves to the next physical block with data.
While the start address makes one round, the logical address 32 of the logical block accesses all the physical blocks for a certain period. This is true for all logical addresses. In other words, each physical block address has accessed all the logical block addresses for a certain period of time, and this means that the uneven access times of each logical block have been made uniform on the physical block.

In the above description, the logical block address is uniquely converted to the physical block address, and the number of times of rewriting to the physical block is made uniform. Here, an embodiment in the case where a physical block becomes defective will be described. As described in the conventional example, the defective block can be detected by the ECC circuit, the reading and determination of the status signal of the flash chip, and the read verify.

The detected bad blocks are respectively
An alternative block is allocated. These defective physical block addresses and replacement block addresses are stored in pairs in the address reference table. Also, the data of the management information section of the flash memory section storing the same data as the table is updated. When the system is started by a power-on reset or the like, the information is returned from the management information section of the flash memory section to the address reference table of the defective block composed of the volatile memory.

When the host computer accesses the flash memory, it first converts a logical block address into a physical block address. Next, this physical block address is compared with the addresses of all the defective blocks in the address reference table of the defective block, and if they match, the access is controlled using the alternative block address stored in the table. .

In this case, the substitute block address is
This is the logical block address of the virtual area. The logical block address is again calculated and converted into the physical block address. This allows the replacement block to:
This makes it easy to achieve a uniform number of rewrites.

FIG. 11 shows an address reference table of a defective block. This dress reference table stores a block address of a defective block and a replacement block address in pairs. Also, to make searches faster,
Sorted in physical block address order. Control can be performed at high speed from the beginning to the end of the address data of the bad block using a technique such as binary sorting. The size of the table depends on the amount of bad blocks generated, but is usually around 2% of normal blocks. Therefore, the table size can be significantly reduced as compared with the case where the logical address-physical address conversion table is created.

An estimation is performed under the same conditions as the estimation of the work memory size shown in the conventional example. The size of the work memory varies depending on the capacity.
Estimate the capacity of the work memory at 60 MB.

The size of each block address is
There are 500 addresses and 20,000 addresses. If the maximum number of defective blocks is designed to be 2% of all blocks, the number of defective block address tables becomes 10 blocks and 400 blocks, respectively. Since the address of the bad block and its replacement address are each composed of 2 bytes, the size of the table is 40 bytes and 1600 bytes, respectively. It is reduced to about 1/50 as compared with the conventional example. In addition, data to be stored in the management area of the flash memory unit, which is a nonvolatile memory, includes a first variable parameter, a second variable parameter,
In addition, a pointer indicating the start address of an unused replacement block and a parameter 4 indicating the number of defective blocks
Seed, totaling about 8 bytes.

[0089]

As is clear from the above description, the address conversion table for converting the logical address to the physical address and the table of the integrated value of the number of rewrites of the physical block, which are required in the conventional example, are simply two. Can be replaced by two variable parameters, and the size of the work memory is about 5
It can be reduced to 1/0.

Further, the amount of management information that needs to be saved in the non-volatile memory is greatly reduced.
Since it is a fixed period such as a power-on reset or a limited period and the number of times when a defective block occurs, it is possible to manage them collectively on the flash memory. Along with that, in the conventional example, compared to reading the management information distributed and stored in the redundant portion on the flash memory,
By reading the collectively managed management information from the designated block, it is possible to reduce the time required to load the power-on management information into the work memory, that is, the time required for initialization.

Further, the reduction in the work memory leads to a reduction in the power consumption associated with data retention in the work memory and a reduction in the cost associated with the work memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment according to the present invention.

FIG. 2 is a block diagram showing one embodiment according to the present invention.

FIG. 3 is a block diagram showing one embodiment according to the present invention.

FIG. 4 is a hardware configuration diagram showing an embodiment according to the present invention.

FIG. 5 is an explanatory diagram of a physical memory space according to the present invention.

FIG. 6 is an explanatory diagram of a logical memory space according to the present invention.

FIG. 7 is an explanatory diagram of mapping of a block address in a memory space according to the present invention.

FIG. 8 is a schematic diagram of an address operation according to the present invention.

FIG. 9 is a flowchart of an address operation according to the present invention.

FIG. 10 is a transition diagram of a logical block address in a physical block space according to the present invention.

FIG. 11 is an explanatory diagram of a defective block address reference table according to the present invention.

FIG. 12 is a block diagram showing a conventional example.

FIG. 13 is a diagram showing an address conversion table according to a conventional embodiment.

FIG. 14 is a state table diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Interface part 2 Address calculation part 3 Register part 4 Address conversion part 5 Address reference table 6 Buffer memory part 7 Control part 8 Flash memory device 10 Management information part 11 Data part 12 Substitution area 12 Data part + substitution area 20 Address conversion part ( Conventional example) 21 Table (conventional example) 25 Block state table 26 Rewrite count reference table 27 Address reference table 50 Interface circuit 60 Microcontroller 70 Work memory 80 Memory controller 90 Flash memory

Claims (5)

[Claims] 1. A semiconductor flash memory device of a type which is connected to a host computer system and can be addressed in units of blocks, comprising a nonvolatile memory which can be electrically written and read, a management information section, and a blank area. Comprising a flash memory unit having a built-in data unit, a substitute data unit, an interface unit connected to the host computer system to receive and receive data and an access request, and a volatile work memory, A buffer memory unit for temporarily storing data of the flash memory unit or data received from the host computer, a first variable parameter for giving an address displacement when converting a logical block address to a physical block address, Indicates the location of the blank area in the physical memory space Use the be the second of variable parameters,
An address operation unit for uniquely calculating and converting a logical block address to a physical block address, a register unit configured with a volatile work memory and storing the two variable parameters used in the address operation unit, A control unit which is constituted by a controller and corresponding hardware logic and executes main means of the present apparatus, such as access to data in the flash memory unit when an access request is issued from a host computer; The above 2 which is collectively stored in the management information section
Means for expanding the two variable parameters in the register section of the volatile work memory; and, at regular intervals, subtracting a constant amount of the second variable parameter, and at the same time, a fixed width data and a blank area on the flash memory section. And, if the value of the second variable parameter and the value of the first variable parameter match, add a fixed amount of the value of the first variable parameter, A semiconductor flash memory device comprising means for storing in a management information section of the flash memory section. 2. A semiconductor flash memory device which is connected to a host computer system and can be addressed in units of blocks, comprising a nonvolatile memory which can be electrically written and read, a management information section, and a blank area. Comprising a flash memory unit having a built-in data unit, a substitute data unit, an interface unit connected to the host computer system to receive and receive data and an access request, and a volatile work memory, A buffer memory unit for temporarily storing data of the flash memory unit or data received from the host computer, a first variable parameter for giving an address displacement when converting a logical block address to a physical block address, Indicates the location of the blank area in the physical memory space Use the be the second of variable parameters,
An address operation unit for uniquely calculating and converting a logical block address into a physical block address, a register unit configured with a volatile work memory and storing the two variable parameters used in the address operation unit, An address reference table, which is constituted by a work memory of different types and stores a bad block physical address and its substitute block address in pairs, and determines whether or not the physical block address output from the address operation unit is a bad block address. Inspection at any time using the address reference table,
An address conversion unit that outputs a related alternative block address when the block addresses match, and a physical block address that is an output of the address calculation unit,
The data unit of the flash memory unit is accessed, and the substitute block address is constituted by an access unit for accessing the substitute data unit of the flash memory unit, a microcontroller and corresponding hardware logic, and an access request is issued from a host computer. A control unit that executes the main means of the present apparatus, such as access to data in the flash memory unit when there is an error, and the two variable parameters stored collectively in a management information unit in the flash memory unit. Means for developing a plurality of defective block addresses and alternative block addresses forming a pair with the defective block addresses in the register section and the address reference table of the volatile work memory; Subtraction and at the same time a fixed width on the flash memory Data and a blank area, and when the value of the second variable parameter matches the value of the first variable parameter, the value of the first variable parameter is further added by a fixed amount. A semiconductor flash memory device comprising: means for storing two variable parameters in a management information section of the flash memory section. 3. A semiconductor flash memory device which is used in connection with a host computer system and is addressable in a block unit, comprising a nonvolatile memory which can be electrically written and read, a management information section,
A data memory, a flash memory unit containing a substitute data unit and a blank area, an interface unit connected to the host computer system to receive and transmit data and receive an access request, and a volatile work memory; A buffer memory unit for temporarily storing data of the flash memory unit and data received from the host computer, a first variable parameter for giving an address displacement when converting a logical block address into a physical block address, , Using a second variable parameter that points to the location of the blank area in physical memory space,
An address operation unit for uniquely calculating and converting a logical block address into a physical block address, a register unit configured with a volatile work memory and storing the two variable parameters used in the address operation unit, An address reference table, which is constituted by a work memory of different types and stores a bad block physical address and its substitute block address in pairs, and determines whether or not the physical block address output from the address operation unit is a bad block address. Inspection at any time using the address reference table,
An address conversion unit for outputting a related alternative block address when the block addresses match, an address latch for temporarily storing the alternative block address and feeding back to perform an address operation again; A control unit configured with a controller and corresponding hardware logic, and executing main means of the present apparatus, such as accessing data in a flash memory unit when an access request is issued from a host computer;
The two variable parameters, which are collectively stored in a management information section in the flash memory section, and a plurality of defective block addresses and a replacement block address paired therewith are stored in the register section of the volatile work memory and Means for developing in an address reference table, for every fixed period, subtracting a fixed amount of the second variable parameter, and simultaneously exchanging a blank area with data of a fixed width on the flash memory unit; If the value of the variable parameter matches the value of the first variable parameter, the value of the first variable parameter is further added by a fixed amount, and these two variable parameters are added to the management information section of the flash memory section. A semiconductor flash memory device comprising means for storing. 4. The means according to claim 1, wherein said second variable parameter is added at a constant interval for a constant amount, and simultaneously with data of a constant width on said flash memory unit. Exchanging a blank area, and when the value of the second variable parameter matches the value of the first variable parameter, further subtracts a fixed amount of the value of the first variable parameter, and A semiconductor flash memory device comprising means for storing parameters in a management information section of the flash memory section. 5. An address conversion unit for replacing a defective block according to claim 2 or 3, reading data of the block and analyzing the data of the block as a defective block detection procedure. And a control method for the semiconductor flash memory device, which detects block address coincidence and outputs an alternative block address.